X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=target_firmware%2Fwlan%2Fif_ath.c;h=b31fbdb67e866d883732f14ca4171515015bbfbd;hb=83dd3bf0aae9da59ecb39852500f5e25adddef27;hp=3cc61f7f29f094db4f2fa358e7668a0de3ba70ab;hpb=28d5112c4933b4b26e1744ebd2411755865004c0;p=open-ath9k-htc-firmware.git diff --git a/target_firmware/wlan/if_ath.c b/target_firmware/wlan/if_ath.c index 3cc61f7..b31fbdb 100755 --- a/target_firmware/wlan/if_ath.c +++ b/target_firmware/wlan/if_ath.c @@ -56,6 +56,8 @@ #include "if_athvar.h" #include "ah_desc.h" #include "ah.h" +#include "ratectrl.h" +#include "ah_internal.h" static a_int32_t ath_numrxbufs = -1; static a_int32_t ath_numrxdescs = -1; @@ -82,26 +84,36 @@ void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf); void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host); /* - * Extend a 32 bit TSF to 64 bit, taking wrapping into account. + * Extend a 32 bit TSF to nearest 64 bit TSF value. + * When the adapter is a STATION, its local TSF is periodically modified by + * the hardware to match the BSS TSF (as received in beacon packets), and + * rstamp may appear to be from the future or from the past (with reference + * to the current local TSF) because of jitter. This is mostly noticable in + * highly congested channels. The code uses signed modulo arithmetic to + * handle both past/future cases and signed-extension to avoid branches. + * Test cases: + * extend(0x0000001200000004, 0x00000006) == 0x0000001200000006 + * extend(0x0000001200000004, 0x00000002) == 0x0000001200000002 + * extend(0x0000001200000004, 0xfffffffe) == 0x00000011fffffffe ! tsfhigh-- + * extend(0x000000127ffffffe, 0x80000002) == 0x0000001280000002 + * extend(0x0000001280000002, 0x7ffffffe) == 0x000000127ffffffe + * extend(0x00000012fffffffc, 0xfffffffe) == 0x00000012fffffffe + * extend(0x00000012fffffffc, 0xfffffffa) == 0x00000012fffffffa + * extend(0x00000012fffffffc, 0x00000002) == 0x0000001300000002 ! tsfhigh++ */ static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp) { struct ath_hal *ah = sc->sc_ah; u_int64_t tsf; u_int32_t tsf_low; - u_int64_t tsf64; + a_int64_t tsf_delta; /* signed int64 */ tsf = ah->ah_getTsf64(ah); - tsf_low = tsf & 0xffffffff; - tsf64 = (tsf & ~0xffffffffULL) | rstamp; + tsf_low = tsf & 0xffffffffUL; - if (rstamp > tsf_low && (rstamp - tsf_low > 0x10000000)) - tsf64 -= 0x100000000ULL; + tsf_delta = (a_int32_t)((rstamp - tsf_low) & 0xffffffffUL); - if (rstamp < tsf_low && (tsf_low - rstamp > 0x10000000)) - tsf64 += 0x100000000ULL; - - return tsf64; + return (tsf + (u_int64_t)tsf_delta); } static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode) @@ -317,13 +329,11 @@ static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc) a_int32_t retval; a_uint32_t cnt = 0; a_uint16_t frame_len = 0; - a_uint64_t tsf; #define PA2DESC(_sc, _pa) \ ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) - tsf = ah->ah_getTsf64(ah); bf = asf_tailq_first(&sc->sc_rxbuf); ds = asf_tailq_first(&sc->sc_rxdesc); @@ -574,9 +584,7 @@ static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr, struct ath_tx_buf *bf; a_uint8_t vap_index, *anbdata; ath_beacon_hdr_t *bhdr; - struct ieee80211vap_target *vap; a_uint32_t anblen; - struct ieee80211_frame *wh; if (!bc_hdr) { adf_nbuf_peek_header(nbuf, &anbdata, &anblen); @@ -587,10 +595,8 @@ static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr, vap_index = bhdr->vap_index; adf_os_assert(vap_index < TARGET_VAP_MAX); - vap = &sc->sc_vap[vap_index].av_vap; - wh = (struct ieee80211_frame *)adf_nbuf_pull_head(nbuf, - sizeof(ath_beacon_hdr_t)); + adf_nbuf_pull_head(nbuf, sizeof(ath_beacon_hdr_t)); bf = sc->sc_vap[vap_index].av_bcbuf; adf_os_assert(bf); @@ -864,7 +870,6 @@ static void ath_descdma_cleanup(struct ath_softc_tgt *sc, ath_bufhead *head, a_int32_t dir) { struct ath_buf *bf; - struct ieee80211_node_target *ni; asf_tailq_foreach(bf, head, bf_list) { if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) { @@ -882,7 +887,6 @@ static void ath_descdma_cleanup(struct ath_softc_tgt *sc, adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap); - ni = bf->bf_node; bf->bf_node = NULL; } @@ -1094,9 +1098,9 @@ static void ath_enable_intr_tgt(void *Context, A_UINT16 Command, { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; - a_uint32_t intr; + a_uint32_t intr = 0; - if (data) + if (datalen == 4) intr = (*(a_uint32_t *)data); intr = adf_os_ntohl(intr); @@ -1384,17 +1388,17 @@ static a_int32_t ath_reg_read_filter(struct ath_hal *ah, a_int32_t addr) { if ((addr & 0xffffe000) == 0x2000) { /* SEEPROM registers */ - ath_hal_reg_read_target(ah, addr); + ioread32_mac(addr); if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) adf_os_print("SEEPROM Read fail: 0x%08x\n", addr); - return (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff); + return ioread32_mac(0x407c) & 0x0000ffff; } else if (addr > 0xffff) /* SoC registers */ - return HAL_WORD_REG_READ(addr); + return ioread32(addr); else /* MAC registers */ - return ath_hal_reg_read_target(ah, addr); + return ioread32_mac(addr); } static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command, @@ -1424,20 +1428,20 @@ static void ath_pll_reset_ones(struct ath_hal *ah) if(reset_pll == 0) { #if defined(PROJECT_K2) /* here we write to core register */ - HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0); + iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0); /* and here to mac register */ - ath_hal_reg_write_target(ah, 0x786c, - ath_hal_reg_read_target(ah,0x786c) | 0x6000000); - ath_hal_reg_write_target(ah, 0x786c, - ath_hal_reg_read_target(ah,0x786c) & (~0x6000000)); + iowrite32_mac(0x786c, + ioread32_mac(0x786c) | 0x6000000); + iowrite32_mac(0x786c, + ioread32_mac(0x786c) & (~0x6000000)); - HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20); + iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20); #elif defined(PROJECT_MAGPIE) && !defined (FPGA) - ath_hal_reg_write_target(ah, 0x7890, - ath_hal_reg_read_target(ah,0x7890) | 0x1800000); - ath_hal_reg_write_target(ah, 0x7890, - ath_hal_reg_read_target(ah,0x7890) & (~0x1800000)); + iowrite32_mac(0x7890, + ioread32_mac(0x7890) | 0x1800000); + iowrite32_mac(0x7890, + ioread32_mac(0x7890) & (~0x1800000)); #endif reset_pll = 1; } @@ -1447,7 +1451,7 @@ static void ath_hal_reg_write_filter(struct ath_hal *ah, a_uint32_t reg, a_uint32_t val) { if(reg > 0xffff) { - HAL_WORD_REG_WRITE(reg, val); + iowrite32(reg, val); #if defined(PROJECT_K2) if(reg == 0x50040) { static uint8_t flg=0; @@ -1466,7 +1470,7 @@ static void ath_hal_reg_write_filter(struct ath_hal *ah, if(reg == 0x7014) ath_pll_reset_ones(ah); - ath_hal_reg_write_target(ah, reg, val); + iowrite32_mac(reg, val); } }