X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=target_firmware%2Fwlan%2Fif_ath.c;h=864f48f8229f47f919d96aea4aa3dea33b2c30af;hb=9eb079a1801b89fec0578831c95c0fb1f1383158;hp=380356ddf4df586025c458f9052f7e3af9edd4c1;hpb=c73c159303e30a28e2d3dc05ba0d2d15504e5fad;p=open-ath9k-htc-firmware.git

diff --git a/target_firmware/wlan/if_ath.c b/target_firmware/wlan/if_ath.c
index 380356d..864f48f 100755
--- a/target_firmware/wlan/if_ath.c
+++ b/target_firmware/wlan/if_ath.c
@@ -1380,6 +1380,23 @@ static void ath_node_update_tgt(void *Context, A_UINT16 Command,
 	wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
 }
 
+static a_int32_t ath_reg_read_filter(struct ath_hal *ah, a_int32_t addr)
+{
+	if ((addr & 0xffffe000) == 0x2000) {
+		/* SEEPROM registers */
+		ioread32_mac(addr);
+		if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0))
+			adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
+
+		return ioread32_mac(0x407c) & 0x0000ffff;
+	} else if (addr > 0xffff)
+		/* SoC registers */
+		return ioread32(addr);
+	else
+		/* MAC registers */
+		return ioread32_mac(addr);
+}
+
 static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
 				 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
 {
@@ -1393,24 +1410,66 @@ static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
 		addr = *(a_uint32_t *)(data + i);
 		addr = adf_os_ntohl(addr);
 
-		if ((addr & 0xffffe000) == 0x2000) {
-			/* SEEPROM */
-			ath_hal_reg_read_target(ah, addr);
-			if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) {
-				adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
-			}
-			val[i/sizeof(a_int32_t)] = (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
-		} else if (addr > 0xffff) {
-			val[i/sizeof(a_int32_t)] = *(a_uint32_t *)addr;
-		} else
-			val[i/sizeof(a_int32_t)] = ath_hal_reg_read_target(ah, addr);
-
-		val[i/sizeof(a_int32_t)] = adf_os_ntohl(val[i/sizeof(a_int32_t)]);
+		val[i/sizeof(a_int32_t)] =
+			adf_os_ntohl(ath_reg_read_filter(ah, addr));
 	}
 
 	wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen);
 }
 
+static void ath_pll_reset_ones(struct ath_hal *ah)
+{
+	static uint8_t reset_pll = 0;
+
+	if(reset_pll == 0) {
+#if defined(PROJECT_K2)
+		/* here we write to core register */
+		iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
+		/* and here to mac register */
+		iowrite32_mac(0x786c,
+			 ioread32_mac(0x786c) | 0x6000000);
+		iowrite32_mac(0x786c,
+			 ioread32_mac(0x786c) & (~0x6000000));
+
+		iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
+
+#elif defined(PROJECT_MAGPIE) && !defined (FPGA)
+		iowrite32_mac(0x7890,
+			 ioread32_mac(0x7890) | 0x1800000);
+		iowrite32_mac(0x7890,
+			 ioread32_mac(0x7890) & (~0x1800000));
+#endif
+		reset_pll = 1;
+	}
+}
+
+static void ath_hal_reg_write_filter(struct ath_hal *ah,
+			a_uint32_t reg, a_uint32_t val)
+{
+	if(reg > 0xffff) {
+		iowrite32(reg, val);
+#if defined(PROJECT_K2)
+		if(reg == 0x50040) {
+			static uint8_t flg=0;
+
+			if(flg == 0) {
+				/* reinit clock and uart.
+				 * TODO: Independent on what host will
+				 * here set. We do our own decision. Why? */
+				A_CLOCK_INIT(117);
+				A_UART_HWINIT(117*1000*1000, 19200);
+				flg = 1;
+			}
+		}
+#endif
+	} else {
+		if(reg == 0x7014)
+			ath_pll_reset_ones(ah);
+
+		iowrite32_mac(reg, val);
+	}
+}
+
 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
 				  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
 {
@@ -1425,52 +1484,7 @@ static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
 	for (i = 0; i < datalen; i += sizeof(struct registerWrite)) {
 		t = (struct registerWrite *)(data+i);
 
-		if( t->reg > 0xffff ) {
-			HAL_WORD_REG_WRITE(t->reg, t->val);
-#if defined(PROJECT_K2)
-			if( t->reg == 0x50040 ) {
-				static uint8_t flg=0;
-
-				if( flg == 0 ) {
-					A_CLOCK_INIT(117);
-					A_UART_HWINIT(117*1000*1000, 19200);
-					flg = 1;
-				}
-			}
-#endif
-		} else {
-#if defined(PROJECT_K2)
-			if( t->reg == 0x7014 ) {
-				static uint8_t resetPLL = 0;
-
-				if( resetPLL == 0 ) {
-					/* here we write to core register */
-					HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
-					/* and here to mac register */
-					ath_hal_reg_write_target(ah, 0x786c,
-						 ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
-					ath_hal_reg_write_target(ah, 0x786c,
-						 ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
-
-					HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
-					resetPLL = 1;
-				}
-			}
-#elif defined(PROJECT_MAGPIE) && !defined (FPGA)
-			if( t->reg == 0x7014 ){
-				static uint8_t resetPLL = 0;
-
-				if( resetPLL == 0 ) {
-					ath_hal_reg_write_target(ah, 0x7890,
-						 ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
-					ath_hal_reg_write_target(ah, 0x7890,
-						 ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
-					resetPLL = 1;
-				}
-			}
-#endif
-			ath_hal_reg_write_target(ah,t->reg,t->val);
-		}
+		ath_hal_reg_write_filter(ah, t->reg, t->val);
 	}
 
 	wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
@@ -1490,10 +1504,10 @@ static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command,
 		a_uint32_t val;
 		buf = (struct register_rmw *)(data + i);
 
-		val = ath_hal_reg_read_target(ah, buf->reg);
+		val = ath_reg_read_filter(ah, buf->reg);
 		val &= ~buf->clr;
 		val |= buf->set;
-		ath_hal_reg_write_target(ah, buf->reg, val);
+		ath_hal_reg_write_filter(ah, buf->reg, val);
 	}
 	wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
 }