X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=target_firmware%2Fwlan%2Fif_ath.c;h=3cc61f7f29f094db4f2fa358e7668a0de3ba70ab;hb=28d5112c4933b4b26e1744ebd2411755865004c0;hp=ce29af409fec4ae747a9337a0128013c50084e64;hpb=4fae5acb89fde36e7b03df258e304181590df98d;p=open-ath9k-htc-firmware.git diff --git a/target_firmware/wlan/if_ath.c b/target_firmware/wlan/if_ath.c index ce29af4..3cc61f7 100755 --- a/target_firmware/wlan/if_ath.c +++ b/target_firmware/wlan/if_ath.c @@ -72,6 +72,7 @@ uint32_t *init_htc_handle = 0; void owl_tgt_tx_tasklet(TQUEUE_ARG data); static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt); static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen); +static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen); extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh); extern void ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt); extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val); @@ -80,17 +81,6 @@ void owl_tgt_node_init(struct ath_node_target * an); void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf); void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host); -/*************/ -/* Utilities */ -/*************/ - -#undef adf_os_cpu_to_le16 - -static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x) -{ - return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8)); -} - /* * Extend a 32 bit TSF to 64 bit, taking wrapping into account. */ @@ -266,9 +256,7 @@ static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *d ds->ds_link = 0; adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen); - ath_hal_setuprxdesc(ah, ds, - adf_nbuf_tailroom(ds->ds_nbuf), - 0); + ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0); if (sc->sc_rxlink == NULL) { ah->ah_setRxDP(ah, ds->ds_daddr); @@ -277,7 +265,7 @@ static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *d *sc->sc_rxlink = ds->ds_daddr; } sc->sc_rxlink = &ds->ds_link; - ath_hal_rxena(ah); + ah->ah_enableReceive(ah); return 0; } @@ -386,7 +374,7 @@ static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc) continue; } - retval = ath_hal_rxprocdescfast(ah, ds, ds->ds_daddr, + retval = ah->ah_procRxDescFast(ah, ds, ds->ds_daddr, PA2DESC(sc, ds->ds_link), &bf->bf_rx_status); if (HAL_EINPROGRESS == retval) { break; @@ -522,7 +510,7 @@ static void ath_tgt_rx_tasklet(TQUEUE_ARG data) } while(1); sc->sc_imask |= HAL_INT_RX; - ath_hal_intrset(ah, sc->sc_imask); + ah->ah_setInterrupts(ah, sc->sc_imask); } /*******************/ @@ -555,22 +543,18 @@ static void ath_beacon_setup(struct ath_softc_tgt *sc, rt = sc->sc_currates; rate = rt->info[rix].rateCode; - ath_hal_setuptxdesc(ah, ds + ah->ah_setupTxDesc(ds , adf_nbuf_len(skb) + IEEE80211_CRC_LEN , sizeof(struct ieee80211_frame) , HAL_PKT_TYPE_BEACON , MAX_RATE_POWER , rate, 1 , HAL_TXKEYIX_INVALID - , 0 , flags , 0 - , 0 - , 0 - , 0 - , ATH_COMP_PROC_NO_COMP_NO_CCS); + , 0); - ath_hal_filltxdesc(ah, ds + ah->ah_fillTxDesc(ds , asf_roundup(adf_nbuf_len(skb), 4) , AH_TRUE , AH_TRUE @@ -580,7 +564,7 @@ static void ath_beacon_setup(struct ath_softc_tgt *sc, series[0].Rate = rate; series[0].ChSel = sc->sc_ic.ic_tx_chainmask; series[0].RateFlags = 0; - ath_hal_set11n_ratescenario(ah, ds, 0, 0, 0, series, 4, 0); + ah->ah_set11nRateScenario(ds, 0, 0, series, 4, 0); } static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr, @@ -1021,15 +1005,15 @@ adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl) if (sc->sc_invalid) return ADF_OS_IRQ_NONE; - if (!ath_hal_intrpend(ah)) + if (!ah->ah_isInterruptPending(ah)) return ADF_OS_IRQ_NONE; - ath_hal_getisr(ah, &status); + ah->ah_getPendingInterrupts(ah, &status); status &= sc->sc_imask; if (status & HAL_INT_FATAL) { - ath_hal_intrset(ah, 0); + ah->ah_setInterrupts(ah, 0); ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq); } else { if (status & HAL_INT_SWBA) { @@ -1061,7 +1045,7 @@ adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl) ath_uapsd_processtriggers(sc); sc->sc_imask &= ~HAL_INT_RX; - ath_hal_intrset(ah, sc->sc_imask); + ah->ah_setInterrupts(ah, sc->sc_imask); ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq); } @@ -1127,7 +1111,7 @@ static void ath_enable_intr_tgt(void *Context, A_UINT16 Command, sc->sc_imask |= HAL_INT_BMISS; } - ath_hal_intrset(ah, sc->sc_imask); + ah->ah_setInterrupts(ah, sc->sc_imask); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0); } @@ -1143,11 +1127,11 @@ static void ath_init_tgt(void *Context, A_UINT16 Command, sc->sc_imask |= HAL_INT_GTT; - if (ath_hal_htsupported(ah)) + if (ath_hal_getcapability(ah, HAL_CAP_HT)) sc->sc_imask |= HAL_INT_CST; adf_os_setup_intr(sc->sc_dev, ath_intr); - ath_hal_intrset(ah, sc->sc_imask); + ah->ah_setInterrupts(ah, sc->sc_imask); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } @@ -1396,6 +1380,23 @@ static void ath_node_update_tgt(void *Context, A_UINT16 Command, wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } +static a_int32_t ath_reg_read_filter(struct ath_hal *ah, a_int32_t addr) +{ + if ((addr & 0xffffe000) == 0x2000) { + /* SEEPROM registers */ + ath_hal_reg_read_target(ah, addr); + if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) + adf_os_print("SEEPROM Read fail: 0x%08x\n", addr); + + return (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff); + } else if (addr > 0xffff) + /* SoC registers */ + return HAL_WORD_REG_READ(addr); + else + /* MAC registers */ + return ath_hal_reg_read_target(ah, addr); +} + static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { @@ -1409,24 +1410,66 @@ static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command, addr = *(a_uint32_t *)(data + i); addr = adf_os_ntohl(addr); - if ((addr & 0xffffe000) == 0x2000) { - /* SEEPROM */ - ath_hal_reg_read_target(ah, addr); - if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) { - adf_os_print("SEEPROM Read fail: 0x%08x\n", addr); - } - val[i/sizeof(a_int32_t)] = (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff); - } else if (addr > 0xffff) { - val[i/sizeof(a_int32_t)] = *(a_uint32_t *)addr; - } else - val[i/sizeof(a_int32_t)] = ath_hal_reg_read_target(ah, addr); - - val[i/sizeof(a_int32_t)] = adf_os_ntohl(val[i/sizeof(a_int32_t)]); + val[i/sizeof(a_int32_t)] = + adf_os_ntohl(ath_reg_read_filter(ah, addr)); } wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen); } +static void ath_pll_reset_ones(struct ath_hal *ah) +{ + static uint8_t reset_pll = 0; + + if(reset_pll == 0) { +#if defined(PROJECT_K2) + /* here we write to core register */ + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0); + /* and here to mac register */ + ath_hal_reg_write_target(ah, 0x786c, + ath_hal_reg_read_target(ah,0x786c) | 0x6000000); + ath_hal_reg_write_target(ah, 0x786c, + ath_hal_reg_read_target(ah,0x786c) & (~0x6000000)); + + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20); + +#elif defined(PROJECT_MAGPIE) && !defined (FPGA) + ath_hal_reg_write_target(ah, 0x7890, + ath_hal_reg_read_target(ah,0x7890) | 0x1800000); + ath_hal_reg_write_target(ah, 0x7890, + ath_hal_reg_read_target(ah,0x7890) & (~0x1800000)); +#endif + reset_pll = 1; + } +} + +static void ath_hal_reg_write_filter(struct ath_hal *ah, + a_uint32_t reg, a_uint32_t val) +{ + if(reg > 0xffff) { + HAL_WORD_REG_WRITE(reg, val); +#if defined(PROJECT_K2) + if(reg == 0x50040) { + static uint8_t flg=0; + + if(flg == 0) { + /* reinit clock and uart. + * TODO: Independent on what host will + * here set. We do our own decision. Why? */ + A_CLOCK_INIT(117); + A_UART_HWINIT(117*1000*1000, 19200); + flg = 1; + } + } +#endif + } else { + if(reg == 0x7014) + ath_pll_reset_ones(ah); + + ath_hal_reg_write_target(ah, reg, val); + } +} + static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { @@ -1441,58 +1484,31 @@ static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, for (i = 0; i < datalen; i += sizeof(struct registerWrite)) { t = (struct registerWrite *)(data+i); - if( t->reg > 0xffff ) { - a_uint32_t *pReg = (a_uint32_t *)t->reg; + ath_hal_reg_write_filter(ah, t->reg, t->val); + } - *pReg = t->val; + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} -#if defined(PROJECT_K2) - if( t->reg == 0x50040 ) { - static uint8_t flg=0; +static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, + a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ath_hal *ah = sc->sc_ah; + struct register_rmw *buf = (struct register_rmw *)data; + int i; - if( flg == 0 ) { - A_CLOCK_INIT(117); - A_UART_HWINIT(117*1000*1000, 19200); - flg = 1; - } - } -#endif - } else { -#if defined(PROJECT_K2) - if( t->reg == 0x7014 ) { - static uint8_t resetPLL = 0; - a_uint32_t *pReg; - - if( resetPLL == 0 ) { - t->reg = 0x50044; - pReg = (a_uint32_t *)t->reg; - *pReg = 0; - ath_hal_reg_write_target(ah, 0x786c, - ath_hal_reg_read_target(ah,0x786c) | 0x6000000); - ath_hal_reg_write_target(ah, 0x786c, - ath_hal_reg_read_target(ah,0x786c) & (~0x6000000)); - *pReg = 0x20; - resetPLL = 1; - } - t->reg = 0x7014; - } -#elif defined(PROJECT_MAGPIE) && !defined (FPGA) - if( t->reg == 0x7014 ){ - static uint8_t resetPLL = 0; - - if( resetPLL == 0 ) { - ath_hal_reg_write_target(ah, 0x7890, - ath_hal_reg_read_target(ah,0x7890) | 0x1800000); - ath_hal_reg_write_target(ah, 0x7890, - ath_hal_reg_read_target(ah,0x7890) & (~0x1800000)); - resetPLL = 1; - } - } -#endif - ath_hal_reg_write_target(ah,t->reg,t->val); - } - } + for (i = 0; i < datalen; + i += sizeof(struct register_rmw)) { + a_uint32_t val; + buf = (struct register_rmw *)(data + i); + val = ath_reg_read_filter(ah, buf->reg); + val &= ~buf->clr; + val |= buf->set; + ath_hal_reg_write_filter(ah, buf->reg, val); + } wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } @@ -1516,7 +1532,7 @@ static void ath_disable_intr_tgt(void *Context, A_UINT16 Command, struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; - ath_hal_intrset(ah, 0); + ah->ah_setInterrupts(ah, 0); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0); } @@ -1617,9 +1633,9 @@ static void ath_stoprecv_tgt(void *Context, A_UINT16 Command, struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; - ath_hal_stoppcurecv(ah); + ah->ah_stopPcuReceive(ah); ah->ah_setRxFilter(ah, 0); - ath_hal_stopdmarecv(ah); + ah->ah_stopDmaReceive(ah); sc->sc_rxlink = NULL; wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); @@ -1755,6 +1771,7 @@ static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] = {ath_tx_stats_tgt, WMI_TX_STATS_CMDID, 0}, {ath_rx_stats_tgt, WMI_RX_STATS_CMDID, 0}, {ath_rc_mask_tgt, WMI_BITRATE_MASK_CMDID, 0}, + {ath_hal_reg_rmw_tgt, WMI_REG_RMW_CMDID, 0}, }; /*****************/ @@ -1931,7 +1948,7 @@ a_int32_t ath_tgt_attach(a_uint32_t devid, struct ath_softc_tgt *sc, adf_os_devi ath_tgt_txq_setup(sc); sc->sc_imask =0; - ath_hal_intrset(ah,0); + ah->ah_setInterrupts(ah, 0); return 0; bad: