X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=target_firmware%2Fwlan%2Far5416_hw.c;h=becd89d5164545f1624fdd5d664721b6d742f725;hb=6f2219c1ab25d1dfbb5d2de6508212a27f9d7e9c;hp=78882ff9b064570361d65f66510f8766657f0761;hpb=0056916c5ac6d4d5b8fa151c010fc2874906a61d;p=open-ath9k-htc-firmware.git diff --git a/target_firmware/wlan/ar5416_hw.c b/target_firmware/wlan/ar5416_hw.c index 78882ff..becd89d 100644 --- a/target_firmware/wlan/ar5416_hw.c +++ b/target_firmware/wlan/ar5416_hw.c @@ -58,7 +58,7 @@ static const struct ath_hal_private ar5416hal_10 = {{ /* Transmit functions */ .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel, .ah_setTxDP = ar5416SetTxDP, - .ah_numTxPending = ar5416NumTxPending, + .ah_numTxPending = ar5416NumTxPending, .ah_startTxDma = ar5416StartTxDma, .ah_stopTxDma = ar5416StopTxDma, @@ -88,8 +88,7 @@ void ar5416Detach(struct ath_hal *ah) } struct ath_hal * -ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev, - a_uint32_t flags, HAL_STATUS *status) +ar5416Attach(HAL_SOFTC sc, adf_os_device_t dev, HAL_STATUS *status) { struct ath_hal_5416 *ahp; struct ath_hal *ah; @@ -130,7 +129,8 @@ ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev, HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah) { - a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE); + a_uint32_t host_isr = + ioread32_mac(AR_INTR_ASYNC_CAUSE); /* * Some platforms trigger our ISR before applying power to * the card, so make sure. @@ -145,8 +145,10 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) HAL_BOOL fatal_int = AH_FALSE; a_uint32_t sync_cause; - if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { - if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) { + if (ioread32_mac(AR_INTR_ASYNC_CAUSE) + & AR_INTR_MAC_IRQ) { + if ((ioread32_mac(AR_RTC_STATUS) + & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) { *masked = 0; return AH_FALSE; } @@ -155,7 +157,7 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) return AH_FALSE; } #endif - isr = OS_REG_READ(ah, AR_ISR_RAC); + isr = ioread32_mac(AR_ISR_RAC); if (isr == 0xffffffff) { *masked = 0; return AH_FALSE; @@ -175,7 +177,7 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) if (isr & AR_ISR_BCNMISC) { a_uint32_t s2_s; - s2_s = OS_REG_READ(ah, AR_ISR_S2_S); + s2_s = ioread32_mac(AR_ISR_S2_S); if (s2_s & AR_ISR_S2_GTT) { *masked |= HAL_INT_GTT; @@ -193,8 +195,8 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) a_uint32_t s0_s, s1_s; *masked |= HAL_INT_TX; - s0_s = OS_REG_READ(ah, AR_ISR_S0_S); - s1_s = OS_REG_READ(ah, AR_ISR_S1_S); + s0_s = ioread32_mac(AR_ISR_S0_S); + s1_s = ioread32_mac(AR_ISR_S1_S); ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); @@ -202,14 +204,14 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) } #ifndef AR9100 - sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); + sync_cause = ioread32_mac(AR_INTR_SYNC_CAUSE); fatal_int = ((sync_cause != AR_INTR_SPURIOUS) && - (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ? - AH_TRUE : AH_FALSE; + (sync_cause & (AR_INTR_SYNC_HOST1_FATAL + | AR_INTR_SYNC_HOST1_PERR))) ? AH_TRUE : AH_FALSE; if (AH_TRUE == fatal_int) { - OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); - (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); + iowrite32_mac(AR_INTR_SYNC_CAUSE_CLR, sync_cause); + (void) ioread32_mac(AR_INTR_SYNC_CAUSE_CLR); } #endif return AH_TRUE; @@ -223,8 +225,8 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) a_uint32_t mask; if (omask & HAL_INT_GLOBAL) { - OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); - (void) OS_REG_READ(ah, AR_IER); + iowrite32_mac(AR_IER, AR_IER_DISABLE); + (void) ioread32_mac(AR_IER); } mask = ints & HAL_INT_COMMON; @@ -251,20 +253,20 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) mask |= AR_IMR_BCNMISC; } - OS_REG_WRITE(ah, AR_IMR, mask); - (void) OS_REG_READ(ah, AR_IMR); + iowrite32_mac(AR_IMR, mask); + (void) ioread32_mac(AR_IMR); ahp->ah_maskReg = ints; /* Re-enable interrupts if they were enabled before. */ if (ints & HAL_INT_GLOBAL) { - OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); + iowrite32_mac(AR_IER, AR_IER_ENABLE); /* See explanation above... */ - (void) OS_REG_READ(ah, AR_IER); + (void) ioread32_mac(AR_IER); } - OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); - OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); - OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL); + iowrite32_mac(AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); + iowrite32_mac(AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); + iowrite32_mac(AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL); return omask; } @@ -273,14 +275,23 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) /* TSF Handling */ /****************/ +#define ATH9K_HTC_MAX_TSF_READ 3 + u_int64_t ar5416GetTsf64(struct ath_hal *ah) { - u_int64_t tsf; + a_uint32_t tsf_lower, tsf_upper1, tsf_upper2; + a_int32_t i; - tsf = OS_REG_READ(ah, AR_TSF_U32); - tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32); + tsf_upper1 = ioread32_mac(AR_TSF_U32); + for (i = 0; i < ATH9K_HTC_MAX_TSF_READ; i++) { + tsf_lower = ioread32_mac(AR_TSF_L32); + tsf_upper2 = ioread32_mac(AR_TSF_U32); + if (tsf_upper2 == tsf_upper1) + break; + tsf_upper1 = tsf_upper2; + } - return tsf; + return (((u_int64_t)tsf_upper2 << 32) | tsf_lower); } /******/ @@ -288,35 +299,13 @@ u_int64_t ar5416GetTsf64(struct ath_hal *ah) /******/ void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp) { - OS_REG_WRITE(ah, AR_RXDP, rxdp); - HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp); -} - -void ar5416SetMulticastFilter(struct ath_hal *ah, a_uint32_t filter0, a_uint32_t filter1) -{ - OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0); - OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1); -} - -HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix) -{ - a_uint32_t val; - - if (ix >= 64) - return AH_FALSE; - if (ix >= 32) { - val = OS_REG_READ(ah, AR_MCAST_FIL1); - OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32)))); - } else { - val = OS_REG_READ(ah, AR_MCAST_FIL0); - OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<= 64) - return AH_FALSE; - if (ix >= 32) { - val = OS_REG_READ(ah, AR_MCAST_FIL1); - OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32)))); - } else { - val = OS_REG_READ(ah, AR_MCAST_FIL0); - OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<ds_rxstatus8 & AR_RxDone) == 0 - && OS_REG_READ(ah, AR_RXDP) == pa) + && ioread32_mac(AR_RXDP) == pa) return HAL_EINPROGRESS; /* - * Now we need to get the stats from the descriptor. Since desc are + * Now we need to get the stats from the descriptor. Since desc are * uncached, lets make a copy of the stats first. Note that, since we * touch most of the rx stats, a memcpy would always be more efficient * @@ -423,7 +400,7 @@ HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds, rx_stats->rs_tstamp = ads.AR_RcvTimestamp; /* XXX what about KeyCacheMiss? */ - rx_stats->rs_rssi_combined = + rx_stats->rs_rssi_combined = MS(ads.ds_rxstatus4, AR_RxRSSICombined); rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00); rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01); @@ -496,7 +473,7 @@ HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel) */ omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL); - txcfg = OS_REG_READ(ah, AR_TXCFG); + txcfg = ioread32_mac(AR_TXCFG); curLevel = MS(txcfg, AR_FTRIG); newLevel = curLevel; @@ -506,8 +483,8 @@ HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel) } else if (curLevel > MIN_TX_FIFO_THRESHOLD) newLevel--; if (newLevel != curLevel) - OS_REG_WRITE(ah, AR_TXCFG, - (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG)); + iowrite32_mac(AR_TXCFG, + (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG)); /* re-enable chip interrupts */ ar5416SetInterrupts(ah, omask); @@ -524,9 +501,9 @@ HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp) * Make sure that TXE is deasserted before setting the TXDP. If TXE * is still asserted, setting TXDP will have no effect. */ - HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0); + HALASSERT((ioread32_mac(AR_Q_TXE) & (1 << q)) == 0); - OS_REG_WRITE(ah, AR_QTXDP(q), txdp); + iowrite32_mac(AR_QTXDP(q), txdp); return AH_TRUE; } @@ -537,9 +514,9 @@ HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q) HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); /* Check to be sure we're not enabling a q that has its TXD bit set. */ - HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0); + HALASSERT((ioread32_mac(AR_Q_TXD) & (1 << q)) == 0); - OS_REG_WRITE(ah, AR_Q_TXE, 1 << q); + iowrite32_mac(AR_Q_TXE, 1 << q); return AH_TRUE; } @@ -551,22 +528,24 @@ a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q) HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); - npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; + npend = ioread32_mac(AR_QSTS(q)) + & AR_Q_STS_PEND_FR_CNT; if (npend == 0) { /* * Pending frame count (PFC) can momentarily go to zero * while TXE remains asserted. In other words a PFC of * zero is not sufficient to say that the queue has stopped. */ - if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) + if (ioread32_mac(AR_Q_TXE) & (1 << q)) npend = 1; } #ifdef DEBUG if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) { - if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) { + if (ioread32_mac(AR_Q_RDYTIMESHDN) + & (1 << q)) { isrPrintf("RTSD on CAB queue\n"); /* Clear the ReadyTime shutdown status bits */ - OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q); + iowrite32_mac(AR_Q_RDYTIMESHDN, 1 << q); } } #endif @@ -580,7 +559,7 @@ HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah) /* * set txd on all queues */ - OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); + iowrite32_mac(AR_Q_TXD, AR_Q_TXD_M); /* * set tx abort bits @@ -614,7 +593,7 @@ HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah) /* * clear txd */ - OS_REG_WRITE(ah, AR_Q_TXD, 0); + iowrite32_mac(AR_Q_TXD, 0); return AH_TRUE; } @@ -622,36 +601,32 @@ HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah) HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q) { a_uint32_t i; - + HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); - OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); + iowrite32_mac(AR_Q_TXD, 1 << q); for (i = 1000; i != 0; i--) { if (ar5416NumTxPending(ah, q) == 0) break; OS_DELAY(100); /* XXX get actual value */ } - OS_REG_WRITE(ah, AR_Q_TXD, 0); + iowrite32_mac(AR_Q_TXD, 0); return (i != 0); } -HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, +HAL_BOOL ar5416SetupTxDesc_20(struct ath_tx_desc *ds, a_uint32_t pktLen, a_uint32_t hdrLen, HAL_PKT_TYPE type, a_uint32_t txPower, a_uint32_t txRate0, a_uint32_t txTries0, a_uint32_t keyIx, - a_uint32_t antMode, a_uint32_t flags, a_uint32_t rtsctsRate, - a_uint32_t rtsctsDuration, - a_uint32_t compicvLen, - a_uint32_t compivLen, - a_uint32_t comp) + a_uint32_t rtsctsDuration) { #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA) @@ -680,9 +655,9 @@ HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0); ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S); - ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0) + ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0) | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1) - | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2) + | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2) | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3); if (keyIx != HAL_TXKEYIX_INVALID) { @@ -706,7 +681,7 @@ HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, #undef RTSCTS } -HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, +HAL_BOOL ar5416FillTxDesc_20(struct ath_tx_desc *ds, a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, const struct ath_tx_desc *ds0) { @@ -744,7 +719,7 @@ HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, return AH_TRUE; } -HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, +HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_tx_desc *ds, HAL_KEY_TYPE keyType) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -757,7 +732,7 @@ HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds) { struct ar5416_desc *ads = AR5416DESC(gds); struct ath_tx_desc *ds = (struct ath_tx_desc *)gds; - + if ((ads->ds_txstatus9 & AR_TxDone) == 0) return HAL_EINPROGRESS; @@ -801,7 +776,7 @@ HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds) * ``alternate'' if it wasn't the series 0 rate. */ ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx); - ds->ds_txstat.ts_rssi_combined = + ds->ds_txstat.ts_rssi_combined = MS(ads->ds_txstatus5, AR_TxRSSICombined); ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00); ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01); @@ -820,7 +795,7 @@ HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds) return HAL_OK; } -void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, +void ar5416Set11nTxDesc_20(struct ath_tx_desc *ds, a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower, a_uint32_t keyIx, HAL_KEY_TYPE keyType, a_uint32_t flags) @@ -852,26 +827,23 @@ void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, ads->ds_ctl6 = SM(keyType, AR_EncrType); } -#ifdef MAGPIE_MERLIN - -void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds, +void ar5416Set11nRateScenario_20(struct ath_tx_desc *ds, a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, - a_uint32_t rtsctsDuration, HAL_11N_RATE_SERIES series[], a_uint32_t nseries, a_uint32_t flags) { - struct ar5416_desc *ads = AR5416DESC(ds); - a_uint32_t ds_ctl0; + struct ar5416_desc *ads = AR5416DESC(ds); + a_uint32_t ds_ctl0; - HALASSERT(nseries == 4); - (void)nseries; + HALASSERT(nseries == 4); + (void)nseries; - /* - * Rate control settings override - */ + /* + * Rate control settings override + */ ds_ctl0 = ads->ds_ctl0; - if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { + if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { if (flags & HAL_TXDESC_RTSENA) { ds_ctl0 &= ~AR_CTSEnable; ds_ctl0 |= AR_RTSEnable; @@ -879,94 +851,39 @@ void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds, ds_ctl0 &= ~AR_RTSEnable; ds_ctl0 |= AR_CTSEnable; } - } else { + } else { + /* this line is only difference between merlin and k2 + * Current one is for merlin */ ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable)); - } + } ads->ds_ctl0 = ds_ctl0; - ads->ds_ctl2 = set11nTries(series, 0) - | set11nTries(series, 1) - | set11nTries(series, 2) - | set11nTries(series, 3) - | (durUpdateEn ? AR_DurUpdateEn : 0); - - ads->ds_ctl3 = set11nRate(series, 0) - | set11nRate(series, 1) - | set11nRate(series, 2) - | set11nRate(series, 3); - - ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0) - | set11nPktDurRTSCTS(series, 1); - - ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2) - | set11nPktDurRTSCTS(series, 3); - - ads->ds_ctl7 = set11nRateFlags(series, 0) - | set11nRateFlags(series, 1) - | set11nRateFlags(series, 2) - | set11nRateFlags(series, 3) - | SM(rtsctsRate, AR_RTSCTSRate); -} - -#else - -void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds, - a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, - a_uint32_t rtsctsDuration, - HAL_11N_RATE_SERIES series[], a_uint32_t nseries, - a_uint32_t flags) -{ - struct ar5416_desc *ads = AR5416DESC(ds); - a_uint32_t ds_ctl0; - - HALASSERT(nseries == 4); - (void)nseries; + ads->ds_ctl2 = set11nTries(series, 0) + | set11nTries(series, 1) + | set11nTries(series, 2) + | set11nTries(series, 3) + | (durUpdateEn ? AR_DurUpdateEn : 0); - /* - * Rate control settings override - */ - if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { - ds_ctl0 = ads->ds_ctl0; - - if (flags & HAL_TXDESC_RTSENA) { - ds_ctl0 &= ~AR_CTSEnable; - ds_ctl0 |= AR_RTSEnable; - } else { - ds_ctl0 &= ~AR_RTSEnable; - ds_ctl0 |= AR_CTSEnable; - } - - ads->ds_ctl0 = ds_ctl0; - } + ads->ds_ctl3 = set11nRate(series, 0) + | set11nRate(series, 1) + | set11nRate(series, 2) + | set11nRate(series, 3); - ads->ds_ctl2 = set11nTries(series, 0) - | set11nTries(series, 1) - | set11nTries(series, 2) - | set11nTries(series, 3) - | (durUpdateEn ? AR_DurUpdateEn : 0); + ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0) + | set11nPktDurRTSCTS(series, 1); - ads->ds_ctl3 = set11nRate(series, 0) - | set11nRate(series, 1) - | set11nRate(series, 2) - | set11nRate(series, 3); + ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2) + | set11nPktDurRTSCTS(series, 3); - ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0) - | set11nPktDurRTSCTS(series, 1); - - ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2) - | set11nPktDurRTSCTS(series, 3); - - ads->ds_ctl7 = set11nRateFlags(series, 0) - | set11nRateFlags(series, 1) - | set11nRateFlags(series, 2) - | set11nRateFlags(series, 3) - | SM(rtsctsRate, AR_RTSCTSRate); + ads->ds_ctl7 = set11nRateFlags(series, 0) + | set11nRateFlags(series, 1) + | set11nRateFlags(series, 2) + | set11nRateFlags(series, 3) + | SM(rtsctsRate, AR_RTSCTSRate); } -#endif - -void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t aggrLen, +void ar5416Set11nAggrFirst_20(struct ath_tx_desc *ds, a_uint32_t aggrLen, a_uint32_t numDelims) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -978,7 +895,7 @@ void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint SM(numDelims, AR_PadDelim); } -void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t numDelims) +void ar5416Set11nAggrMiddle_20(struct ath_tx_desc *ds, a_uint32_t numDelims) { struct ar5416_desc *ads = AR5416DESC(ds); a_uint32_t ctl6; @@ -986,7 +903,7 @@ void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uin ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); /* - * We use a stack variable to manipulate ctl6 to reduce uncached + * We use a stack variable to manipulate ctl6 to reduce uncached * read modify, modfiy, write. */ ctl6 = ads->ds_ctl6; @@ -995,7 +912,7 @@ void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uin ads->ds_ctl6 = ctl6; } -void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_tx_desc *ds) +void ar5416Set11nAggrLast_20(struct ath_tx_desc *ds) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -1004,14 +921,14 @@ void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_tx_desc *ds) ads->ds_ctl6 &= ~AR_PadDelim; } -void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_tx_desc *ds) +void ar5416Clr11nAggr_20(struct ath_tx_desc *ds) { struct ar5416_desc *ads = AR5416DESC(ds); ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); } -void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds, +void ar5416Set11nBurstDuration_20(struct ath_tx_desc *ds, a_uint32_t burstDuration) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -1020,7 +937,7 @@ void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds, ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur); } -void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_tx_desc *ds, +void ar5416Set11nVirtualMoreFrag_20(struct ath_tx_desc *ds, a_uint32_t vmf) { struct ar5416_desc *ads = AR5416DESC(ds);