X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=target_firmware%2Fwlan%2Far5416_hw.c;h=becd89d5164545f1624fdd5d664721b6d742f725;hb=6f2219c1ab25d1dfbb5d2de6508212a27f9d7e9c;hp=5d0d1218c8508b0939afd789e7576de3e9ebcc53;hpb=0421b61b6a02eb61eaea125641ba69002d76ecf2;p=open-ath9k-htc-firmware.git diff --git a/target_firmware/wlan/ar5416_hw.c b/target_firmware/wlan/ar5416_hw.c index 5d0d121..becd89d 100644 --- a/target_firmware/wlan/ar5416_hw.c +++ b/target_firmware/wlan/ar5416_hw.c @@ -58,7 +58,7 @@ static const struct ath_hal_private ar5416hal_10 = {{ /* Transmit functions */ .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel, .ah_setTxDP = ar5416SetTxDP, - .ah_numTxPending = ar5416NumTxPending, + .ah_numTxPending = ar5416NumTxPending, .ah_startTxDma = ar5416StartTxDma, .ah_stopTxDma = ar5416StopTxDma, @@ -210,7 +210,7 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) | AR_INTR_SYNC_HOST1_PERR))) ? AH_TRUE : AH_FALSE; if (AH_TRUE == fatal_int) { - OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); + iowrite32_mac(AR_INTR_SYNC_CAUSE_CLR, sync_cause); (void) ioread32_mac(AR_INTR_SYNC_CAUSE_CLR); } #endif @@ -225,7 +225,7 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) a_uint32_t mask; if (omask & HAL_INT_GLOBAL) { - OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); + iowrite32_mac(AR_IER, AR_IER_DISABLE); (void) ioread32_mac(AR_IER); } @@ -253,20 +253,20 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) mask |= AR_IMR_BCNMISC; } - OS_REG_WRITE(ah, AR_IMR, mask); + iowrite32_mac(AR_IMR, mask); (void) ioread32_mac(AR_IMR); ahp->ah_maskReg = ints; /* Re-enable interrupts if they were enabled before. */ if (ints & HAL_INT_GLOBAL) { - OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); + iowrite32_mac(AR_IER, AR_IER_ENABLE); /* See explanation above... */ (void) ioread32_mac(AR_IER); } - OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); - OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); - OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL); + iowrite32_mac(AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); + iowrite32_mac(AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); + iowrite32_mac(AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL); return omask; } @@ -275,14 +275,23 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) /* TSF Handling */ /****************/ +#define ATH9K_HTC_MAX_TSF_READ 3 + u_int64_t ar5416GetTsf64(struct ath_hal *ah) { - u_int64_t tsf; - - tsf = ioread32_mac(AR_TSF_U32); - tsf = (tsf << 32) | ioread32_mac(AR_TSF_L32); + a_uint32_t tsf_lower, tsf_upper1, tsf_upper2; + a_int32_t i; + + tsf_upper1 = ioread32_mac(AR_TSF_U32); + for (i = 0; i < ATH9K_HTC_MAX_TSF_READ; i++) { + tsf_lower = ioread32_mac(AR_TSF_L32); + tsf_upper2 = ioread32_mac(AR_TSF_U32); + if (tsf_upper2 == tsf_upper1) + break; + tsf_upper1 = tsf_upper2; + } - return tsf; + return (((u_int64_t)tsf_upper2 << 32) | tsf_lower); } /******/ @@ -290,13 +299,13 @@ u_int64_t ar5416GetTsf64(struct ath_hal *ah) /******/ void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp) { - OS_REG_WRITE(ah, AR_RXDP, rxdp); + iowrite32_mac(AR_RXDP, rxdp); HALASSERT(ioread32_mac(AR_RXDP) == rxdp); } HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah) { - OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ + iowrite32_mac(AR_CR, AR_CR_RXD); /* Set receive disable bit */ if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { return AH_FALSE; } else { @@ -307,20 +316,20 @@ HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah) void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits) { a_uint32_t phybits; - - OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR); + + iowrite32_mac(AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR); phybits = 0; if (bits & HAL_RX_FILTER_PHYRADAR) phybits |= AR_PHY_ERR_RADAR; if (bits & HAL_RX_FILTER_PHYERR) phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; - OS_REG_WRITE(ah, AR_PHY_ERR, phybits); + iowrite32_mac(AR_PHY_ERR, phybits); if (phybits) { - OS_REG_WRITE(ah, AR_RXCFG, + iowrite32_mac(AR_RXCFG, ioread32_mac(AR_RXCFG) | AR_RXCFG_ZLFDMA); } else { - OS_REG_WRITE(ah, AR_RXCFG, + iowrite32_mac(AR_RXCFG, ioread32_mac(AR_RXCFG) & ~AR_RXCFG_ZLFDMA); } @@ -328,7 +337,7 @@ void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits) void ar5416EnableReceive(struct ath_hal *ah) { - OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); + iowrite32_mac(AR_CR, AR_CR_RXE); } void ar5416StopPcuReceive(struct ath_hal *ah) @@ -373,7 +382,7 @@ HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds, return HAL_EINPROGRESS; /* - * Now we need to get the stats from the descriptor. Since desc are + * Now we need to get the stats from the descriptor. Since desc are * uncached, lets make a copy of the stats first. Note that, since we * touch most of the rx stats, a memcpy would always be more efficient * @@ -391,7 +400,7 @@ HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds, rx_stats->rs_tstamp = ads.AR_RcvTimestamp; /* XXX what about KeyCacheMiss? */ - rx_stats->rs_rssi_combined = + rx_stats->rs_rssi_combined = MS(ads.ds_rxstatus4, AR_RxRSSICombined); rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00); rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01); @@ -474,8 +483,8 @@ HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel) } else if (curLevel > MIN_TX_FIFO_THRESHOLD) newLevel--; if (newLevel != curLevel) - OS_REG_WRITE(ah, AR_TXCFG, - (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG)); + iowrite32_mac(AR_TXCFG, + (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG)); /* re-enable chip interrupts */ ar5416SetInterrupts(ah, omask); @@ -494,7 +503,7 @@ HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp) */ HALASSERT((ioread32_mac(AR_Q_TXE) & (1 << q)) == 0); - OS_REG_WRITE(ah, AR_QTXDP(q), txdp); + iowrite32_mac(AR_QTXDP(q), txdp); return AH_TRUE; } @@ -507,7 +516,7 @@ HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q) /* Check to be sure we're not enabling a q that has its TXD bit set. */ HALASSERT((ioread32_mac(AR_Q_TXD) & (1 << q)) == 0); - OS_REG_WRITE(ah, AR_Q_TXE, 1 << q); + iowrite32_mac(AR_Q_TXE, 1 << q); return AH_TRUE; } @@ -536,7 +545,7 @@ a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q) & (1 << q)) { isrPrintf("RTSD on CAB queue\n"); /* Clear the ReadyTime shutdown status bits */ - OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q); + iowrite32_mac(AR_Q_RDYTIMESHDN, 1 << q); } } #endif @@ -550,7 +559,7 @@ HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah) /* * set txd on all queues */ - OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); + iowrite32_mac(AR_Q_TXD, AR_Q_TXD_M); /* * set tx abort bits @@ -584,7 +593,7 @@ HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah) /* * clear txd */ - OS_REG_WRITE(ah, AR_Q_TXD, 0); + iowrite32_mac(AR_Q_TXD, 0); return AH_TRUE; } @@ -592,19 +601,19 @@ HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah) HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q) { a_uint32_t i; - + HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); - OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); + iowrite32_mac(AR_Q_TXD, 1 << q); for (i = 1000; i != 0; i--) { if (ar5416NumTxPending(ah, q) == 0) break; OS_DELAY(100); /* XXX get actual value */ } - OS_REG_WRITE(ah, AR_Q_TXD, 0); + iowrite32_mac(AR_Q_TXD, 0); return (i != 0); } @@ -646,9 +655,9 @@ HAL_BOOL ar5416SetupTxDesc_20(struct ath_tx_desc *ds, ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0); ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S); - ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0) + ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0) | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1) - | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2) + | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2) | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3); if (keyIx != HAL_TXKEYIX_INVALID) { @@ -723,7 +732,7 @@ HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds) { struct ar5416_desc *ads = AR5416DESC(gds); struct ath_tx_desc *ds = (struct ath_tx_desc *)gds; - + if ((ads->ds_txstatus9 & AR_TxDone) == 0) return HAL_EINPROGRESS; @@ -767,7 +776,7 @@ HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds) * ``alternate'' if it wasn't the series 0 rate. */ ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx); - ds->ds_txstat.ts_rssi_combined = + ds->ds_txstat.ts_rssi_combined = MS(ads->ds_txstatus5, AR_TxRSSICombined); ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00); ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01); @@ -894,7 +903,7 @@ void ar5416Set11nAggrMiddle_20(struct ath_tx_desc *ds, a_uint32_t numDelims) ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); /* - * We use a stack variable to manipulate ctl6 to reduce uncached + * We use a stack variable to manipulate ctl6 to reduce uncached * read modify, modfiy, write. */ ctl6 = ads->ds_ctl6;