X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=target_firmware%2Fwlan%2Far5416_hw.c;h=5d0d1218c8508b0939afd789e7576de3e9ebcc53;hb=0421b61b6a02eb61eaea125641ba69002d76ecf2;hp=d1ceb66deb0e3d2515815bad81cf15c0b58cb184;hpb=e4cdb5e9803b91e157f3db293facac50349b53ac;p=open-ath9k-htc-firmware.git diff --git a/target_firmware/wlan/ar5416_hw.c b/target_firmware/wlan/ar5416_hw.c index d1ceb66..5d0d121 100644 --- a/target_firmware/wlan/ar5416_hw.c +++ b/target_firmware/wlan/ar5416_hw.c @@ -61,28 +61,22 @@ static const struct ath_hal_private ar5416hal_10 = {{ .ah_numTxPending = ar5416NumTxPending, .ah_startTxDma = ar5416StartTxDma, .ah_stopTxDma = ar5416StopTxDma, - - .ah_getTxIntrQueue = ar5416GetTxIntrQueue, + .ah_abortTxDma = ar5416AbortTxDma, /* Misc Functions */ - .ah_getTsf32 = ar5416GetTsf32, .ah_getTsf64 = ar5416GetTsf64, - .ah_resetTsf = ar5416ResetTsf, .ah_setRxFilter = ar5416SetRxFilter, /* RX Functions */ - .ah_getRxDP = ar5416GetRxDP, .ah_setRxDP = ar5416SetRxDP, .ah_stopDmaReceive = ar5416StopDmaReceive, .ah_enableReceive = ar5416EnableReceive, - .ah_startPcuReceive = ar5416StartPcuReceive, .ah_stopPcuReceive = ar5416StopPcuReceive, /* Interrupt Functions */ .ah_isInterruptPending = ar5416IsInterruptPending, .ah_getPendingInterrupts = ar5416GetPendingInterrupts, - .ah_getInterrupts = ar5416GetInterrupts, .ah_setInterrupts = ar5416SetInterrupts, }, }; @@ -94,8 +88,7 @@ void ar5416Detach(struct ath_hal *ah) } struct ath_hal * -ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev, - a_uint32_t flags, HAL_STATUS *status) +ar5416Attach(HAL_SOFTC sc, adf_os_device_t dev, HAL_STATUS *status) { struct ath_hal_5416 *ahp; struct ath_hal *ah; @@ -111,27 +104,21 @@ ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev, ah->ah_dev = dev; ah->ah_sc = sc; - - /* If its a Owl 2.0 chip then change the hal structure to - point to the Owl 2.0 ar5416_hal_20 structure */ - if(1) { - ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20; - ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20; - ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20; - ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20; - ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20; - ah->ah_clr11nAggr = ar5416Clr11nAggr_20; - ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20; - ah->ah_setupRxDesc = ar5416SetupRxDesc_20; - ah->ah_procRxDescFast = ar5416ProcRxDescFast_20; - ah->ah_updateCTSForBursting = NULL; - ah->ah_setupTxDesc = ar5416SetupTxDesc_20; - ah->ah_reqTxIntrDesc = ar5416IntrReqTxDesc_20; - ah->ah_fillTxDesc = ar5416FillTxDesc_20; - ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20; - ah->ah_procTxDesc = ar5416ProcTxDesc_20; - ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20; - } + + ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20; + ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20; + ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20; + ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20; + ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20; + ah->ah_clr11nAggr = ar5416Clr11nAggr_20; + ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20; + ah->ah_setupRxDesc = ar5416SetupRxDesc_20; + ah->ah_procRxDescFast = ar5416ProcRxDescFast_20; + ah->ah_setupTxDesc = ar5416SetupTxDesc_20; + ah->ah_fillTxDesc = ar5416FillTxDesc_20; + ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20; + ah->ah_procTxDesc = ar5416ProcTxDesc_20; + ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20; return ah; } @@ -142,7 +129,8 @@ ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev, HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah) { - a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE); + a_uint32_t host_isr = + ioread32_mac(AR_INTR_ASYNC_CAUSE); /* * Some platforms trigger our ISR before applying power to * the card, so make sure. @@ -157,8 +145,10 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) HAL_BOOL fatal_int = AH_FALSE; a_uint32_t sync_cause; - if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { - if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) { + if (ioread32_mac(AR_INTR_ASYNC_CAUSE) + & AR_INTR_MAC_IRQ) { + if ((ioread32_mac(AR_RTC_STATUS) + & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) { *masked = 0; return AH_FALSE; } @@ -167,7 +157,7 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) return AH_FALSE; } #endif - isr = OS_REG_READ(ah, AR_ISR_RAC); + isr = ioread32_mac(AR_ISR_RAC); if (isr == 0xffffffff) { *masked = 0; return AH_FALSE; @@ -187,7 +177,7 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) if (isr & AR_ISR_BCNMISC) { a_uint32_t s2_s; - s2_s = OS_REG_READ(ah, AR_ISR_S2_S); + s2_s = ioread32_mac(AR_ISR_S2_S); if (s2_s & AR_ISR_S2_GTT) { *masked |= HAL_INT_GTT; @@ -205,8 +195,8 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) a_uint32_t s0_s, s1_s; *masked |= HAL_INT_TX; - s0_s = OS_REG_READ(ah, AR_ISR_S0_S); - s1_s = OS_REG_READ(ah, AR_ISR_S1_S); + s0_s = ioread32_mac(AR_ISR_S0_S); + s1_s = ioread32_mac(AR_ISR_S1_S); ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); @@ -214,24 +204,19 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) } #ifndef AR9100 - sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); + sync_cause = ioread32_mac(AR_INTR_SYNC_CAUSE); fatal_int = ((sync_cause != AR_INTR_SPURIOUS) && - (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ? - AH_TRUE : AH_FALSE; + (sync_cause & (AR_INTR_SYNC_HOST1_FATAL + | AR_INTR_SYNC_HOST1_PERR))) ? AH_TRUE : AH_FALSE; if (AH_TRUE == fatal_int) { OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); - (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); + (void) ioread32_mac(AR_INTR_SYNC_CAUSE_CLR); } #endif return AH_TRUE; } -HAL_INT ar5416GetInterrupts(struct ath_hal *ah) -{ - return AH5416(ah)->ah_maskReg; -} - HAL_INT ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) { @@ -241,7 +226,7 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) if (omask & HAL_INT_GLOBAL) { OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); - (void) OS_REG_READ(ah, AR_IER); + (void) ioread32_mac(AR_IER); } mask = ints & HAL_INT_COMMON; @@ -269,14 +254,14 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) } OS_REG_WRITE(ah, AR_IMR, mask); - (void) OS_REG_READ(ah, AR_IMR); + (void) ioread32_mac(AR_IMR); ahp->ah_maskReg = ints; /* Re-enable interrupts if they were enabled before. */ if (ints & HAL_INT_GLOBAL) { OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); /* See explanation above... */ - (void) OS_REG_READ(ah, AR_IER); + (void) ioread32_mac(AR_IER); } OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); @@ -294,69 +279,19 @@ u_int64_t ar5416GetTsf64(struct ath_hal *ah) { u_int64_t tsf; - tsf = OS_REG_READ(ah, AR_TSF_U32); - tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32); + tsf = ioread32_mac(AR_TSF_U32); + tsf = (tsf << 32) | ioread32_mac(AR_TSF_L32); return tsf; } -a_uint32_t ar5416GetTsf32(struct ath_hal *ah) -{ - return OS_REG_READ(ah, AR_TSF_L32); -} - -void ar5416ResetTsf(struct ath_hal *ah) -{ - a_int32_t count; - - count = 0; - - while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { - count++; - if (count > 10) { - break; - } - OS_DELAY(10); - } - OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); -} - /******/ /* RX */ /******/ - -a_uint32_t ar5416GetRxDP(struct ath_hal *ath) -{ - return OS_REG_READ(ath, AR_RXDP); -} - - void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp) { OS_REG_WRITE(ah, AR_RXDP, rxdp); - HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp); -} - -void ar5416SetMulticastFilter(struct ath_hal *ah, a_uint32_t filter0, a_uint32_t filter1) -{ - OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0); - OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1); -} - -HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix) -{ - a_uint32_t val; - - if (ix >= 64) - return AH_FALSE; - if (ix >= 32) { - val = OS_REG_READ(ah, AR_MCAST_FIL1); - OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32)))); - } else { - val = OS_REG_READ(ah, AR_MCAST_FIL0); - OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<= 64) - return AH_FALSE; - if (ix >= 32) { - val = OS_REG_READ(ah, AR_MCAST_FIL1); - OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32)))); - } else { - val = OS_REG_READ(ah, AR_MCAST_FIL0); - OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<ds_rxstatus8 & AR_RxDone) == 0 - && OS_REG_READ(ah, AR_RXDP) == pa) + && ioread32_mac(AR_RXDP) == pa) return HAL_EINPROGRESS; /* @@ -547,7 +464,7 @@ HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel) */ omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL); - txcfg = OS_REG_READ(ah, AR_TXCFG); + txcfg = ioread32_mac(AR_TXCFG); curLevel = MS(txcfg, AR_FTRIG); newLevel = curLevel; @@ -575,7 +492,7 @@ HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp) * Make sure that TXE is deasserted before setting the TXDP. If TXE * is still asserted, setting TXDP will have no effect. */ - HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0); + HALASSERT((ioread32_mac(AR_Q_TXE) & (1 << q)) == 0); OS_REG_WRITE(ah, AR_QTXDP(q), txdp); @@ -588,7 +505,7 @@ HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q) HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); /* Check to be sure we're not enabling a q that has its TXD bit set. */ - HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0); + HALASSERT((ioread32_mac(AR_Q_TXD) & (1 << q)) == 0); OS_REG_WRITE(ah, AR_Q_TXE, 1 << q); @@ -602,19 +519,21 @@ a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q) HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); - npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; + npend = ioread32_mac(AR_QSTS(q)) + & AR_Q_STS_PEND_FR_CNT; if (npend == 0) { /* * Pending frame count (PFC) can momentarily go to zero * while TXE remains asserted. In other words a PFC of * zero is not sufficient to say that the queue has stopped. */ - if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) + if (ioread32_mac(AR_Q_TXE) & (1 << q)) npend = 1; } #ifdef DEBUG if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) { - if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) { + if (ioread32_mac(AR_Q_RDYTIMESHDN) + & (1 << q)) { isrPrintf("RTSD on CAB queue\n"); /* Clear the ReadyTime shutdown status bits */ OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q); @@ -689,33 +608,16 @@ HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q) return (i != 0); } -void ar5416GetTxIntrQueue(struct ath_hal *ah, a_uint32_t *txqs) -{ - struct ath_hal_5416 *ahp = AH5416(ah); - *txqs &= ahp->ah_intrTxqs; - ahp->ah_intrTxqs &= ~(*txqs); -} - -void ar5416IntrReqTxDesc_20(struct ath_hal *ah, struct ath_desc *ds) -{ - struct ar5416_desc *ads = AR5416DESC(ds); - ads->ds_ctl0 |= AR_TxIntrReq; -} - -HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, +HAL_BOOL ar5416SetupTxDesc_20(struct ath_tx_desc *ds, a_uint32_t pktLen, a_uint32_t hdrLen, HAL_PKT_TYPE type, a_uint32_t txPower, a_uint32_t txRate0, a_uint32_t txTries0, a_uint32_t keyIx, - a_uint32_t antMode, a_uint32_t flags, a_uint32_t rtsctsRate, - a_uint32_t rtsctsDuration, - a_uint32_t compicvLen, - a_uint32_t compivLen, - a_uint32_t comp) + a_uint32_t rtsctsDuration) { #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA) @@ -770,7 +672,7 @@ HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, #undef RTSCTS } -HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, +HAL_BOOL ar5416FillTxDesc_20(struct ath_tx_desc *ds, a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, const struct ath_tx_desc *ds0) { @@ -808,7 +710,7 @@ HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, return AH_TRUE; } -HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, +HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_tx_desc *ds, HAL_KEY_TYPE keyType) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -884,7 +786,7 @@ HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds) return HAL_OK; } -void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, +void ar5416Set11nTxDesc_20(struct ath_tx_desc *ds, a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower, a_uint32_t keyIx, HAL_KEY_TYPE keyType, a_uint32_t flags) @@ -916,26 +818,23 @@ void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds, ads->ds_ctl6 = SM(keyType, AR_EncrType); } -#ifdef MAGPIE_MERLIN - -void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds, +void ar5416Set11nRateScenario_20(struct ath_tx_desc *ds, a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, - a_uint32_t rtsctsDuration, HAL_11N_RATE_SERIES series[], a_uint32_t nseries, a_uint32_t flags) { - struct ar5416_desc *ads = AR5416DESC(ds); - a_uint32_t ds_ctl0; + struct ar5416_desc *ads = AR5416DESC(ds); + a_uint32_t ds_ctl0; - HALASSERT(nseries == 4); - (void)nseries; + HALASSERT(nseries == 4); + (void)nseries; - /* - * Rate control settings override - */ + /* + * Rate control settings override + */ ds_ctl0 = ads->ds_ctl0; - if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { + if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { if (flags & HAL_TXDESC_RTSENA) { ds_ctl0 &= ~AR_CTSEnable; ds_ctl0 |= AR_RTSEnable; @@ -943,94 +842,39 @@ void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds, ds_ctl0 &= ~AR_RTSEnable; ds_ctl0 |= AR_CTSEnable; } - } else { + } else { + /* this line is only difference between merlin and k2 + * Current one is for merlin */ ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable)); - } + } ads->ds_ctl0 = ds_ctl0; - ads->ds_ctl2 = set11nTries(series, 0) - | set11nTries(series, 1) - | set11nTries(series, 2) - | set11nTries(series, 3) - | (durUpdateEn ? AR_DurUpdateEn : 0); - - ads->ds_ctl3 = set11nRate(series, 0) - | set11nRate(series, 1) - | set11nRate(series, 2) - | set11nRate(series, 3); - - ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0) - | set11nPktDurRTSCTS(series, 1); - - ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2) - | set11nPktDurRTSCTS(series, 3); - - ads->ds_ctl7 = set11nRateFlags(series, 0) - | set11nRateFlags(series, 1) - | set11nRateFlags(series, 2) - | set11nRateFlags(series, 3) - | SM(rtsctsRate, AR_RTSCTSRate); -} - -#else - -void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds, - a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, - a_uint32_t rtsctsDuration, - HAL_11N_RATE_SERIES series[], a_uint32_t nseries, - a_uint32_t flags) -{ - struct ar5416_desc *ads = AR5416DESC(ds); - a_uint32_t ds_ctl0; + ads->ds_ctl2 = set11nTries(series, 0) + | set11nTries(series, 1) + | set11nTries(series, 2) + | set11nTries(series, 3) + | (durUpdateEn ? AR_DurUpdateEn : 0); - HALASSERT(nseries == 4); - (void)nseries; + ads->ds_ctl3 = set11nRate(series, 0) + | set11nRate(series, 1) + | set11nRate(series, 2) + | set11nRate(series, 3); - /* - * Rate control settings override - */ - if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { - ds_ctl0 = ads->ds_ctl0; + ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0) + | set11nPktDurRTSCTS(series, 1); - if (flags & HAL_TXDESC_RTSENA) { - ds_ctl0 &= ~AR_CTSEnable; - ds_ctl0 |= AR_RTSEnable; - } else { - ds_ctl0 &= ~AR_RTSEnable; - ds_ctl0 |= AR_CTSEnable; - } - - ads->ds_ctl0 = ds_ctl0; - } - - ads->ds_ctl2 = set11nTries(series, 0) - | set11nTries(series, 1) - | set11nTries(series, 2) - | set11nTries(series, 3) - | (durUpdateEn ? AR_DurUpdateEn : 0); + ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2) + | set11nPktDurRTSCTS(series, 3); - ads->ds_ctl3 = set11nRate(series, 0) - | set11nRate(series, 1) - | set11nRate(series, 2) - | set11nRate(series, 3); - - ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0) - | set11nPktDurRTSCTS(series, 1); - - ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2) - | set11nPktDurRTSCTS(series, 3); - - ads->ds_ctl7 = set11nRateFlags(series, 0) - | set11nRateFlags(series, 1) - | set11nRateFlags(series, 2) - | set11nRateFlags(series, 3) - | SM(rtsctsRate, AR_RTSCTSRate); + ads->ds_ctl7 = set11nRateFlags(series, 0) + | set11nRateFlags(series, 1) + | set11nRateFlags(series, 2) + | set11nRateFlags(series, 3) + | SM(rtsctsRate, AR_RTSCTSRate); } -#endif - -void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t aggrLen, +void ar5416Set11nAggrFirst_20(struct ath_tx_desc *ds, a_uint32_t aggrLen, a_uint32_t numDelims) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -1042,7 +886,7 @@ void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint SM(numDelims, AR_PadDelim); } -void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t numDelims) +void ar5416Set11nAggrMiddle_20(struct ath_tx_desc *ds, a_uint32_t numDelims) { struct ar5416_desc *ads = AR5416DESC(ds); a_uint32_t ctl6; @@ -1059,7 +903,7 @@ void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uin ads->ds_ctl6 = ctl6; } -void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_tx_desc *ds) +void ar5416Set11nAggrLast_20(struct ath_tx_desc *ds) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -1068,14 +912,14 @@ void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_tx_desc *ds) ads->ds_ctl6 &= ~AR_PadDelim; } -void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_tx_desc *ds) +void ar5416Clr11nAggr_20(struct ath_tx_desc *ds) { struct ar5416_desc *ads = AR5416DESC(ds); ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); } -void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds, +void ar5416Set11nBurstDuration_20(struct ath_tx_desc *ds, a_uint32_t burstDuration) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -1084,7 +928,7 @@ void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds, ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur); } -void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_tx_desc *ds, +void ar5416Set11nVirtualMoreFrag_20(struct ath_tx_desc *ds, a_uint32_t vmf) { struct ar5416_desc *ads = AR5416DESC(ds);