X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=target_firmware%2Fmagpie_fw_dev%2Ftarget%2Finc%2Fusb_defs.h;h=ce2e24e26f758f8862d3501e13c48149ac10c8f3;hb=6f2219c1ab25d1dfbb5d2de6508212a27f9d7e9c;hp=109071a20ed7d960ce9fe5dfccb25f604f68e912;hpb=a985c30bbfbdd1539e98e9e0b84bbff20d8fa0a9;p=open-ath9k-htc-firmware.git diff --git a/target_firmware/magpie_fw_dev/target/inc/usb_defs.h b/target_firmware/magpie_fw_dev/target/inc/usb_defs.h index 109071a..ce2e24e 100755 --- a/target_firmware/magpie_fw_dev/target/inc/usb_defs.h +++ b/target_firmware/magpie_fw_dev/target/inc/usb_defs.h @@ -63,15 +63,14 @@ #define mADDR(addr) (*mpADDR(addr)) #define muADDR(addr) ((uint16_t) (&(addr))) -#define USB_BYTE_REG_WRITE(addr, val) HAL_BYTE_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3), (val)) -#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3)) -//#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr)) +#define USB_BYTE_REG_WRITE(addr, val) iowrite8_usb(addr, val) +#define USB_BYTE_REG_READ(addr) ioread8_usb(addr) -#define USB_HALF_WORD_REG_WRITE(addr, val) HAL_HALF_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr), (val)) -#define USB_HALF_WORD_REG_READ(addr) HAL_HALF_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr)) +#define USB_HALF_WORD_REG_WRITE(addr, val) iowrite16_usb(addr, val) +#define USB_HALF_WORD_REG_READ(addr) ioread16_usb(addr) -#define USB_WORD_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr), (val)) -#define USB_WORD_REG_READ(addr) HAL_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr)) +#define USB_WORD_REG_WRITE(addr, val) iowrite32_usb(addr, val) +#define USB_WORD_REG_READ(addr) ioread32_usb(addr) /************************** Register Deinition ***************************/ @@ -138,7 +137,7 @@ #define ZM_ADDR_CONV 0x0 #define ZM_CBUS_FIFO_SIZE_REG (ZM_CBUS_FIFO_SIZE_OFFSET^ZM_ADDR_CONV) - + #define ZM_CBUS_CTRL_REG (cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET^ZM_ADDR_CONV) #define ZM_MAIN_CTRL_REG (ZM_MAIN_CTRL_OFFSET^ZM_ADDR_CONV) @@ -180,7 +179,7 @@ #define ZM_INTR_SOURCE_2_REG (ZM_INTR_SOURCE_2_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_SOURCE_3_REG (ZM_INTR_SOURCE_3_OFFSET^ZM_ADDR_CONV) - + #define ZM_INTR_SOURCE_4_REG (ZM_INTR_SOURCE_4_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_SOURCE_5_REG (ZM_INTR_SOURCE_5_OFFSET^ZM_ADDR_CONV) @@ -240,7 +239,7 @@ USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&~BIT0) #define mUsbRmWkupSet() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0) - + #define mUsbGlobIntEnable() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT2) @@ -297,7 +296,7 @@ #if (HS_C1_INTERFACE_NUMBER >= 1) // Interface 0 #define HS_C1_I0_ALT_NUMBER 0X01 - #if (HS_C1_I0_ALT_NUMBER >= 1) + #if (HS_C1_I0_ALT_NUMBER >= 1) // AlternateSetting 0X00 #define HS_C1_I0_A0_bInterfaceNumber 0X00 #define HS_C1_I0_A0_bAlternateSetting 0X00 @@ -851,7 +850,7 @@ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// #define USB_ENABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0)) // upstream DMA enable - + #define USB_DISABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))) // upstream DMA disable @@ -876,10 +875,10 @@ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// #define USB_ENABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ - (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)) // hp downstream DMA enable + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)) // hp downstream DMA enable #define USB_DISABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ - (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))) // hp downstream DMA disable + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))) // hp downstream DMA disable #define USB_HP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT7))) // hpQ packet mode @@ -888,9 +887,9 @@ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT7)) // hpQ stream mode /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -#define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)) // mp downstream DMA enable +#define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)) // mp downstream DMA enable -#define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))) // mp downstream DMA disable +#define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))) // mp downstream DMA disable #define USB_MP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT10))) // hpQ packet mode @@ -932,7 +931,7 @@ USB_ENABLE_HP_DN_DMA(); #define USB_STREAM_HOST_BUF_SIZE(size) USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ - (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size))); + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size))); #define USB_STREAM_TIMEOUT(time_cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, time_cnt); // set stream mode timeout critirea #define USB_STREAM_AGG_PKT_CNT(cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, cnt); // set stream mode packet buffer critirea