X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=include%2Fshared%2Fhw.h;h=13b7b754cc4dfa1226ed4191dfeb78c538d0d8f6;hb=65dd584c008fdc28e8398bacfdb311b19ae80507;hp=fa40ebdfc55366a26121bd961ab1b691f5d6295a;hpb=0629466a3ee72bd525639a57af25a0a56e26101f;p=carl9170fw.git

diff --git a/include/shared/hw.h b/include/shared/hw.h
index fa40ebd..13b7b75 100644
--- a/include/shared/hw.h
+++ b/include/shared/hw.h
@@ -375,8 +375,8 @@
 
 #define	AR9170_MAC_REG_BCN_PLCP			(AR9170_MAC_REG_BASE + 0xd90)
 #define	AR9170_MAC_REG_BCN_CTRL			(AR9170_MAC_REG_BASE + 0xd94)
-#define		AR9170_BCN_READY			0x01
-#define		AR9170_BCN_LOCK				0x02
+#define		AR9170_BCN_CTRL_READY			0x01
+#define		AR9170_BCN_CTRL_LOCK			0x02
 
 #define AR9170_MAC_REG_BCN_CURR_ADDR		(AR9170_MAC_REG_BASE + 0xd98)
 #define	AR9170_MAC_REG_BCN_COUNT		(AR9170_MAC_REG_BASE + 0xd9c)
@@ -387,26 +387,6 @@
 
 #define	AR9170_MAC_REG_DMA_TXQX_ADDR_CURR	(AR9170_MAC_REG_BASE + 0xdc0)
 
-#define	AR9170_PWR_REG_BASE			0x1d4000
-
-#define AR9170_PWR_REG_POWER_STATE		(AR9170_PWR_REG_BASE + 0x000)
-
-#define	AR9170_PWR_REG_ADDA_BB			(AR9170_PWR_REG_BASE + 0x004)
-#define		AR9170_PWR_ADDA_BB_USB_FIFO_RESET	0x00000005
-#define		AR9170_PWR_ADDA_BB_COLD_RESET		0x00000800
-#define		AR9170_PWR_ADDA_BB_WARM_RESET		0x00000400
-
-#define	AR9170_PWR_REG_CLOCK_SEL		(AR9170_PWR_REG_BASE + 0x008)
-#define		AR9170_PWR_CLK_AHB_40MHZ		0
-#define		AR9170_PWR_CLK_AHB_20_22MHZ		1
-#define		AR9170_PWR_CLK_AHB_40_44MHZ		2
-#define		AR9170_PWR_CLK_AHB_80_88MHZ		3
-#define		AR9170_PWR_CLK_DAC_160_INV_DLY		0x70
-
-#define	AR9170_PWR_REG_CHIP_REVISION		(AR9170_PWR_REG_BASE + 0x010)
-#define AR9170_PWR_REG_PLL_ADDAC		(AR9170_PWR_REG_BASE + 0x014)
-#define	AR9170_PWR_REG_WATCH_DOG_MAGIC		(AR9170_PWR_REG_BASE + 0x020)
-
 /* Random number generator */
 #define	AR9170_RAND_REG_BASE			0x1d0000
 
@@ -460,6 +440,34 @@
 #define	AR9170_INT_REG_FIQ_ENCODE		(AR9170_INT_REG_BASE + 0x020)
 #define	AR9170_INT_INT_IRQ_ENCODE		(AR9170_INT_REG_BASE + 0x024)
 
+/* Power Management */
+#define	AR9170_PWR_REG_BASE			0x1d4000
+
+#define AR9170_PWR_REG_POWER_STATE		(AR9170_PWR_REG_BASE + 0x000)
+
+#define	AR9170_PWR_REG_RESET			(AR9170_PWR_REG_BASE + 0x004)
+#define		AR9170_PWR_RESET_COMMIT_RESET_MASK	BIT(0)
+#define		AR9170_PWR_RESET_WLAN_MASK		BIT(1)
+#define		AR9170_PWR_RESET_DMA_MASK		BIT(2)
+#define		AR9170_PWR_RESET_BRIDGE_MASK		BIT(3)
+#define		AR9170_PWR_RESET_AHB_MASK		BIT(9)
+#define		AR9170_PWR_RESET_BB_WARM_RESET		BIT(10)
+#define		AR9170_PWR_RESET_BB_COLD_RESET		BIT(11)
+#define		AR9170_PWR_RESET_ADDA_CLK_COLD_RESET	BIT(12)
+#define		AR9170_PWR_RESET_PLL			BIT(13)
+#define		AR9170_PWR_RESET_USB_PLL		BIT(14)
+
+#define	AR9170_PWR_REG_CLOCK_SEL		(AR9170_PWR_REG_BASE + 0x008)
+#define		AR9170_PWR_CLK_AHB_40MHZ		0
+#define		AR9170_PWR_CLK_AHB_20_22MHZ		1
+#define		AR9170_PWR_CLK_AHB_40_44MHZ		2
+#define		AR9170_PWR_CLK_AHB_80_88MHZ		3
+#define		AR9170_PWR_CLK_DAC_160_INV_DLY		0x70
+
+#define	AR9170_PWR_REG_CHIP_REVISION		(AR9170_PWR_REG_BASE + 0x010)
+#define AR9170_PWR_REG_PLL_ADDAC		(AR9170_PWR_REG_BASE + 0x014)
+#define	AR9170_PWR_REG_WATCH_DOG_MAGIC		(AR9170_PWR_REG_BASE + 0x020)
+
 /* Faraday USB Controller */
 #define	AR9170_USB_REG_BASE			0x1e1000
 
@@ -558,17 +566,21 @@
 
 #define	AR9170_USB_REG_FIFO_SIZE		(AR9170_USB_REG_BASE + 0x100)
 #define	AR9170_USB_REG_DMA_CTL			(AR9170_USB_REG_BASE + 0x108)
-#define		AR9170_DMA_CTL_ENABLE_TO_DEVICE		BIT(0)
-#define		AR9170_DMA_CTL_ENABLE_FROM_DEVICE	BIT(1)
-#define		AR9170_DMA_CTL_HIGH_SPEED		BIT(2)
-#define		AR9170_DMA_CTL_UP_PACKET_MODE		BIT(3)
-#define		AR9170_DMA_CTL_UP_STREAM_S		4
-#define		AR9170_DMA_CTL_UP_STREAM		(3 << 4)
-#define		AR9170_DMA_CTL_UP_STREAM_4K		(0 << 4)
-#define		AR9170_DMA_CTL_UP_STREAM_8K		(1 << 4)
-#define		AR9170_DMA_CTL_UP_STREAM_16K		(2 << 4)
-#define		AR9170_DMA_CTL_UP_STREAM_32K		(3 << 4)
-#define		AR9170_DMA_CTL_DOWN_STREAM		BIT(6)
+#define		AR9170_USB_DMA_CTL_ENABLE_TO_DEVICE	BIT(0)
+#define		AR9170_USB_DMA_CTL_ENABLE_FROM_DEVICE	BIT(1)
+#define		AR9170_USB_DMA_CTL_HIGH_SPEED		BIT(2)
+#define		AR9170_USB_DMA_CTL_UP_PACKET_MODE	BIT(3)
+#define		AR9170_USB_DMA_CTL_UP_STREAM_S		4
+#define		AR9170_USB_DMA_CTL_UP_STREAM		(BIT(4) | BIT(5))
+#define		AR9170_USB_DMA_CTL_UP_STREAM_4K		(0)
+#define		AR9170_USB_DMA_CTL_UP_STREAM_8K		BIT(4)
+#define		AR9170_USB_DMA_CTL_UP_STREAM_16K	BIT(5)
+#define		AR9170_USB_DMA_CTL_UP_STREAM_32K	(BIT(4) | BIT(5))
+#define		AR9170_USB_DMA_CTL_DOWN_STREAM		BIT(6)
+
+#define	AR9170_USB_REG_DMA_STATUS		(AR9170_USB_REG_BASE + 0x10c)
+#define		AR9170_USB_DMA_STATUS_UP_IDLE		BIT(8)
+#define		AR9170_USB_DMA_STATUS_DN_IDLE		BIT(16)
 
 #define	AR9170_USB_REG_MAX_AGG_UPLOAD		(AR9170_USB_REG_BASE + 0x110)
 #define	AR9170_USB_REG_UPLOAD_TIME_CTL		(AR9170_USB_REG_BASE + 0x114)