X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=include%2Fshared%2Fhw.h;h=0db874abde500750f7365ed6a9c254b297d03025;hb=91978587bb5fc143a0c61d1b30213a3c400f27ea;hp=90c84a60b69894d0e825ab0da2e92b70a28174f4;hpb=10280c74bd62f63b1483bf1b17d40b0eeb35845e;p=carl9170fw.git diff --git a/include/shared/hw.h b/include/shared/hw.h index 90c84a6..0db874a 100644 --- a/include/shared/hw.h +++ b/include/shared/hw.h @@ -4,7 +4,7 @@ * Register map, hardware-specific definitions * * Copyright 2008, Johannes Berg - * Copyright 2009, 2010, Christian Lamparter + * Copyright 2009-2011 Christian Lamparter * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -174,6 +174,7 @@ #define AR9170_MAC_SNIFFER_ENABLE_PROMISC BIT(0) #define AR9170_MAC_SNIFFER_DEFAULTS 0x02000000 #define AR9170_MAC_REG_ENCRYPTION (AR9170_MAC_REG_BASE + 0x678) +#define AR9170_MAC_ENCRYPTION_MGMT_RX_SOFTWARE BIT(2) #define AR9170_MAC_ENCRYPTION_RX_SOFTWARE BIT(3) #define AR9170_MAC_ENCRYPTION_DEFAULTS 0x70 @@ -222,6 +223,12 @@ #define AR9170_MAC_REG_TX_BLOCKACKS (AR9170_MAC_REG_BASE + 0x6c0) #define AR9170_MAC_REG_NAV_COUNT (AR9170_MAC_REG_BASE + 0x6c4) #define AR9170_MAC_REG_BACKOFF_STATUS (AR9170_MAC_REG_BASE + 0x6c8) +#define AR9170_MAC_BACKOFF_CCA BIT(24) +#define AR9170_MAC_BACKOFF_TX_PEX BIT(25) +#define AR9170_MAC_BACKOFF_RX_PE BIT(26) +#define AR9170_MAC_BACKOFF_MD_READY BIT(27) +#define AR9170_MAC_BACKOFF_TX_PE BIT(28) + #define AR9170_MAC_REG_TX_RETRY (AR9170_MAC_REG_BASE + 0x6cc) #define AR9170_MAC_REG_TX_COMPLETE (AR9170_MAC_REG_BASE + 0x6d4) @@ -357,7 +364,18 @@ #define AR9170_MAC_REG_DMA_WLAN_STATUS (AR9170_MAC_REG_BASE + 0xd38) #define AR9170_MAC_REG_DMA_STATUS (AR9170_MAC_REG_BASE + 0xd3c) - +#define AR9170_MAC_REG_DMA_TXQ_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd40) +#define AR9170_MAC_REG_DMA_TXQ0_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd40) +#define AR9170_MAC_REG_DMA_TXQ1_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd44) +#define AR9170_MAC_REG_DMA_TXQ2_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd48) +#define AR9170_MAC_REG_DMA_TXQ3_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd4c) +#define AR9170_MAC_REG_DMA_TXQ4_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd50) +#define AR9170_MAC_REG_DMA_TXQ0Q1_LEN (AR9170_MAC_REG_BASE + 0xd54) +#define AR9170_MAC_REG_DMA_TXQ2Q3_LEN (AR9170_MAC_REG_BASE + 0xd58) +#define AR9170_MAC_REG_DMA_TXQ4_LEN (AR9170_MAC_REG_BASE + 0xd5c) + +#define AR9170_MAC_REG_DMA_TXQX_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd74) +#define AR9170_MAC_REG_DMA_TXQX_FAIL_ADDR (AR9170_MAC_REG_BASE + 0xd78) #define AR9170_MAC_REG_TXRX_MPI (AR9170_MAC_REG_BASE + 0xd7c) #define AR9170_MAC_TXRX_MPI_TX_MPI_MASK 0x0000000f #define AR9170_MAC_TXRX_MPI_TX_TO_MASK 0x0000fff0 @@ -366,7 +384,7 @@ #define AR9170_MAC_REG_BCN_ADDR (AR9170_MAC_REG_BASE + 0xd84) #define AR9170_MAC_REG_BCN_LENGTH (AR9170_MAC_REG_BASE + 0xd88) -#define AR9170_MAC_BCN_LENGTH_MAX 256 +#define AR9170_MAC_BCN_LENGTH_MAX (512 - 32) #define AR9170_MAC_REG_BCN_STATUS (AR9170_MAC_REG_BASE + 0xd8c) @@ -377,10 +395,40 @@ #define AR9170_MAC_REG_BCN_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd98) #define AR9170_MAC_REG_BCN_COUNT (AR9170_MAC_REG_BASE + 0xd9c) - - #define AR9170_MAC_REG_BCN_HT1 (AR9170_MAC_REG_BASE + 0xda0) +#define AR9170_MAC_BCN_HT1_HT_EN BIT(0) +#define AR9170_MAC_BCN_HT1_GF_PMB BIT(1) +#define AR9170_MAC_BCN_HT1_SP_EXP BIT(2) +#define AR9170_MAC_BCN_HT1_TX_BF BIT(3) +#define AR9170_MAC_BCN_HT1_PWR_CTRL_S 4 +#define AR9170_MAC_BCN_HT1_PWR_CTRL 0x70 +#define AR9170_MAC_BCN_HT1_TX_ANT1 BIT(7) +#define AR9170_MAC_BCN_HT1_TX_ANT0 BIT(8) +#define AR9170_MAC_BCN_HT1_NUM_LFT_S 9 +#define AR9170_MAC_BCN_HT1_NUM_LFT 0x600 +#define AR9170_MAC_BCN_HT1_BWC_20M_EXT BIT(16) +#define AR9170_MAC_BCN_HT1_BWC_40M_SHARED BIT(17) +#define AR9170_MAC_BCN_HT1_BWC_40M_DUP (BIT(16) | BIT(17)) +#define AR9170_MAC_BCN_HT1_BF_MCS_S 18 +#define AR9170_MAC_BCN_HT1_BF_MCS 0x1c0000 +#define AR9170_MAC_BCN_HT1_TPC_S 21 +#define AR9170_MAC_BCN_HT1_TPC 0x7e00000 +#define AR9170_MAC_BCN_HT1_CHAIN_MASK_S 27 +#define AR9170_MAC_BCN_HT1_CHAIN_MASK 0x38000000 + #define AR9170_MAC_REG_BCN_HT2 (AR9170_MAC_REG_BASE + 0xda4) +#define AR9170_MAC_BCN_HT2_MCS_S 0 +#define AR9170_MAC_BCN_HT2_MCS 0x7f +#define AR9170_MAC_BCN_HT2_BW40 BIT(8) +#define AR9170_MAC_BCN_HT2_SMOOTHING BIT(9) +#define AR9170_MAC_BCN_HT2_SS BIT(10) +#define AR9170_MAC_BCN_HT2_NSS BIT(11) +#define AR9170_MAC_BCN_HT2_STBC_S 12 +#define AR9170_MAC_BCN_HT2_STBC 0x3000 +#define AR9170_MAC_BCN_HT2_ADV_COD BIT(14) +#define AR9170_MAC_BCN_HT2_SGI BIT(15) +#define AR9170_MAC_BCN_HT2_LEN_S 16 +#define AR9170_MAC_BCN_HT2_LEN 0xffff0000 #define AR9170_MAC_REG_DMA_TXQX_ADDR_CURR (AR9170_MAC_REG_BASE + 0xdc0) @@ -602,6 +650,10 @@ #define AR9170_USB_REG_MAX_AGG_UPLOAD (AR9170_USB_REG_BASE + 0x110) #define AR9170_USB_REG_UPLOAD_TIME_CTL (AR9170_USB_REG_BASE + 0x114) + +#define AR9170_USB_REG_WAKE_UP (AR9170_USB_REG_BASE + 0x120) +#define AR9170_USB_WAKE_UP_WAKE BIT(0) + #define AR9170_USB_REG_CBUS_CTRL (AR9170_USB_REG_BASE + 0x1f0) #define AR9170_USB_CBUS_CTRL_BUFFER_END (BIT(1))