X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=carlfw%2Fsrc%2Frf.c;h=9537c2a747f4d3d48849c4b36e45884f6ccd4e0e;hb=e8d747355467293087e6818a19073627b0528fce;hp=703bd4281d2492e37a9642e9728bac7ff44cd06e;hpb=7fe56f5344c292bede880f351a0d8eb710898c03;p=carl9170fw.git

diff --git a/carlfw/src/rf.c b/carlfw/src/rf.c
index 703bd42..9537c2a 100644
--- a/carlfw/src/rf.c
+++ b/carlfw/src/rf.c
@@ -6,7 +6,7 @@
  * Copyright (c) 2000-2005 ZyDAS Technology Corporation
  * Copyright (c) 2007-2009 Atheros Communications, Inc.
  * Copyright	2009	Johannes Berg <johannes@sipsolutions.net>
- * Copyright 2009, 2010 Christian Lamparter <chunkeey@googlemail.com>
+ * Copyright 2009-2011	Christian Lamparter <chunkeey@googlemail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -136,7 +136,7 @@ static uint32_t AGC_calibration(uint32_t loop)
 	uint32_t wrdata;
 	uint32_t ret;
 
-#define AGC_CAL_NF	(AR9170_PHY_AGC_CONTROL_CAL | AR9170_PHY_AGC_CONTROL_NF);
+#define AGC_CAL_NF	(AR9170_PHY_AGC_CONTROL_CAL | AR9170_PHY_AGC_CONTROL_NF)
 
 	wrdata = get_async(AR9170_PHY_REG_AGC_CONTROL) | AGC_CAL_NF;
 	set(AR9170_PHY_REG_AGC_CONTROL, wrdata);
@@ -144,14 +144,10 @@ static uint32_t AGC_calibration(uint32_t loop)
 	ret = get_async(AR9170_PHY_REG_AGC_CONTROL) & AGC_CAL_NF;
 
 	/* sitesurvey : 100 ms / current connected 200 ms */
-	while (loop && ret != 0x0) {
-		ret = get_async(AR9170_PHY_REG_AGC_CONTROL) & AGC_CAL_NF;
-
-		if (ret == 0)
-			break;
-
+	while ((ret != 0) && loop--) {
 		udelay(100);
-		loop--;
+
+		ret = get_async(AR9170_PHY_REG_AGC_CONTROL) & AGC_CAL_NF;
 	}
 
 	/* return the AGC/Noise calibration state to the driver */
@@ -185,10 +181,6 @@ static uint32_t rf_init(const uint32_t delta_slope_coeff_exp,
 		set(AR9170_PHY_REG_ANALOG_SWAP, AR9170_PHY_ANALOG_SWAP_AB |
 						AR9170_PHY_ANALOG_SWAP_ALT_CHAIN);
 
-		/* configure mask */
-		set(AR9170_PHY_REG_RX_CHAINMASK, 0x5);	/* chain 0 + chain 2 */
-		set(AR9170_PHY_REG_CAL_CHAINMASK, 0x5);	/* chain 0 + chain 2 */
-
 		/* Activate BB */
 		set(AR9170_PHY_REG_ACTIVE, AR9170_PHY_ACTIVE_EN);
 		delay(10);
@@ -207,10 +199,13 @@ void rf_cmd(const struct carl9170_cmd *cmd, struct carl9170_rsp *resp)
 	fw.phy.ht_settings = cmd->rf_init.ht_settings;
 	fw.phy.frequency = cmd->rf_init.freq;
 
+	/*
+	 * Is the clock controlled by the PHY?
+	 */
 	if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG)
-		clock_set(true, AHB_80_88MHZ);
+		clock_set(AHB_80_88MHZ, true);
 	else
-		clock_set(true, AHB_40_44MHZ);
+		clock_set(AHB_40_44MHZ, true);
 
 	ret = rf_init(le32_to_cpu(cmd->rf_init.delta_slope_coeff_exp),
 		      le32_to_cpu(cmd->rf_init.delta_slope_coeff_man),
@@ -223,7 +218,6 @@ void rf_cmd(const struct carl9170_cmd *cmd, struct carl9170_rsp *resp)
 	resp->rf_init_res.ret = cpu_to_le32(ret);
 }
 
-#ifdef CONFIG_CARL9170FW_PSM
 void rf_psm(void)
 {
 	u32 bank3;
@@ -252,7 +246,7 @@ void rf_psm(void)
 		/* Synthesizer off + RX off */
 		bank3 = 0x00400018;
 
-		clock_set(true, AHB_20_22MHZ);
+		clock_set(AHB_20_22MHZ, false);
 	} else {
 		/* advance to the next PSM step */
 		fw.phy.psm.state--;
@@ -270,19 +264,18 @@ void rf_psm(void)
 			bank3 = 0x01420098;
 
 			if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG)
-				clock_set(true, AHB_80_88MHZ);
+				clock_set(AHB_80_88MHZ, true);
 			else
-				clock_set(true, AHB_40_44MHZ);
+				clock_set(AHB_40_44MHZ, true);
 		} else {
 			return ;
 		}
 	}
 
-	if (fw.phy.frequency < 30000000)
+	if (fw.phy.frequency < 3000000)
 		bank3 |= 0x00800000;
 
 	set(0x1c58f0, bank3);
 }
-#endif /* CONFIG_CARL9170FW_PSM */
 
 #endif /* CONFIG_CARL9170FW_RADIO_FUNCTIONS */