X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=assembler%2Fmain.c;h=8abe03c8fbbe51ac3371b0c9990ce313f6aa6dd3;hb=74d3a3ff50e1dbf14732fb63f2c5ede7fe551b8a;hp=461b0d8126cca3764300bf393fd1ce170122f253;hpb=4366b5ddfc844ad72d9fd8e62418307c70407154;p=b43-tools.git

diff --git a/assembler/main.c b/assembler/main.c
index 461b0d8..8abe03c 100644
--- a/assembler/main.c
+++ b/assembler/main.c
@@ -482,6 +482,27 @@ static struct code_output * do_assemble_insn(struct assembler_context *ctx,
 	return out;
 }
 
+static void do_assemble_ret(struct assembler_context *ctx,
+			    struct instruction *insn,
+			    unsigned int opcode)
+{
+	struct code_output *out;
+
+	/* Get the previous instruction and check whether it
+	 * is a jump instruction. */
+	list_for_each_entry_reverse(out, &ctx->output, list) {
+		/* Search the last insn. */
+		if (out->type == OUT_INSN) {
+			if (out->is_jump_insn) {
+				asm_warn(ctx, "RET instruction directly after "
+					 "jump instruction. The hardware won't like this.");
+			}
+			break;
+		}
+	}
+	do_assemble_insn(ctx, insn, opcode);
+}
+
 static unsigned int merge_ext_into_opcode(struct assembler_context *ctx,
 					  unsigned int opbase,
 					  struct instruction *insn)
@@ -855,22 +876,24 @@ static void assemble_instruction(struct assembler_context *ctx,
 		out->is_jump_insn = 1;
 		break;
 	case OP_CALL:
+		if (ctx->arch != 5)
+			asm_error(ctx, "'call' instruction is only supported on arch 5");
 		do_assemble_insn(ctx, insn, 0x002);
 		break;
+	case OP_CALLS:
+		if (ctx->arch != 15)
+			asm_error(ctx, "'calls' instruction is only supported on arch 15");
+		do_assemble_insn(ctx, insn, 0x004);
+		break;
 	case OP_RET:
-		/* Get the previous instruction and check whether it
-		 * is a jump instruction. */
-		list_for_each_entry_reverse(out, &ctx->output, list) {
-			/* Search the last insn. */
-			if (out->type == OUT_INSN) {
-				if (out->is_jump_insn) {
-					asm_warn(ctx, "RET instruction directly after "
-						 "jump instruction. The hardware won't like this.");
-				}
-				break;
-			}
-		}
-		do_assemble_insn(ctx, insn, 0x003);
+		if (ctx->arch != 5)
+			asm_error(ctx, "'ret' instruction is only supported on arch 5");
+		do_assemble_ret(ctx, insn, 0x003);
+		break;
+	case OP_RETS:
+		if (ctx->arch != 15)
+			asm_error(ctx, "'rets' instruction is only supported on arch 15");
+		do_assemble_insn(ctx, insn, 0x005);
 		break;
 	case OP_TKIPH:
 	case OP_TKIPHS:
@@ -1081,7 +1104,7 @@ static void emit_code(struct assembler_context *ctx)
 		exit(1);
 	}
 	if (IS_VERBOSE_DEBUG)
-		fprintf(stderr, "\nCode:\n");
+		printf("\nCode:\n");
 
 	list_for_each_entry(c, &ctx->output, list) {
 		switch (c->type) {
@@ -1093,7 +1116,7 @@ static void emit_code(struct assembler_context *ctx)
 		}
 	}
 
-	switch (output_format) {
+	switch (cmdargs.outformat) {
 	case FMT_RAW_LE32:
 	case FMT_RAW_BE32:
 		/* Nothing */
@@ -1129,7 +1152,7 @@ static void emit_code(struct assembler_context *ctx)
 		switch (c->type) {
 		case OUT_INSN:
 			if (IS_VERBOSE_DEBUG) {
-				fprintf(stderr, "%03X %03X,%03X,%03X\n",
+				printf("%03X %04X,%04X,%04X\n",
 					c->opcode,
 					c->operands[0].u.operand,
 					c->operands[1].u.operand,
@@ -1156,7 +1179,7 @@ static void emit_code(struct assembler_context *ctx)
 					  ctx->arch);
 			}
 
-			switch (output_format) {
+			switch (cmdargs.outformat) {
 			case FMT_B43:
 			case FMT_RAW_BE32:
 				code = ((code & (uint64_t)0xFFFFFFFF00000000ULL) >> 32) |
@@ -1192,7 +1215,7 @@ static void emit_code(struct assembler_context *ctx)
 		}
 	}
 
-	if (arg_print_sizes) {
+	if (cmdargs.print_sizes) {
 		printf("%s:  text = %u instructions (%u bytes)\n",
 		       fn, insn_count,
 		       (unsigned int)(insn_count * sizeof(uint64_t)));