X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=assembler%2Fmain.c;h=54252dabe95fe89b762524ced673fd3d4a80fd5c;hb=3bd4f014e1ae2af49b2cbdd94a86c07559aacbce;hp=f2d2826aa5b2e804bf75506347d8b3b8a0f63aed;hpb=f981680e63cf6efb80b270d5ba2d30ffcbbf0ef4;p=b43-tools.git

diff --git a/assembler/main.c b/assembler/main.c
index f2d2826..54252da 100644
--- a/assembler/main.c
+++ b/assembler/main.c
@@ -488,8 +488,8 @@ static unsigned int merge_external_jmp_into_opcode(struct assembler_context *ctx
 
 	/* This instruction has two fake r0 operands
 	 * at position 0 and 1. */
-	fake = xmalloc(sizeof(struct operand));
-	fake_reg = xmalloc(sizeof(struct operand));
+	fake = xmalloc(sizeof(*fake));
+	fake_reg = xmalloc(sizeof(*fake_reg));
 	fake->type = OPER_REG;
 	fake->u.reg = fake_reg;
 	fake_reg->type = GPR;
@@ -571,19 +571,20 @@ static void emulate_jmp_insn(struct assembler_context *ctx,
 {
 	struct instruction em_insn;
 	struct operlist em_ol;
-	struct operand em_op;
-	struct immediate em_imm;
-
-	/* This is a pseudo-OP. We emulate it by JE */
-
-	em_insn.op = OP_JE;
-	em_imm.imm = 1;
-	em_op.type = OPER_IMM;
-	em_op.u.imm = &em_imm;
-	em_ol.oper[0] = &em_op;
-	em_ol.oper[1] = &em_op;
-	em_ol.oper[2] = insn->operands->oper[0];
+	struct immediate em_condition;
+	struct operand em_cond_op;
+
+	/* This is a pseudo-OP. We emulate it with
+	 * JEXT 0x7F, target */
+
+	em_insn.op = OP_JEXT;
+	em_condition.imm = 0x7F; /* Ext cond: Always true */
+	em_cond_op.type = OPER_IMM;
+	em_cond_op.u.imm = &em_condition;
+	em_ol.oper[0] = &em_cond_op;
+	em_ol.oper[1] = insn->operands->oper[0]; /* Target */
 	em_insn.operands = &em_ol;
+
 	assemble_instruction(ctx, &em_insn); /* recurse */
 }
 
@@ -816,13 +817,16 @@ static void assemble_instruction(struct assembler_context *ctx,
 		do_assemble_insn(ctx, insn, 0x002);
 		break;
 	case OP_RET:
-		if (!list_empty(&ctx->output)) {
-			/* Get the previous instruction and check whether it
-			 * is a jump instruction. */
-			out = list_entry(ctx->output.prev, struct code_output, list);
-			if (out->is_jump_insn) {
-				asm_error(ctx, "RET instruction directly after "
-					  "jump instruction. The hardware won't like this.");
+		/* Get the previous instruction and check whether it
+		 * is a jump instruction. */
+		list_for_each_entry_reverse(out, &ctx->output, list) {
+			/* Search the last insn. */
+			if (out->type == OUT_INSN) {
+				if (out->is_jump_insn) {
+					asm_warn(ctx, "RET instruction directly after "
+						 "jump instruction. The hardware won't like this.");
+				}
+				break;
 			}
 		}
 		do_assemble_insn(ctx, insn, 0x003);
@@ -1022,21 +1026,17 @@ does_not_exist:
 static void emit_code(struct assembler_context *ctx)
 {
 	FILE *fd;
-	char *fn;
-	size_t fn_len;
+	const char *fn;
 	struct code_output *c;
 	uint64_t code;
 	unsigned char outbuf[8];
 	unsigned int insn_count = 0;
 	struct fw_header hdr;
 
-	fn_len = strlen(outfile_name) + 20;
-	fn = xmalloc(fn_len);
-	snprintf(fn, fn_len, "%s.ucode", outfile_name);
+	fn = outfile_name;
 	fd = fopen(fn, "w+");
 	if (!fd) {
 		fprintf(stderr, "Could not open microcode output file \"%s\"\n", fn);
-		free(fn);
 		exit(1);
 	}
 	if (IS_VERBOSE_DEBUG)
@@ -1121,8 +1121,13 @@ static void emit_code(struct assembler_context *ctx)
 			break;
 		}
 	}
+
+	if (arg_print_sizes) {
+		printf("%s:  text = %u instructions (%u bytes)\n",
+		       fn, insn_count, insn_count * sizeof(uint64_t));
+	}
+
 	fclose(fd);
-	free(fn);
 }
 
 static void assemble(void)