return ioread32_mac(0x407c) & 0x0000ffff;
} else if (addr > 0xffff)
/* SoC registers */
- return HAL_WORD_REG_READ(addr);
+ return ioread32(addr);
else
/* MAC registers */
return ioread32_mac(addr);
if(reset_pll == 0) {
#if defined(PROJECT_K2)
/* here we write to core register */
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
+ iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
/* and here to mac register */
- ath_hal_reg_write_target(ah, 0x786c,
+ iowrite32_mac(0x786c,
ioread32_mac(0x786c) | 0x6000000);
- ath_hal_reg_write_target(ah, 0x786c,
+ iowrite32_mac(0x786c,
ioread32_mac(0x786c) & (~0x6000000));
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
+ iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
#elif defined(PROJECT_MAGPIE) && !defined (FPGA)
- ath_hal_reg_write_target(ah, 0x7890,
+ iowrite32_mac(0x7890,
ioread32_mac(0x7890) | 0x1800000);
- ath_hal_reg_write_target(ah, 0x7890,
+ iowrite32_mac(0x7890,
ioread32_mac(0x7890) & (~0x1800000));
#endif
reset_pll = 1;
a_uint32_t reg, a_uint32_t val)
{
if(reg > 0xffff) {
- HAL_WORD_REG_WRITE(reg, val);
+ iowrite32(reg, val);
#if defined(PROJECT_K2)
if(reg == 0x50040) {
static uint8_t flg=0;
if(reg == 0x7014)
ath_pll_reset_ones(ah);
- ath_hal_reg_write_target(ah, reg, val);
+ iowrite32_mac(reg, val);
}
}