HAL_CAP_RTS_AGGR_LIMIT = 6,
} HAL_CAPABILITY_TYPE;
-typedef enum {
- HAL_M_STA = 1,
- HAL_M_IBSS = 0,
- HAL_M_HOSTAP = 6,
- HAL_M_MONITOR = 8,
-} HAL_OPMODE;
-
typedef enum {
HAL_TX_QUEUE_INACTIVE = 0,
HAL_TX_QUEUE_DATA = 1,
void __ahdecl(*ah_set11nRateScenario)(struct ath_tx_desc *ds,
a_uint32_t durUpdateEn,
a_uint32_t rtsctsRate,
- a_uint32_t rtsctsDuration,
HAL_11N_RATE_SERIES series[],
a_uint32_t nseries, a_uint32_t flags);
- void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *ah,
- struct ath_tx_desc *ds, a_uint32_t aggrLen,
+ void __ahdecl(*ah_set11nAggrFirst)(struct ath_tx_desc *ds, a_uint32_t aggrLen,
a_uint32_t numDelims);
- void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *ah,
- struct ath_tx_desc *ds, a_uint32_t numDelims);
- void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *ah,
- struct ath_tx_desc *ds);
- void __ahdecl(*ah_clr11nAggr)(struct ath_hal *ah,
- struct ath_tx_desc *ds);
- void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *ah,
- struct ath_tx_desc *ds,
+ void __ahdecl(*ah_set11nAggrMiddle)(struct ath_tx_desc *ds, a_uint32_t numDelims);
+ void __ahdecl(*ah_set11nAggrLast)(struct ath_tx_desc *ds);
+ void __ahdecl(*ah_clr11nAggr)(struct ath_tx_desc *ds);
+ void __ahdecl(*ah_set11nBurstDuration)(struct ath_tx_desc *ds,
a_uint32_t burstDuration);
- void __ahdecl(*ah_set11nVirtualMoreFrag)(struct ath_hal *ah,
- struct ath_tx_desc *ds, a_uint32_t vmf);
+ void __ahdecl(*ah_set11nVirtualMoreFrag)(struct ath_tx_desc *ds, a_uint32_t vmf);
HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_tx_desc *,
a_uint32_t pktLen, a_uint32_t hdrLen,