projects
/
open-ath9k-htc-firmware.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
Merge pull request #119 from olerem/rate-2016.12.16.1
[open-ath9k-htc-firmware.git]
/
target_firmware
/
wlan
/
if_owl.c
diff --git
a/target_firmware/wlan/if_owl.c
b/target_firmware/wlan/if_owl.c
index f5ce647f453207eee1a8dc08f717f49f4bc9c517..6dda78cef6b11c340fada4b4b900a118bed2ee50 100755
(executable)
--- a/
target_firmware/wlan/if_owl.c
+++ b/
target_firmware/wlan/if_owl.c
@@
-57,6
+57,7
@@
#include "if_athrate.h"
#include "if_athvar.h"
#include "ah_desc.h"
#include "if_athrate.h"
#include "if_athvar.h"
#include "ah_desc.h"
+#include "ah_internal.h"
#define ath_tgt_free_skb adf_nbuf_free
#define ath_tgt_free_skb adf_nbuf_free
@@
-147,6
+148,8
@@
static void ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
int ath_tgt_tx_add_to_aggr(struct ath_softc_tgt *sc,
struct ath_buf *bf,int datatype,
ath_atx_tid_t *tid, int is_burst);
int ath_tgt_tx_add_to_aggr(struct ath_softc_tgt *sc,
struct ath_buf *bf,int datatype,
ath_atx_tid_t *tid, int is_burst);
+int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
+ ath_tx_bufhead *bf_q);
struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb)
{
struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb)
{
@@
-228,15
+231,14
@@
static void ath_dma_map(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
- adf_nbuf_t skb = bf->bf_skb;
-
- skb = adf_nbuf_queue_first(&bf->bf_skbhead);
+ adf_nbuf_queue_first(&bf->bf_skbhead);
adf_nbuf_unmap( sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
}
static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
struct ath_tx_desc *ds0, *ds = bf->bf_desc;
adf_nbuf_unmap( sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
}
static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
struct ath_tx_desc *ds0, *ds = bf->bf_desc;
+ struct ath_hal *ah = sc->sc_ah;
a_uint8_t i;
ds0 = ds;
a_uint8_t i;
ds0 = ds;
@@
-252,7
+254,7
@@
static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
} else
ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1);
} else
ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1);
- a
th_hal_filltxdesc(sc->sc_ah,
ds
+ a
h->ah_fillTxDesc(
ds
, bf->bf_dmamap_info.dma_segs[i].len
, i == 0
, i == (bf->bf_dmamap_info.nsegs - 1)
, bf->bf_dmamap_info.dma_segs[i].len
, i == 0
, i == (bf->bf_dmamap_info.nsegs - 1)
@@
-263,6
+265,7
@@
static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
struct ath_tx_desc *ds = bf->bf_desc;
static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
struct ath_tx_desc *ds = bf->bf_desc;
+ struct ath_hal *ah = sc->sc_ah;
switch (bf->bf_protmode) {
case IEEE80211_PROT_RTSCTS:
switch (bf->bf_protmode) {
case IEEE80211_PROT_RTSCTS:
@@
-275,7
+278,7
@@
static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
break;
}
break;
}
- a
th_hal_set11n_txdesc(sc->sc_ah,
ds
+ a
h->ah_set11nTxDesc(
ds
, bf->bf_pktlen
, bf->bf_atype
, 60
, bf->bf_pktlen
, bf->bf_atype
, 60
@@
-370,7
+373,6
@@
static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
HAL_11N_RATE_SERIES series[4];
a_int32_t i, flags;
a_uint8_t rix, cix, rtsctsrate;
HAL_11N_RATE_SERIES series[4];
a_int32_t i, flags;
a_uint8_t rix, cix, rtsctsrate;
- a_uint32_t ctsduration = 0;
a_int32_t prot_mode = AH_FALSE;
rt = sc->sc_currates;
a_int32_t prot_mode = AH_FALSE;
rt = sc->sc_currates;
@@
-385,7
+387,7
@@
static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
cix = rt->info[sc->sc_protrix].controlRate;
prot_mode = AH_TRUE;
} else {
cix = rt->info[sc->sc_protrix].controlRate;
prot_mode = AH_TRUE;
} else {
- if (ath_hal_
htsupported(ah
) && (!bf->bf_ismcast))
+ if (ath_hal_
getcapability(ah, HAL_CAP_HT
) && (!bf->bf_ismcast))
flags = HAL_TXDESC_RTSENA;
for (i = 4; i--;) {
flags = HAL_TXDESC_RTSENA;
for (i = 4; i--;) {
@@
-442,8
+444,8
@@
static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
rtsctsrate = rt->info[cix].rateCode |
(bf->bf_shpream ? rt->info[cix].shortPreamble : 0);
rtsctsrate = rt->info[cix].rateCode |
(bf->bf_shpream ? rt->info[cix].shortPreamble : 0);
- a
th_hal_set11n_ratescenario(ah,
ds, 1,
- rtsctsrate,
ctsduration,
+ a
h->ah_set11nRateScenario(
ds, 1,
+ rtsctsrate,
series, 4,
flags);
}
series, 4,
flags);
}
@@
-555,6
+557,8
@@
void ath_tx_status_update(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
if (txs == NULL)
return;
if (txs == NULL)
return;
+ txs->txstatus[txs->cnt].ts_flags = 0;
+
txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
@@
-649,6
+653,7
@@
void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
{
struct ath_tx_buf *bf;
struct ath_tx_desc *ds;
{
struct ath_tx_buf *bf;
struct ath_tx_desc *ds;
+ struct ath_hal *ah = sc->sc_ah;
HAL_STATUS status;
for (;;) {
HAL_STATUS status;
for (;;) {
@@
-661,7
+666,7
@@
void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
bf = asf_tailq_first(&txq->axq_q);
ds = bf->bf_lastds;
bf = asf_tailq_first(&txq->axq_q);
ds = bf->bf_lastds;
- status = a
th_hal_txprocdesc(sc->sc_
ah, ds);
+ status = a
h->ah_procTxDesc(
ah, ds);
if (status == HAL_EINPROGRESS) {
if (txqstate == OWL_TXQ_ACTIVE)
if (status == HAL_EINPROGRESS) {
if (txqstate == OWL_TXQ_ACTIVE)
@@
-877,14
+882,13
@@
static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *b
{
struct ath_hal *ah = sc->sc_ah;
struct ath_txq *txq;
{
struct ath_hal *ah = sc->sc_ah;
struct ath_txq *txq;
- HAL_STATUS status;
volatile a_int32_t txe_val;
adf_os_assert(bf);
txq = bf->bf_txq;
volatile a_int32_t txe_val;
adf_os_assert(bf);
txq = bf->bf_txq;
-
status = ath_hal_txprocdesc(sc->sc_
ah, bf->bf_lastds);
+
ah->ah_procTxDesc(
ah, bf->bf_lastds);
ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
@@
-893,7
+897,7
@@
static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *b
} else {
*txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
} else {
*txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
- txe_val =
OS_REG_READ(ah, 0x
840);
+ txe_val =
ioread32_mac(0x0
840);
if (!(txe_val & (1<< txq->axq_qnum)))
ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
}
if (!(txe_val & (1<< txq->axq_qnum)))
ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
}
@@
-965,9
+969,13
@@
ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
rcs, &isProbe);
ath_hal_memcpy(bf->bf_rcs, rcs, sizeof(rcs));
} else {
rcs, &isProbe);
ath_hal_memcpy(bf->bf_rcs, rcs, sizeof(rcs));
} else {
+ struct ath_vap_target *avp;
+
+ avp = &sc->sc_vap[bf->vap_index];
+
mrcs[1].tries = mrcs[2].tries = mrcs[3].tries = 0;
mrcs[1].rix = mrcs[2].rix = mrcs[3].rix = 0;
mrcs[1].tries = mrcs[2].tries = mrcs[3].tries = 0;
mrcs[1].rix = mrcs[2].rix = mrcs[3].rix = 0;
- mrcs[0].rix
= 0
;
+ mrcs[0].rix
= ath_get_minrateidx(sc, avp)
;
mrcs[0].tries = 1;
mrcs[0].flags = 0;
ath_hal_memcpy(bf->bf_rcs, mrcs, sizeof(mrcs));
mrcs[0].tries = 1;
mrcs[0].flags = 0;
ath_hal_memcpy(bf->bf_rcs, mrcs, sizeof(mrcs));
@@
-982,11
+990,12
@@
ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
a_int32_t i ;
struct ath_tx_desc *bfd = NULL;
{
a_int32_t i ;
struct ath_tx_desc *bfd = NULL;
+ struct ath_hal *ah = sc->sc_ah;
for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) {
for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) {
- a
th_hal_clr11n_aggr(sc->sc_ah,
bfd);
- a
th_hal_set11n_burstduration(sc->sc_ah,
bfd, 0);
- a
th_hal_set11n_virtualmorefrag(sc->sc_ah,
bfd, 0);
+ a
h->ah_clr11nAggr(
bfd);
+ a
h->ah_set11nBurstDuration(
bfd, 0);
+ a
h->ah_set11nVirtualMoreFrag(
bfd, 0);
}
ath_dma_unmap(sc, bf);
}
ath_dma_unmap(sc, bf);
@@
-1018,13
+1027,15
@@
static void
ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
struct ath_tx_desc *ds = bf->bf_desc;
ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
struct ath_tx_desc *ds = bf->bf_desc;
+ struct ieee80211_frame *wh = ATH_SKB2_WH(bf->bf_skb);
u_int32_t sr, lr;
if (ds->ds_txstat.ts_status == 0) {
if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
sc->sc_tx_stats.ast_tx_altrate++;
} else {
u_int32_t sr, lr;
if (ds->ds_txstat.ts_status == 0) {
if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
sc->sc_tx_stats.ast_tx_altrate++;
} else {
- if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
+ if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY &&
+ !IEEE80211_IS_MULTICAST(wh->i_addr1))
sc->sc_tx_stats.ast_tx_xretries++;
if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
sc->sc_tx_stats.ast_tx_fifoerr++;
sc->sc_tx_stats.ast_tx_xretries++;
if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
sc->sc_tx_stats.ast_tx_fifoerr++;
@@
-1048,7
+1059,7
@@
ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
struct ath_vap_target *avp;
struct ath_hal *ah = sc->sc_ah;
a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
struct ath_vap_target *avp;
struct ath_hal *ah = sc->sc_ah;
a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
- a_uint32_t
ivlen = 0, icvlen = 0,
subtype, flags, ctsduration;
+ a_uint32_t subtype, flags, ctsduration;
a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
struct ath_tx_desc *ds=NULL;
struct ath_txq *txq=NULL;
a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
struct ath_tx_desc *ds=NULL;
struct ath_txq *txq=NULL;
@@
-1197,20
+1208,16
@@
ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
flags |= HAL_TXDESC_INTREQ;
flags |= HAL_TXDESC_INTREQ;
- a
th_hal_setuptxdesc(ah,
ds
+ a
h->ah_setupTxDesc(
ds
, pktlen
, hdrlen
, atype
, 60
, txrate, try0
, keyix
, pktlen
, hdrlen
, atype
, 60
, txrate, try0
, keyix
- , 0
, flags
, ctsrate
, flags
, ctsrate
- , ctsduration
- , icvlen
- , ivlen
- , ATH_COMP_PROC_NO_COMP_NO_CCS);
+ , ctsduration);
bf->bf_flags = flags;
bf->bf_flags = flags;
@@
-1219,8
+1226,8
@@
ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
* in Auth frame 3 of Shared Authentication, owl needs this.
*/
if (iswep && (keyix != HAL_TXKEYIX_INVALID) &&
* in Auth frame 3 of Shared Authentication, owl needs this.
*/
if (iswep && (keyix != HAL_TXKEYIX_INVALID) &&
- (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
- a
th_hal_fillkeytxdesc(ah,
ds, mh->keytype);
+
(wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
+ a
h->ah_fillKeyTxDesc(
ds, mh->keytype);
ath_filltxdesc(sc, bf);
ath_filltxdesc(sc, bf);
@@
-1230,7
+1237,7
@@
ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
series[i].RateFlags = 0;
}
series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
series[i].RateFlags = 0;
}
- a
th_hal_set11n_ratescenario(ah, ds, 0, ctsrate, ctsduration
, series, 4, 0);
+ a
h->ah_set11nRateScenario(ds, 0, ctsrate
, series, 4, 0);
ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds);
return;
ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds);
return;
@@
-1378,6
+1385,7
@@
ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
ath_tx_bufhead bf_q;
struct ath_txq *txq = TID_TO_ACTXQ(tid->tidno);
struct ath_tx_desc *ds = NULL;
ath_tx_bufhead bf_q;
struct ath_txq *txq = TID_TO_ACTXQ(tid->tidno);
struct ath_tx_desc *ds = NULL;
+ struct ath_hal *ah = sc->sc_ah;
int i;
int i;
@@
-1408,7
+1416,7
@@
ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
bf->bf_next = NULL;
for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
bf->bf_next = NULL;
for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
- a
th_hal_clr11n_aggr(sc->sc_ah,
ds);
+ a
h->ah_clr11nAggr(
ds);
ath_buf_set_rate(sc, bf);
bf->bf_txq_add(sc, bf);
ath_buf_set_rate(sc, bf);
bf->bf_txq_add(sc, bf);
@@
-1422,12
+1430,12
@@
ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
bf->bf_isaggr = 1;
ath_buf_set_rate(sc, bf);
bf->bf_isaggr = 1;
ath_buf_set_rate(sc, bf);
- a
th_hal_set11n_aggr_first(sc->sc_ah,
bf->bf_desc, bf->bf_al,
+ a
h->ah_set11nAggrFirst(
bf->bf_desc, bf->bf_al,
bf->bf_ndelim);
bf->bf_lastds = bf_last->bf_lastds;
for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++)
bf->bf_ndelim);
bf->bf_lastds = bf_last->bf_lastds;
for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++)
- a
th_hal_set11n_aggr_last(sc->sc_ah,
&bf_last->bf_descarr[i]);
+ a
h->ah_set11nAggrLast(
&bf_last->bf_descarr[i]);
if (status == ATH_AGGR_8K_LIMITED) {
adf_os_assert(0);
if (status == ATH_AGGR_8K_LIMITED) {
adf_os_assert(0);
@@
-1495,6
+1503,7
@@
int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
int nframes = 0, rl = 0;;
struct ath_tx_desc *ds = NULL;
struct ath_tx_buf *bf;
int nframes = 0, rl = 0;;
struct ath_tx_desc *ds = NULL;
struct ath_tx_buf *bf;
+ struct ath_hal *ah = sc->sc_ah;
u_int16_t aggr_limit = (64*1024 -1), al = 0, bpad = 0, al_delta;
u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0;
u_int16_t aggr_limit = (64*1024 -1), al = 0, bpad = 0, al_delta;
u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0;
@@
-1571,7
+1580,7
@@
int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
bf_prev = bf;
for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
bf_prev = bf;
for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
- a
th_hal_set11n_aggr_middle(sc->sc_ah,
ds, bf->bf_ndelim);
+ a
h->ah_set11nAggrMiddle(
ds, bf->bf_ndelim);
} while (!asf_tailq_empty(&tid->buf_q));
} while (!asf_tailq_empty(&tid->buf_q));
@@
-1738,21
+1747,13
@@
ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
struct ath_tx_desc lastds;
struct ath_tx_desc *ds = &lastds;
struct ath_rc_series rcs[4];
struct ath_tx_desc lastds;
struct ath_tx_desc *ds = &lastds;
struct ath_rc_series rcs[4];
- u_int16_t seq_st;
- u_int32_t *ba;
- int ba_index;
int nbad = 0;
int nframes = bf->bf_nframes;
struct ath_tx_buf *bf_next;
int nbad = 0;
int nframes = bf->bf_nframes;
struct ath_tx_buf *bf_next;
- int tx_ok = 1;
adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
- seq_st = ATH_DS_BA_SEQ(ds);
- ba = ATH_DS_BA_BITMAP(ds);
- tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
-
if (!bf->bf_isaggr) {
ath_update_stats(sc, bf);
if (!bf->bf_isaggr) {
ath_update_stats(sc, bf);
@@
-1771,7
+1772,6
@@
ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
}
while (bf) {
}
while (bf) {
- ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
bf_next = bf->bf_next;
ath_tx_status_update_aggr(sc, bf, ds, rcs, 0);
bf_next = bf->bf_next;
ath_tx_status_update_aggr(sc, bf, ds, rcs, 0);
@@
-1800,14
+1800,15
@@
ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
struct ath_tx_desc *ds = NULL;
struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
struct ath_tx_desc *ds = NULL;
+ struct ath_hal *ah = sc->sc_ah;
int i = 0;
__stats(sc, txaggr_compretries);
for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) {
int i = 0;
__stats(sc, txaggr_compretries);
for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) {
- a
th_hal_clr11n_aggr(sc->sc_ah,
ds);
- a
th_hal_set11n_burstduration(sc->sc_ah,
ds, 0);
- a
th_hal_set11n_virtualmorefrag(sc->sc_ah,
ds, 0);
+ a
h->ah_clr11nAggr(
ds);
+ a
h->ah_set11nBurstDuration(
ds, 0);
+ a
h->ah_set11nVirtualMoreFrag(
ds, 0);
}
if (bf->bf_retries >= OWLMAX_RETRIES) {
}
if (bf->bf_retries >= OWLMAX_RETRIES) {
@@
-1957,9
+1958,6
@@
void ath_tgt_tx_cleanup(struct ath_softc_tgt *sc, struct ath_node_target *an,
{
struct ath_tx_buf *bf;
struct ath_tx_buf *bf_next;
{
struct ath_tx_buf *bf;
struct ath_tx_buf *bf_next;
- struct ath_txq *txq;
-
- txq = TID_TO_ACTXQ(tid->tidno);
bf = asf_tailq_first(&tid->buf_q);
bf = asf_tailq_first(&tid->buf_q);
@@
-2056,11
+2054,9
@@
static void ath_bar_tx_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
struct ath_tx_desc *ds = bf->bf_lastds;
struct ath_node_target *an;
ath_atx_tid_t *tid;
struct ath_tx_desc *ds = bf->bf_lastds;
struct ath_node_target *an;
ath_atx_tid_t *tid;
- struct ath_txq *txq;
an = (struct ath_node_target *)bf->bf_node;
tid = &an->tid[bf->bf_tidno];
an = (struct ath_node_target *)bf->bf_node;
tid = &an->tid[bf->bf_tidno];
- txq = TID_TO_ACTXQ(tid->tidno);
if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
ath_bar_retry(sc, bf);
if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
ath_bar_retry(sc, bf);
@@
-2080,9
+2076,9
@@
static void ath_bar_tx(struct ath_softc_tgt *sc,
struct ieee80211_frame_bar *bar;
u_int8_t min_rate;
struct ath_tx_desc *ds, *ds0;
struct ieee80211_frame_bar *bar;
u_int8_t min_rate;
struct ath_tx_desc *ds, *ds0;
+ struct ath_hal *ah = sc->sc_ah;
HAL_11N_RATE_SERIES series[4];
int i = 0;
HAL_11N_RATE_SERIES series[4];
int i = 0;
- adf_nbuf_queue_t skbhead;
a_uint8_t *anbdata;
a_uint32_t anblen;
a_uint8_t *anbdata;
a_uint32_t anblen;
@@
-2121,7
+2117,7
@@
static void ath_bar_tx(struct ath_softc_tgt *sc,
adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
ds = bf->bf_desc;
adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
ds = bf->bf_desc;
- a
th_hal_setuptxdesc(sc->sc_ah,
ds
+ a
h->ah_setupTxDesc(
ds
, adf_nbuf_len(skb) + IEEE80211_CRC_LEN
, 0
, HAL_PKT_TYPE_NORMAL
, adf_nbuf_len(skb) + IEEE80211_CRC_LEN
, 0
, HAL_PKT_TYPE_NORMAL
@@
-2129,18
+2125,15
@@
static void ath_bar_tx(struct ath_softc_tgt *sc,
, min_rate
, ATH_TXMAXTRY
, bf->bf_keyix
, min_rate
, ATH_TXMAXTRY
, bf->bf_keyix
- , 0
, HAL_TXDESC_INTREQ
| HAL_TXDESC_CLRDMASK
, HAL_TXDESC_INTREQ
| HAL_TXDESC_CLRDMASK
- , 0, 0, 0, 0
- , ATH_COMP_PROC_NO_COMP_NO_CCS);
+ , 0, 0);
- skbhead = bf->bf_skbhead;
bf->bf_isaggr = 0;
bf->bf_next = NULL;
for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) {
bf->bf_isaggr = 0;
bf->bf_next = NULL;
for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) {
- a
th_hal_clr11n_aggr(sc->sc_ah,
ds0);
+ a
h->ah_clr11nAggr(
ds0);
}
ath_filltxdesc(sc, bf);
}
ath_filltxdesc(sc, bf);
@@
-2151,6
+2144,6
@@
static void ath_bar_tx(struct ath_softc_tgt *sc,
series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
}
series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
}
- a
th_hal_set11n_ratescenario(sc->sc_ah, bf->bf_desc, 0
, 0, 0, series, 4, 4);
+ a
h->ah_set11nRateScenario(bf->bf_desc
, 0, 0, series, 4, 4);
ath_tgt_txq_add_ucast(sc, bf);
}
ath_tgt_txq_add_ucast(sc, bf);
}