+static void ath_pll_reset_ones(struct ath_hal *ah)
+{
+ static uint8_t reset_pll = 0;
+
+ if(reset_pll == 0) {
+#if defined(PROJECT_K2)
+ /* here we write to core register */
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
+ /* and here to mac register */
+ ath_hal_reg_write_target(ah, 0x786c,
+ ioread32_mac(0x786c) | 0x6000000);
+ ath_hal_reg_write_target(ah, 0x786c,
+ ioread32_mac(0x786c) & (~0x6000000));
+
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
+
+#elif defined(PROJECT_MAGPIE) && !defined (FPGA)
+ ath_hal_reg_write_target(ah, 0x7890,
+ ioread32_mac(0x7890) | 0x1800000);
+ ath_hal_reg_write_target(ah, 0x7890,
+ ioread32_mac(0x7890) & (~0x1800000));
+#endif
+ reset_pll = 1;
+ }
+}
+
+static void ath_hal_reg_write_filter(struct ath_hal *ah,
+ a_uint32_t reg, a_uint32_t val)
+{
+ if(reg > 0xffff) {
+ HAL_WORD_REG_WRITE(reg, val);
+#if defined(PROJECT_K2)
+ if(reg == 0x50040) {
+ static uint8_t flg=0;
+
+ if(flg == 0) {
+ /* reinit clock and uart.
+ * TODO: Independent on what host will
+ * here set. We do our own decision. Why? */
+ A_CLOCK_INIT(117);
+ A_UART_HWINIT(117*1000*1000, 19200);
+ flg = 1;
+ }
+ }
+#endif
+ } else {
+ if(reg == 0x7014)
+ ath_pll_reset_ones(ah);
+
+ ath_hal_reg_write_target(ah, reg, val);
+ }
+}
+