2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <adf_os_types.h>
37 #include <adf_os_dma.h>
38 #include <adf_os_timer.h>
39 #include <adf_os_lock.h>
40 #include <adf_os_io.h>
41 #include <adf_os_mem.h>
42 #include <adf_os_util.h>
43 #include <adf_os_stdtypes.h>
44 #include <adf_os_defer.h>
45 #include <adf_os_atomic.h>
48 #include <adf_net_wcmd.h>
52 #ifdef USE_HEADERLEN_RESV
56 #include <ieee80211_var.h>
57 #include "if_athrate.h"
58 #include "if_athvar.h"
61 #define ath_tgt_free_skb adf_nbuf_free
63 #define OFDM_PLCP_BITS 22
64 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
65 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
71 #define HT_LTF(_ns) (4 * (_ns))
72 #define SYMBOL_TIME(_ns) ((_ns) << 2) // ns * 4 us
73 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) // ns * 3.6 us
75 static a_uint16_t bits_per_symbol[][2] = {
77 { 26, 54 }, // 0: BPSK
78 { 52, 108 }, // 1: QPSK 1/2
79 { 78, 162 }, // 2: QPSK 3/4
80 { 104, 216 }, // 3: 16-QAM 1/2
81 { 156, 324 }, // 4: 16-QAM 3/4
82 { 208, 432 }, // 5: 64-QAM 2/3
83 { 234, 486 }, // 6: 64-QAM 3/4
84 { 260, 540 }, // 7: 64-QAM 5/6
85 { 52, 108 }, // 8: BPSK
86 { 104, 216 }, // 9: QPSK 1/2
87 { 156, 324 }, // 10: QPSK 3/4
88 { 208, 432 }, // 11: 16-QAM 1/2
89 { 312, 648 }, // 12: 16-QAM 3/4
90 { 416, 864 }, // 13: 64-QAM 2/3
91 { 468, 972 }, // 14: 64-QAM 3/4
92 { 520, 1080 }, // 15: 64-QAM 5/6
95 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
96 owl_txq_state_t txqstate);
97 static void ath_tgt_txqaddbuf(struct ath_softc_tgt *sc, struct ath_txq *txq,
98 struct ath_tx_buf *bf, struct ath_tx_desc *lastds);
99 void ath_rate_findrate_11n_Hardcoded(struct ath_softc_tgt *sc,
100 struct ath_rc_series series[]);
101 void ath_buf_set_rate_Hardcoded(struct ath_softc_tgt *sc,
102 struct ath_tx_buf *bf) ;
103 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
104 struct ath_tx_buf *bf, ath_data_hdr_t *dh);
105 static void ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
106 static void ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
107 static void ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
108 void adf_print_buf(adf_nbuf_t buf);
109 static void ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid);
111 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
112 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb);
114 void ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
116 static void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
117 static void ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
119 extern a_int32_t ath_chainmask_sel_logic(void *);
120 static a_int32_t ath_get_pktlen(struct ath_tx_buf *bf, a_int32_t hdrlen);
121 static void ath_tgt_txq_schedule(struct ath_softc_tgt *sc, struct ath_txq *txq);
123 typedef void (*ath_ft_set_atype_t)(struct ath_softc_tgt *sc, struct ath_buf *bf);
126 ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
129 ath_bar_tx(struct ath_softc_tgt *sc, ath_atx_tid_t *tid, struct ath_tx_buf *bf);
131 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno);
133 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
134 ath_tx_bufhead *bf_q, struct ath_tx_buf **bar);
137 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_atx_tid_t *tid);
139 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf);
140 static inline void ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
141 static void ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
142 static void ath_update_aggr_stats(struct ath_softc_tgt *sc, struct ath_tx_desc *ds,
143 int nframes, int nbad);
144 static inline void ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
145 static void ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
147 int ath_tgt_tx_add_to_aggr(struct ath_softc_tgt *sc,
148 struct ath_buf *bf,int datatype,
149 ath_atx_tid_t *tid, int is_burst);
151 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb)
156 adf_nbuf_peek_header(skb, &anbdata, &anblen);
158 return((struct ieee80211_frame *)anbdata);
161 #undef adf_os_cpu_to_le16
163 static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
165 return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
169 ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
173 txq = TID_TO_ACTXQ(tid->tidno);
176 if (asf_tailq_empty(&tid->buf_q))
179 ath_tgt_tx_enqueue(txq, tid);
180 ath_tgt_txq_schedule(sc, txq);
184 ath_aggr_pause_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
189 static a_uint32_t ath_pkt_duration(struct ath_softc_tgt *sc,
190 a_uint8_t rix, struct ath_tx_buf *bf,
191 a_int32_t width, a_int32_t half_gi)
193 const HAL_RATE_TABLE *rt = sc->sc_currates;
194 a_uint32_t nbits, nsymbits, duration, nsymbols;
199 pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_pktlen;
200 rc = rt->info[rix].rateCode;
203 return ath_hal_computetxtime(sc->sc_ah, rt, pktlen, rix,
206 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
207 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
208 nsymbols = (nbits + nsymbits - 1) / nsymbits;
211 duration = SYMBOL_TIME(nsymbols);
213 duration = SYMBOL_TIME_HALFGI(nsymbols);
215 streams = HT_RC_2_STREAMS(rc);
216 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
221 static void ath_dma_map(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
223 adf_nbuf_t skb = bf->bf_skb;
225 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
226 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
229 static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
231 adf_nbuf_t skb = bf->bf_skb;
233 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
234 adf_nbuf_unmap( sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
237 static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
239 struct ath_tx_desc *ds0, *ds = bf->bf_desc;
240 struct ath_hal *ah = sc->sc_ah;
244 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
246 for (i = 0; i < bf->bf_dmamap_info.nsegs; i++, ds++) {
248 ds->ds_data = bf->bf_dmamap_info.dma_segs[i].paddr;
250 if (i == (bf->bf_dmamap_info.nsegs - 1)) {
254 ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1);
257 , bf->bf_dmamap_info.dma_segs[i].len
259 , i == (bf->bf_dmamap_info.nsegs - 1)
264 static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
266 struct ath_tx_desc *ds = bf->bf_desc;
267 struct ath_hal *ah = sc->sc_ah;
269 switch (bf->bf_protmode) {
270 case IEEE80211_PROT_RTSCTS:
271 bf->bf_flags |= HAL_TXDESC_RTSENA;
273 case IEEE80211_PROT_CTSONLY:
274 bf->bf_flags |= HAL_TXDESC_CTSENA;
280 ah->ah_set11nTxDesc(ds
286 , bf->bf_flags | HAL_TXDESC_INTREQ);
288 ath_filltxdesc(sc, bf);
291 static struct ath_tx_buf *ath_buf_toggle(struct ath_softc_tgt *sc,
292 struct ath_tx_buf *bf,
295 struct ath_tx_buf *tmp = NULL;
296 adf_nbuf_t buf = NULL;
298 adf_os_assert(sc->sc_txbuf_held != NULL);
300 tmp = sc->sc_txbuf_held;
303 ath_dma_unmap(sc, bf);
304 adf_nbuf_queue_init(&tmp->bf_skbhead);
305 buf = adf_nbuf_queue_remove(&bf->bf_skbhead);
307 adf_nbuf_queue_add(&tmp->bf_skbhead, buf);
309 adf_os_assert(adf_nbuf_queue_len(&bf->bf_skbhead) == 0);
311 tmp->bf_next = bf->bf_next;
312 tmp->bf_endpt = bf->bf_endpt;
313 tmp->bf_tidno = bf->bf_tidno;
314 tmp->bf_skb = bf->bf_skb;
315 tmp->bf_node = bf->bf_node;
316 tmp->bf_isaggr = bf->bf_isaggr;
317 tmp->bf_flags = bf->bf_flags;
318 tmp->bf_state = bf->bf_state;
319 tmp->bf_retries = bf->bf_retries;
320 tmp->bf_comp = bf->bf_comp;
321 tmp->bf_nframes = bf->bf_nframes;
322 tmp->bf_cookie = bf->bf_cookie;
334 ath_dma_map(sc, tmp);
335 ath_tx_tgt_setds(sc, tmp);
338 sc->sc_txbuf_held = bf;
343 static void ath_tgt_skb_free(struct ath_softc_tgt *sc,
344 adf_nbuf_queue_t *head,
345 HTC_ENDPOINT_ID endpt)
349 while (adf_nbuf_queue_len(head) != 0) {
350 tskb = adf_nbuf_queue_remove(head);
351 ath_free_tx_skb(sc->tgt_htc_handle,endpt,tskb);
355 static void ath_buf_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
357 ath_dma_unmap(sc, bf);
358 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
361 bf = ath_buf_toggle(sc, bf, 0);
363 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
367 static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
369 struct ath_hal *ah = sc->sc_ah;
370 const HAL_RATE_TABLE *rt;
371 struct ath_tx_desc *ds = bf->bf_desc;
372 HAL_11N_RATE_SERIES series[4];
374 a_uint8_t rix, cix, rtsctsrate;
375 a_int32_t prot_mode = AH_FALSE;
377 rt = sc->sc_currates;
378 rix = bf->bf_rcs[0].rix;
379 flags = (bf->bf_flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA));
380 cix = rt->info[sc->sc_protrix].controlRate;
382 if (bf->bf_protmode != IEEE80211_PROT_NONE &&
383 (rt->info[rix].phy == IEEE80211_T_OFDM ||
384 rt->info[rix].phy == IEEE80211_T_HT) &&
385 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
386 cix = rt->info[sc->sc_protrix].controlRate;
389 if (ath_hal_getcapability(ah, HAL_CAP_HT) && (!bf->bf_ismcast))
390 flags = HAL_TXDESC_RTSENA;
393 if (bf->bf_rcs[i].tries) {
394 cix = rt->info[bf->bf_rcs[i].rix].controlRate;
401 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES) * 4);
403 for (i = 0; i < 4; i++) {
404 if (!bf->bf_rcs[i].tries)
407 rix = bf->bf_rcs[i].rix;
409 series[i].Rate = rt->info[rix].rateCode |
410 (bf->bf_shpream ? rt->info[rix].shortPreamble : 0);
412 series[i].Tries = bf->bf_rcs[i].tries;
414 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
415 HAL_RATESERIES_RTS_CTS : 0 ) |
416 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
417 HAL_RATESERIES_2040 : 0 ) |
418 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
419 HAL_RATESERIES_HALFGI : 0 ) |
420 ((bf->bf_rcs[i].flags & ATH_RC_TX_STBC_FLAG) ?
421 HAL_RATESERIES_STBC: 0);
423 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
424 HAL_RATESERIES_RTS_CTS : 0 ) |
425 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
426 HAL_RATESERIES_2040 : 0 ) |
427 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
428 HAL_RATESERIES_HALFGI : 0 );
430 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
431 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
432 (bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG));
434 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
437 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
439 if (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG)
440 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
443 rtsctsrate = rt->info[cix].rateCode |
444 (bf->bf_shpream ? rt->info[cix].shortPreamble : 0);
446 ah->ah_set11nRateScenario(ds, 1,
452 static void ath_tgt_rate_findrate(struct ath_softc_tgt *sc,
453 struct ath_node_target *an,
454 a_int32_t shortPreamble,
460 struct ath_rc_series series[],
463 ath_rate_findrate(sc, an, 1, frameLen, 10, 4, 1,
464 ATH_RC_PROBE_ALLOWED, series, isProbe);
467 static void owl_tgt_tid_init(struct ath_atx_tid *tid)
471 tid->seq_start = tid->seq_next = 0;
472 tid->baw_size = WME_MAX_BA;
473 tid->baw_head = tid->baw_tail = 0;
476 tid->sched = AH_FALSE;
478 asf_tailq_init(&tid->buf_q);
480 for (i = 0; i < ATH_TID_MAX_BUFS; i++) {
481 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, i);
485 static void owl_tgt_tid_cleanup(struct ath_softc_tgt *sc,
486 struct ath_atx_tid *tid)
493 tid->flag &= ~TID_CLEANUP_INPROGRES;
495 if (tid->flag & TID_REINITIALIZE) {
496 adf_os_print("TID REINIT DONE for tid %p\n", tid);
497 tid->flag &= ~TID_REINITIALIZE;
498 owl_tgt_tid_init(tid);
500 ath_aggr_resume_tid(sc, tid);
504 void owl_tgt_node_init(struct ath_node_target * an)
506 struct ath_atx_tid *tid;
509 for (tidno = 0, tid = &an->tid[tidno]; tidno < WME_NUM_TID;tidno++, tid++) {
513 if ( tid->flag & TID_CLEANUP_INPROGRES ) {
514 tid->flag |= TID_REINITIALIZE;
515 adf_os_print("tid[%p]->incomp is not 0: %d\n",
518 owl_tgt_tid_init(tid);
523 void ath_tx_status_clear(struct ath_softc_tgt *sc)
527 for (i = 0; i < 2; i++) {
528 sc->tx_status[i].cnt = 0;
532 static WMI_TXSTATUS_EVENT *ath_tx_status_get(struct ath_softc_tgt *sc)
534 WMI_TXSTATUS_EVENT *txs = NULL;
537 for (i = 0; i < 2; i++) {
538 if (sc->tx_status[i].cnt < HTC_MAX_TX_STATUS) {
539 txs = &sc->tx_status[i];
547 void ath_tx_status_update(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
549 struct ath_tx_desc *ds = bf->bf_lastds;
550 WMI_TXSTATUS_EVENT *txs;
552 if (sc->sc_tx_draining)
555 txs = ath_tx_status_get(sc);
559 txs->txstatus[txs->cnt].ts_flags = 0;
561 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
562 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
564 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
565 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_FILT;
567 if (!(ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) &&
568 !(ds->ds_txstat.ts_status & HAL_TXERR_FIFO) &&
569 !(ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED) &&
570 !(ds->ds_txstat.ts_status & HAL_TXERR_FILT))
571 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
573 ath_tx_status_update_rate(sc, bf->bf_rcs, ds->ds_txstat.ts_rate, txs);
578 void ath_tx_status_update_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
579 struct ath_tx_desc *ds, struct ath_rc_series rcs[],
582 WMI_TXSTATUS_EVENT *txs;
584 if (sc->sc_tx_draining)
587 txs = ath_tx_status_get(sc);
591 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
592 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
595 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
598 ath_tx_status_update_rate(sc, rcs, ds->ds_txstat.ts_rate, txs);
603 void ath_tx_status_send(struct ath_softc_tgt *sc)
607 if (sc->sc_tx_draining)
610 for (i = 0; i < 2; i++) {
611 if (sc->tx_status[i].cnt) {
612 wmi_event(sc->tgt_wmi_handle, WMI_TXSTATUS_EVENTID,
613 &sc->tx_status[i], sizeof(WMI_TXSTATUS_EVENT));
614 /* FIXME: Handle failures. */
615 sc->tx_status[i].cnt = 0;
620 static void owltgt_tx_process_cabq(struct ath_softc_tgt *sc, struct ath_txq *txq)
622 struct ath_hal *ah = sc->sc_ah;
623 ah->ah_setInterrupts(ah, sc->sc_imask & ~HAL_INT_SWBA);
624 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
625 ah->ah_setInterrupts(ah, sc->sc_imask);
628 void owl_tgt_tx_tasklet(TQUEUE_ARG data)
630 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
634 ath_tx_status_clear(sc);
636 for (i = 0; i < (HAL_NUM_TX_QUEUES - 6); i++) {
637 txq = ATH_TXQ(sc, i);
639 if (ATH_TXQ_SETUP(sc, i)) {
640 if (txq == sc->sc_cabq)
641 owltgt_tx_process_cabq(sc, txq);
643 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
647 ath_tx_status_send(sc);
650 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
651 owl_txq_state_t txqstate)
653 struct ath_tx_buf *bf;
654 struct ath_tx_desc *ds;
655 struct ath_hal *ah = sc->sc_ah;
659 if (asf_tailq_empty(&txq->axq_q)) {
660 txq->axq_link = NULL;
661 txq->axq_linkbuf = NULL;
665 bf = asf_tailq_first(&txq->axq_q);
668 status = ah->ah_procTxDesc(ah, ds);
670 if (status == HAL_EINPROGRESS) {
671 if (txqstate == OWL_TXQ_ACTIVE)
673 else if (txqstate == OWL_TXQ_STOPPED) {
674 __stats(sc, tx_stopfiltered);
675 ds->ds_txstat.ts_flags = 0;
676 ds->ds_txstat.ts_status = HAL_OK;
678 ds->ds_txstat.ts_flags = HAL_TX_SW_FILTERED;
682 ATH_TXQ_REMOVE_HEAD(txq, bf, bf_list);
683 if ((asf_tailq_empty(&txq->axq_q))) {
684 __stats(sc, tx_qnull);
685 txq->axq_link = NULL;
686 txq->axq_linkbuf = NULL;
692 ath_tx_status_update(sc, bf);
693 ath_buf_comp(sc, bf);
696 if (txqstate == OWL_TXQ_ACTIVE) {
697 ath_tgt_txq_schedule(sc, txq);
702 static struct ieee80211_frame* ATH_SKB2_WH(adf_nbuf_t skb)
707 adf_nbuf_peek_header(skb, &anbdata, &anblen);
708 return((struct ieee80211_frame *)anbdata);
712 ath_tgt_tid_drain(struct ath_softc_tgt *sc, struct ath_atx_tid *tid)
714 struct ath_tx_buf *bf;
716 while (!asf_tailq_empty(&tid->buf_q)) {
717 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
718 ath_tx_freebuf(sc, bf);
721 tid->seq_next = tid->seq_start;
722 tid->baw_tail = tid->baw_head;
725 static void ath_tgt_tx_comp_normal(struct ath_softc_tgt *sc,
726 struct ath_tx_buf *bf)
728 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
729 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
731 if (tid->flag & TID_CLEANUP_INPROGRES) {
732 owl_tgt_tid_cleanup(sc, tid);
736 ath_tx_uc_comp(sc, bf);
739 ath_tx_freebuf(sc, bf);
742 static struct ieee80211_node_target * ath_tgt_find_node(struct ath_softc_tgt *sc,
743 a_int32_t node_index)
745 struct ath_node_target *an;
746 struct ieee80211_node_target *ni;
748 if (node_index > TARGET_NODE_MAX)
751 an = &sc->sc_sta[node_index];
755 if (ni->ni_vap == NULL) {
764 static struct ath_tx_buf* ath_tx_buf_alloc(struct ath_softc_tgt *sc)
766 struct ath_tx_buf *bf = NULL;
768 bf = asf_tailq_first(&sc->sc_txbuf);
770 adf_os_mem_set(&bf->bf_state, 0, sizeof(struct ath_buf_state));
771 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
779 struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc,
780 adf_nbuf_t skb, ath_data_hdr_t *dh)
782 struct ath_tx_buf *bf;
783 struct ieee80211_node_target *ni;
784 struct ath_atx_tid *tid;
786 ni = ath_tgt_find_node(sc, dh->ni_index);
790 tid = ATH_AN_2_TID(ATH_NODE_TARGET(ni), dh->tidno);
791 if (tid->flag & TID_REINITIALIZE) {
792 adf_os_print("drop frame due to TID reinit\n");
796 bf = ath_tx_buf_alloc(sc);
798 __stats(sc, tx_nobufs);
802 bf->bf_tidno = dh->tidno;
803 bf->bf_txq = TID_TO_ACTXQ(bf->bf_tidno);
804 bf->bf_keytype = dh->keytype;
805 bf->bf_keyix = dh->keyix;
806 bf->bf_protmode = dh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
809 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
810 skb = adf_nbuf_queue_first(&(bf->bf_skbhead));
812 if (adf_nbuf_queue_len(&(bf->bf_skbhead)) == 0) {
813 __stats(sc, tx_noskbs);
821 ath_tgt_txbuf_setup(sc, bf, dh);
823 ath_tx_tgt_setds(sc, bf);
828 static void ath_tgt_tx_seqno_normal(struct ath_tx_buf *bf)
830 struct ieee80211_node_target *ni = bf->bf_node;
831 struct ath_node_target *an = ATH_NODE_TARGET(ni);
832 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
833 struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno);
835 u_int8_t fragno = (wh->i_seq[0] & 0xf);
837 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
839 bf->bf_seqno = (tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
841 *(u_int16_t *)wh->i_seq = adf_os_cpu_to_le16(bf->bf_seqno);
842 wh->i_seq[0] |= fragno;
844 if (!(wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG))
845 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
848 static a_int32_t ath_key_setup(struct ieee80211_node_target *ni,
849 struct ath_tx_buf *bf)
851 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
853 if (!(wh->i_fc[1] & IEEE80211_FC1_WEP)) {
854 bf->bf_keytype = HAL_KEY_TYPE_CLEAR;
855 bf->bf_keyix = HAL_TXKEYIX_INVALID;
859 switch (bf->bf_keytype) {
860 case HAL_KEY_TYPE_WEP:
861 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
863 case HAL_KEY_TYPE_AES:
864 bf->bf_pktlen += IEEE80211_WEP_MICLEN;
866 case HAL_KEY_TYPE_TKIP:
867 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
873 if (bf->bf_keytype == HAL_KEY_TYPE_AES ||
874 bf->bf_keytype == HAL_KEY_TYPE_TKIP)
875 ieee80211_tgt_crypto_encap(wh, ni, bf->bf_keytype);
880 static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
882 struct ath_hal *ah = sc->sc_ah;
885 volatile a_int32_t txe_val;
891 status = ah->ah_procTxDesc(ah, bf->bf_lastds);
893 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
895 if (txq->axq_link == NULL) {
896 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
898 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
900 txe_val = ioread32_mac(0x0840);
901 if (!(txe_val & (1<< txq->axq_qnum)))
902 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
905 txq->axq_link = &bf->bf_lastds->ds_link;
906 ah->ah_startTxDma(ah, txq->axq_qnum);
909 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
910 struct ath_tx_buf *bf,
914 struct ieee80211_frame *wh = ATH_SKB2_WH(bf->bf_skb);
916 a_uint32_t flags = adf_os_ntohl(dh->flags);
918 ath_tgt_tx_seqno_normal(bf);
920 bf->bf_txq_add = ath_tgt_txq_add_ucast;
921 bf->bf_hdrlen = ieee80211_anyhdrsize(wh);
922 bf->bf_pktlen = ath_get_pktlen(bf, bf->bf_hdrlen);
923 bf->bf_ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
925 if ((retval = ath_key_setup(bf->bf_node, bf)) < 0)
928 if (flags & ATH_SHORT_PREAMBLE)
929 bf->bf_shpream = AH_TRUE;
931 bf->bf_shpream = AH_FALSE;
933 bf->bf_flags = HAL_TXDESC_CLRDMASK;
934 bf->bf_atype = HAL_PKT_TYPE_NORMAL;
940 ath_get_pktlen(struct ath_tx_buf *bf, a_int32_t hdrlen)
942 adf_nbuf_t skb = bf->bf_skb;
945 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
946 pktlen = adf_nbuf_len(skb);
948 pktlen -= (hdrlen & 3);
949 pktlen += IEEE80211_CRC_LEN;
955 ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
957 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
958 struct ath_rc_series rcs[4];
959 struct ath_rc_series mrcs[4];
960 a_int32_t shortPreamble = 0;
961 a_int32_t isProbe = 0;
963 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4 );
964 adf_os_mem_set(mrcs, 0, sizeof(struct ath_rc_series)*4 );
966 if (!bf->bf_ismcast) {
967 ath_tgt_rate_findrate(sc, an, shortPreamble,
970 ath_hal_memcpy(bf->bf_rcs, rcs, sizeof(rcs));
972 mrcs[1].tries = mrcs[2].tries = mrcs[3].tries = 0;
973 mrcs[1].rix = mrcs[2].rix = mrcs[3].rix = 0;
977 ath_hal_memcpy(bf->bf_rcs, mrcs, sizeof(mrcs));
980 ath_buf_set_rate(sc, bf);
981 bf->bf_txq_add(sc, bf);
985 ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
988 struct ath_tx_desc *bfd = NULL;
989 struct ath_hal *ah = sc->sc_ah;
991 for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) {
992 ah->ah_clr11nAggr(bfd);
993 ah->ah_set11nBurstDuration(bfd, 0);
994 ah->ah_set11nVirtualMoreFrag(bfd, 0);
997 ath_dma_unmap(sc, bf);
999 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
1005 bf = ath_buf_toggle(sc, bf, 0);
1007 bf->bf_isretried = 0;
1010 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
1014 ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1016 ath_tx_status_update(sc, bf);
1017 ath_update_stats(sc, bf);
1018 ath_rate_tx_complete(sc, ATH_NODE_TARGET(bf->bf_node),
1019 bf->bf_lastds, bf->bf_rcs, 1, 0);
1023 ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1025 struct ath_tx_desc *ds = bf->bf_desc;
1028 if (ds->ds_txstat.ts_status == 0) {
1029 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
1030 sc->sc_tx_stats.ast_tx_altrate++;
1032 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
1033 sc->sc_tx_stats.ast_tx_xretries++;
1034 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
1035 sc->sc_tx_stats.ast_tx_fifoerr++;
1036 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
1037 sc->sc_tx_stats.ast_tx_filtered++;
1038 if (ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED)
1039 sc->sc_tx_stats.ast_tx_timer_exp++;
1041 sr = ds->ds_txstat.ts_shortretry;
1042 lr = ds->ds_txstat.ts_longretry;
1043 sc->sc_tx_stats.ast_tx_shortretry += sr;
1044 sc->sc_tx_stats.ast_tx_longretry += lr;
1048 ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
1049 HTC_ENDPOINT_ID endpt)
1051 struct ieee80211_node_target *ni;
1052 struct ieee80211vap_target *vap;
1053 struct ath_vap_target *avp;
1054 struct ath_hal *ah = sc->sc_ah;
1055 a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
1056 a_uint32_t subtype, flags, ctsduration;
1057 a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
1058 struct ath_tx_desc *ds=NULL;
1059 struct ath_txq *txq=NULL;
1060 struct ath_tx_buf *bf;
1062 const HAL_RATE_TABLE *rt;
1063 HAL_BOOL shortPreamble;
1064 struct ieee80211_frame *wh;
1065 struct ath_rc_series rcs[4];
1066 HAL_11N_RATE_SERIES series[4];
1071 adf_nbuf_peek_header(skb, &data, &len);
1072 adf_nbuf_pull_head(skb, sizeof(ath_mgt_hdr_t));
1074 adf_nbuf_peek_header(hdr_buf, &data, &len);
1077 adf_os_assert(len >= sizeof(ath_mgt_hdr_t));
1079 mh = (ath_mgt_hdr_t *)data;
1080 adf_nbuf_peek_header(skb, &data, &len);
1081 wh = (struct ieee80211_frame *)data;
1083 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4);
1084 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES)*4);
1086 bf = asf_tailq_first(&sc->sc_txbuf);
1090 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
1092 ni = ath_tgt_find_node(sc, mh->ni_index);
1096 bf->bf_endpt = endpt;
1097 bf->bf_cookie = mh->cookie;
1098 bf->bf_protmode = mh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
1099 txq = &sc->sc_txq[1];
1100 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
1101 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1102 hdrlen = ieee80211_anyhdrsize(wh);
1104 keyix = HAL_TXKEYIX_INVALID;
1105 pktlen -= (hdrlen & 3);
1106 pktlen += IEEE80211_CRC_LEN;
1111 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
1114 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
1117 rt = sc->sc_currates;
1118 adf_os_assert(rt != NULL);
1120 if (mh->flags == ATH_SHORT_PREAMBLE)
1121 shortPreamble = AH_TRUE;
1123 shortPreamble = AH_FALSE;
1125 flags = HAL_TXDESC_CLRDMASK;
1127 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1128 case IEEE80211_FC0_TYPE_MGT:
1129 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1131 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1132 atype = HAL_PKT_TYPE_PROBE_RESP;
1133 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
1134 atype = HAL_PKT_TYPE_ATIM;
1136 atype = HAL_PKT_TYPE_NORMAL;
1140 atype = HAL_PKT_TYPE_NORMAL;
1144 avp = &sc->sc_vap[mh->vap_index];
1146 rcs[0].rix = ath_get_minrateidx(sc, avp);
1147 rcs[0].tries = ATH_TXMAXTRY;
1150 adf_os_mem_copy(bf->bf_rcs, rcs, sizeof(rcs));
1152 try0 = rcs[0].tries;
1153 txrate = rt->info[rix].rateCode;
1156 txrate |= rt->info[rix].shortPreamble;
1163 flags |= HAL_TXDESC_NOACK;
1165 } else if (pktlen > vap->iv_rtsthreshold) {
1166 flags |= HAL_TXDESC_RTSENA;
1167 cix = rt->info[rix].controlRate;
1170 if ((bf->bf_protmode != IEEE80211_PROT_NONE) &&
1171 rt->info[rix].phy == IEEE80211_T_OFDM &&
1172 (flags & HAL_TXDESC_NOACK) == 0) {
1173 cix = rt->info[sc->sc_protrix].controlRate;
1174 sc->sc_tx_stats.ast_tx_protect++;
1177 *(a_uint16_t *)&wh->i_seq[0] = adf_os_cpu_to_le16(ni->ni_txseqmgmt <<
1178 IEEE80211_SEQ_SEQ_SHIFT);
1179 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
1182 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
1183 adf_os_assert(cix != 0xff);
1184 ctsrate = rt->info[cix].rateCode;
1185 if (shortPreamble) {
1186 ctsrate |= rt->info[cix].shortPreamble;
1187 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1188 ctsduration += rt->info[cix].spAckDuration;
1189 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1190 ctsduration += rt->info[cix].spAckDuration;
1192 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1193 ctsduration += rt->info[cix].lpAckDuration;
1194 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1195 ctsduration += rt->info[cix].lpAckDuration;
1197 ctsduration += ath_hal_computetxtime(ah,
1198 rt, pktlen, rix, shortPreamble);
1203 flags |= HAL_TXDESC_INTREQ;
1205 ah->ah_setupTxDesc(ds
1216 bf->bf_flags = flags;
1219 * Set key type in tx desc while sending the encrypted challenge to AP
1220 * in Auth frame 3 of Shared Authentication, owl needs this.
1222 if (iswep && (keyix != HAL_TXKEYIX_INVALID) &&
1223 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
1224 ah->ah_fillKeyTxDesc(ds, mh->keytype);
1226 ath_filltxdesc(sc, bf);
1228 for (i=0; i<4; i++) {
1229 series[i].Tries = 2;
1230 series[i].Rate = txrate;
1231 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
1232 series[i].RateFlags = 0;
1234 ah->ah_set11nRateScenario(ds, 0, ctsrate, series, 4, 0);
1235 ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds);
1239 HTC_ReturnBuffers(sc->tgt_htc_handle, endpt, skb);
1244 ath_tgt_txqaddbuf(struct ath_softc_tgt *sc,
1245 struct ath_txq *txq, struct ath_tx_buf *bf,
1246 struct ath_tx_desc *lastds)
1248 struct ath_hal *ah = sc->sc_ah;
1250 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
1252 if (txq->axq_link == NULL) {
1253 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
1255 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1258 txq->axq_link = &lastds->ds_link;
1259 ah->ah_startTxDma(ah, txq->axq_qnum);
1262 void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1265 struct ath_node_target *an;
1267 an = (struct ath_node_target *)bf->bf_node;
1270 tid = &an->tid[bf->bf_tidno];
1273 bf->bf_comp = ath_tgt_tx_comp_normal;
1274 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1275 ath_tgt_tx_send_normal(sc, bf);
1279 ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid)
1287 tid->sched = AH_TRUE;
1288 asf_tailq_insert_tail(&txq->axq_tidq, tid, tid_qelem);
1292 ath_tgt_txq_schedule(struct ath_softc_tgt *sc, struct ath_txq *txq)
1294 struct ath_atx_tid *tid;
1300 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
1305 tid->sched = AH_FALSE;
1310 if (!(tid->flag & TID_AGGR_ENABLED))
1311 ath_tgt_tx_sched_normal(sc,tid);
1313 ath_tgt_tx_sched_aggr(sc,tid);
1317 if (!asf_tailq_empty(&tid->buf_q)) {
1318 ath_tgt_tx_enqueue(txq, tid);
1321 } while (!asf_tailq_empty(&txq->axq_tidq) && !bdone);
1325 ath_tgt_handle_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1328 struct ath_node_target *an;
1329 struct ath_txq *txq = bf->bf_txq;
1330 a_bool_t queue_frame, within_baw;
1332 an = (struct ath_node_target *)bf->bf_node;
1335 tid = &an->tid[bf->bf_tidno];
1338 bf->bf_comp = ath_tgt_tx_comp_aggr;
1340 within_baw = BAW_WITHIN(tid->seq_start, tid->baw_size,
1341 SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1343 queue_frame = ( (txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) ||
1344 (!asf_tailq_empty(&tid->buf_q)) ||
1345 (tid->paused) || (!within_baw) );
1348 asf_tailq_insert_tail(&tid->buf_q, bf, bf_list);
1349 ath_tgt_tx_enqueue(txq, tid);
1351 ath_tx_addto_baw(tid, bf);
1352 __stats(sc, txaggr_nframes);
1353 ath_tgt_tx_send_normal(sc, bf);
1358 ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1360 struct ath_tx_buf *bf;
1361 struct ath_txq *txq =TID_TO_ACTXQ(tid->tidno);;
1364 if (asf_tailq_empty(&tid->buf_q))
1367 bf = asf_tailq_first(&tid->buf_q);
1368 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1369 ath_tgt_tx_send_normal(sc, bf);
1371 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH);
1375 ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1377 struct ath_tx_buf *bf, *bf_last;
1378 ATH_AGGR_STATUS status;
1379 ath_tx_bufhead bf_q;
1380 struct ath_txq *txq = TID_TO_ACTXQ(tid->tidno);
1381 struct ath_tx_desc *ds = NULL;
1382 struct ath_hal *ah = sc->sc_ah;
1386 if (asf_tailq_empty(&tid->buf_q))
1390 if (asf_tailq_empty(&tid->buf_q))
1393 asf_tailq_init(&bf_q);
1395 status = ath_tgt_tx_form_aggr(sc, tid, &bf_q);
1397 if (asf_tailq_empty(&bf_q))
1400 bf = asf_tailq_first(&bf_q);
1401 bf_last = asf_tailq_last(&bf_q, ath_tx_bufhead_s);
1403 if (bf->bf_nframes == 1) {
1405 if(bf->bf_retries == 0)
1406 __stats(sc, txaggr_single);
1408 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs -1]);
1409 bf->bf_lastds->ds_link = 0;
1412 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1413 ah->ah_clr11nAggr(ds);
1415 ath_buf_set_rate(sc, bf);
1416 bf->bf_txq_add(sc, bf);
1421 bf_last->bf_next = NULL;
1422 bf_last->bf_lastds->ds_link = 0;
1423 bf_last->bf_ndelim = 0;
1426 ath_buf_set_rate(sc, bf);
1427 ah->ah_set11nAggrFirst(bf->bf_desc, bf->bf_al,
1429 bf->bf_lastds = bf_last->bf_lastds;
1431 for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++)
1432 ah->ah_set11nAggrLast(&bf_last->bf_descarr[i]);
1434 if (status == ATH_AGGR_8K_LIMITED) {
1439 bf->bf_txq_add(sc, bf);
1440 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1441 status != ATH_TGT_AGGR_BAW_CLOSED);
1444 static u_int32_t ath_lookup_rate(struct ath_softc_tgt *sc,
1445 struct ath_node_target *an,
1446 struct ath_tx_buf *bf)
1449 u_int32_t max4msframelen, frame_length;
1450 u_int16_t aggr_limit, legacy=0;
1451 const HAL_RATE_TABLE *rt = sc->sc_currates;
1452 struct ieee80211_node_target *ieee_node = (struct ieee80211_node_target *)an;
1454 if (bf->bf_ismcast) {
1455 bf->bf_rcs[1].tries = bf->bf_rcs[2].tries = bf->bf_rcs[3].tries = 0;
1456 bf->bf_rcs[0].rix = 0xb;
1457 bf->bf_rcs[0].tries = ATH_TXMAXTRY - 1;
1458 bf->bf_rcs[0].flags = 0;
1460 ath_tgt_rate_findrate(sc, an, AH_TRUE, 0, ATH_TXMAXTRY-1, 4, 1,
1461 ATH_RC_PROBE_ALLOWED, bf->bf_rcs, &prate);
1464 max4msframelen = IEEE80211_AMPDU_LIMIT_MAX;
1466 for (i = 0; i < 4; i++) {
1467 if (bf->bf_rcs[i].tries) {
1468 frame_length = bf->bf_rcs[i].max4msframelen;
1470 if (rt->info[bf->bf_rcs[i].rix].phy != IEEE80211_T_HT) {
1475 max4msframelen = ATH_MIN(max4msframelen, frame_length);
1479 if (prate || legacy)
1482 if (sc->sc_ic.ic_enable_coex)
1483 aggr_limit = ATH_MIN((max4msframelen*3)/8, sc->sc_ic.ic_ampdu_limit);
1485 aggr_limit = ATH_MIN(max4msframelen, sc->sc_ic.ic_ampdu_limit);
1487 if (ieee_node->ni_maxampdu)
1488 aggr_limit = ATH_MIN(aggr_limit, ieee_node->ni_maxampdu);
1493 int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
1494 ath_tx_bufhead *bf_q)
1496 struct ath_tx_buf *bf_first ,*bf_prev = NULL;
1497 int nframes = 0, rl = 0;;
1498 struct ath_tx_desc *ds = NULL;
1499 struct ath_tx_buf *bf;
1500 struct ath_hal *ah = sc->sc_ah;
1501 u_int16_t aggr_limit = (64*1024 -1), al = 0, bpad = 0, al_delta;
1502 u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0;
1504 bf_first = asf_tailq_first(&tid->buf_q);
1507 bf = asf_tailq_first(&tid->buf_q);
1510 if (!BAW_WITHIN(tid->seq_start, tid->baw_size,
1511 SEQNO_FROM_BF_SEQNO(bf->bf_seqno))) {
1513 bf_first->bf_al= al;
1514 bf_first->bf_nframes = nframes;
1515 return ATH_TGT_AGGR_BAW_CLOSED;
1519 aggr_limit = ath_lookup_rate(sc, tid->an, bf);
1523 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_pktlen;
1525 if (nframes && (aggr_limit < (al + bpad + al_delta + prev_al))) {
1526 bf_first->bf_al= al;
1527 bf_first->bf_nframes = nframes;
1528 return ATH_TGT_AGGR_LIMITED;
1532 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 17)) {
1534 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 22)) {
1536 bf_first->bf_al= al;
1537 bf_first->bf_nframes = nframes;
1538 return ATH_TGT_AGGR_LIMITED;
1541 ath_tx_addto_baw(tid, bf);
1542 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1543 asf_tailq_insert_tail(bf_q, bf, bf_list);
1548 adf_os_assert(bf->bf_comp == ath_tgt_tx_comp_aggr);
1550 al += bpad + al_delta;
1551 bf->bf_ndelim = ATH_AGGR_GET_NDELIM(bf->bf_pktlen);
1553 switch (bf->bf_keytype) {
1554 case HAL_KEY_TYPE_AES:
1555 bf->bf_ndelim += ATH_AGGR_ENCRYPTDELIM;
1557 case HAL_KEY_TYPE_WEP:
1558 case HAL_KEY_TYPE_TKIP:
1559 bf->bf_ndelim += 64;
1561 case HAL_KEY_TYPE_WAPI:
1562 bf->bf_ndelim += 12;
1568 bpad = PADBYTES(al_delta) + (bf->bf_ndelim << 2);
1571 bf_prev->bf_next = bf;
1572 bf_prev->bf_lastds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1576 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1577 ah->ah_set11nAggrMiddle(ds, bf->bf_ndelim);
1579 } while (!asf_tailq_empty(&tid->buf_q));
1581 bf_first->bf_al= al;
1582 bf_first->bf_nframes = nframes;
1584 return ATH_TGT_AGGR_DONE;
1587 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf)
1591 if (bf->bf_isretried) {
1595 index = ATH_BA_INDEX(tid->seq_start, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1596 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1598 TX_BUF_BITMAP_SET(tid->tx_buf_bitmap, cindex);
1600 if (index >= ((tid->baw_tail - tid->baw_head) & (ATH_TID_MAX_BUFS - 1))) {
1601 tid->baw_tail = cindex;
1602 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1606 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1608 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1609 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1610 struct ath_tx_desc lastds;
1611 struct ath_tx_desc *ds = &lastds;
1612 struct ath_rc_series rcs[4];
1617 int nframes = bf->bf_nframes;
1618 struct ath_tx_buf *bf_next;
1619 ath_tx_bufhead bf_q;
1621 struct ath_tx_buf *bar = NULL;
1622 struct ath_txq *txq;
1626 if (tid->flag & TID_CLEANUP_INPROGRES) {
1627 ath_tx_comp_cleanup(sc, bf);
1631 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1632 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1634 if (ds->ds_txstat.ts_flags == HAL_TX_SW_FILTERED) {
1639 if (!bf->bf_isaggr) {
1640 ath_tx_comp_unaggr(sc, bf);
1644 __stats(sc, tx_compaggr);
1646 asf_tailq_init(&bf_q);
1648 seq_st = ATH_DS_BA_SEQ(ds);
1649 ba = ATH_DS_BA_BITMAP(ds);
1650 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1652 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1653 ath_tx_comp_aggr_error(sc, bf, tid);
1657 if (tx_ok && !ATH_DS_TX_BA(ds)) {
1658 __stats(sc, txaggr_babug);
1659 adf_os_print("BA Bug?\n");
1660 ath_tx_comp_aggr_error(sc, bf, tid);
1665 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1666 bf_next = bf->bf_next;
1668 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) {
1669 __stats(sc, txaggr_compgood);
1670 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1671 ath_tx_status_update_aggr(sc, bf, ds, rcs, 1);
1672 ath_tx_freebuf(sc, bf);
1674 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1680 ath_update_aggr_stats(sc, ds, nframes, nbad);
1681 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1684 ath_bar_tx(sc, tid, bar);
1687 if (!asf_tailq_empty(&bf_q)) {
1688 __stats(sc, txaggr_prepends);
1689 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1690 ath_tgt_tx_enqueue(txq, tid);
1695 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1700 struct ath_tx_desc lastds;
1701 struct ath_tx_desc *ds = &lastds;
1702 struct ath_rc_series rcs[4];
1703 struct ath_tx_buf *bar = NULL;
1704 struct ath_tx_buf *bf_next;
1705 int nframes = bf->bf_nframes;
1706 ath_tx_bufhead bf_q;
1707 struct ath_txq *txq;
1709 asf_tailq_init(&bf_q);
1712 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1713 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1716 bf_next = bf->bf_next;
1717 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1721 ath_update_aggr_stats(sc, ds, nframes, nframes);
1722 ath_rate_tx_complete(sc, tid->an, ds, rcs, nframes, nframes);
1725 ath_bar_tx(sc, tid, bar);
1728 if (!asf_tailq_empty(&bf_q)) {
1729 __stats(sc, txaggr_prepends);
1730 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1731 ath_tgt_tx_enqueue(txq, tid);
1736 ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1739 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1740 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1741 struct ath_tx_desc lastds;
1742 struct ath_tx_desc *ds = &lastds;
1743 struct ath_rc_series rcs[4];
1748 int nframes = bf->bf_nframes;
1749 struct ath_tx_buf *bf_next;
1752 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1753 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1755 seq_st = ATH_DS_BA_SEQ(ds);
1756 ba = ATH_DS_BA_BITMAP(ds);
1757 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1759 if (!bf->bf_isaggr) {
1760 ath_update_stats(sc, bf);
1762 __stats(sc, tx_compunaggr);
1764 ath_tx_status_update(sc, bf);
1766 ath_tx_freebuf(sc, bf);
1768 if (tid->flag & TID_CLEANUP_INPROGRES) {
1769 owl_tgt_tid_cleanup(sc, tid);
1777 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1778 bf_next = bf->bf_next;
1780 ath_tx_status_update_aggr(sc, bf, ds, rcs, 0);
1782 ath_tx_freebuf(sc, bf);
1786 tid->flag &= ~TID_CLEANUP_INPROGRES;
1787 ath_aggr_resume_tid(sc, tid);
1794 ath_update_aggr_stats(sc, ds, nframes, nbad);
1795 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1799 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1800 ath_tx_bufhead *bf_q, struct ath_tx_buf **bar)
1803 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1804 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1805 struct ath_tx_desc *ds = NULL;
1806 struct ath_hal *ah = sc->sc_ah;
1809 __stats(sc, txaggr_compretries);
1811 for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) {
1812 ah->ah_clr11nAggr(ds);
1813 ah->ah_set11nBurstDuration(ds, 0);
1814 ah->ah_set11nVirtualMoreFrag(ds, 0);
1817 if (bf->bf_retries >= OWLMAX_RETRIES) {
1818 __stats(sc, txaggr_xretries);
1819 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1820 ath_tx_status_update_aggr(sc, bf, bf->bf_lastds, NULL, 0);
1825 ath_tx_freebuf(sc, bf);
1830 __stats(sc, txaggr_errlast);
1831 bf = ath_buf_toggle(sc, bf, 1);
1833 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs - 1]);
1835 ath_tx_set_retry(sc, bf);
1836 asf_tailq_insert_tail(bf_q, bf, bf_list);
1840 ath_update_aggr_stats(struct ath_softc_tgt *sc,
1841 struct ath_tx_desc *ds, int nframes,
1845 u_int8_t status = ATH_DS_TX_STATUS(ds);
1846 u_int8_t txflags = ATH_DS_TX_FLAGS(ds);
1848 __statsn(sc, txaggr_longretries, ds->ds_txstat.ts_longretry);
1849 __statsn(sc, txaggr_shortretries, ds->ds_txstat.ts_shortretry);
1851 if (txflags & HAL_TX_DESC_CFG_ERR)
1852 __stats(sc, txaggr_desc_cfgerr);
1854 if (txflags & HAL_TX_DATA_UNDERRUN)
1855 __stats(sc, txaggr_data_urun);
1857 if (txflags & HAL_TX_DELIM_UNDERRUN)
1858 __stats(sc, txaggr_delim_urun);
1864 if (status & HAL_TXERR_XRETRY)
1865 __stats(sc, txaggr_compxretry);
1867 if (status & HAL_TXERR_FILT)
1868 __stats(sc, txaggr_filtered);
1870 if (status & HAL_TXERR_FIFO)
1871 __stats(sc, txaggr_fifo);
1873 if (status & HAL_TXERR_XTXOP)
1874 __stats(sc, txaggr_xtxop);
1876 if (status & HAL_TXERR_TIMER_EXPIRED)
1877 __stats(sc, txaggr_timer_exp);
1881 ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1883 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1884 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1885 struct ath_tx_desc *ds = bf->bf_lastds;
1887 ath_update_stats(sc, bf);
1888 ath_rate_tx_complete(sc, an, ds, bf->bf_rcs, 1, 0);
1890 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1891 ath_tx_retry_unaggr(sc, bf);
1894 __stats(sc, tx_compunaggr);
1896 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1897 ath_tx_status_update(sc, bf);
1898 ath_tx_freebuf(sc, bf);
1902 ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1904 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1905 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1906 struct ath_txq *txq;
1910 if (bf->bf_retries >= OWLMAX_RETRIES) {
1911 __stats(sc, txunaggr_xretry);
1912 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1913 ath_tx_status_update(sc, bf);
1914 ath_bar_tx(sc, tid, bf);
1918 __stats(sc, txunaggr_compretries);
1919 if (!bf->bf_lastds->ds_link) {
1920 __stats(sc, txunaggr_errlast);
1921 bf = ath_buf_toggle(sc, bf, 1);
1924 ath_tx_set_retry(sc, bf);
1925 asf_tailq_insert_head(&tid->buf_q, bf, bf_list);
1926 ath_tgt_tx_enqueue(txq, tid);
1930 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno)
1935 index = ATH_BA_INDEX(tid->seq_start, seqno);
1936 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1938 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, cindex);
1940 while (tid->baw_head != tid->baw_tail &&
1941 (!TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head))) {
1942 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1943 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1947 static void ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1949 struct ieee80211_frame *wh;
1951 __stats(sc, txaggr_retries);
1953 bf->bf_isretried = 1;
1955 wh = ATH_SKB_2_WH(bf->bf_skb);
1956 wh->i_fc[1] |= IEEE80211_FC1_RETRY;
1959 void ath_tgt_tx_cleanup(struct ath_softc_tgt *sc, struct ath_node_target *an,
1960 ath_atx_tid_t *tid, a_uint8_t discard_all)
1962 struct ath_tx_buf *bf;
1963 struct ath_tx_buf *bf_next;
1964 struct ath_txq *txq;
1966 txq = TID_TO_ACTXQ(tid->tidno);
1968 bf = asf_tailq_first(&tid->buf_q);
1971 if (discard_all || bf->bf_isretried) {
1972 bf_next = asf_tailq_next(bf, bf_list);
1973 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
1974 if (bf->bf_isretried)
1975 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1976 ath_tx_freebuf(sc, bf);
1980 bf->bf_comp = ath_tgt_tx_comp_normal;
1981 bf = asf_tailq_next(bf, bf_list);
1984 ath_aggr_pause_tid(sc, tid);
1986 while (tid->baw_head != tid->baw_tail) {
1987 if (TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head)) {
1989 tid->flag |= TID_CLEANUP_INPROGRES;
1990 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, tid->baw_head);
1992 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1993 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1996 if (!(tid->flag & TID_CLEANUP_INPROGRES)) {
1997 ath_aggr_resume_tid(sc, tid);
2001 /******************/
2002 /* BAR Management */
2003 /******************/
2005 static void ath_tgt_delba_send(struct ath_softc_tgt *sc,
2006 struct ieee80211_node_target *ni,
2007 a_uint8_t tidno, a_uint8_t initiator,
2008 a_uint16_t reasoncode)
2010 struct ath_node_target *an = ATH_NODE_TARGET(ni);
2011 ath_atx_tid_t *tid = ATH_AN_2_TID(an, tidno);
2012 struct wmi_data_delba wmi_delba;
2014 tid->flag &= ~TID_AGGR_ENABLED;
2016 ath_tgt_tx_cleanup(sc, an, tid, 1);
2018 wmi_delba.ni_nodeindex = ni->ni_nodeindex;
2019 wmi_delba.tidno = tid->tidno;
2020 wmi_delba.initiator = 1;
2021 wmi_delba.reasoncode = IEEE80211_REASON_UNSPECIFIED;
2023 __stats(sc, txbar_xretry);
2024 wmi_event(sc->tgt_wmi_handle,
2030 static void ath_bar_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2032 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
2033 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
2035 if (bf->bf_retries >= OWLMAX_BAR_RETRIES) {
2036 ath_tgt_delba_send(sc, bf->bf_node, tid->tidno, 1,
2037 IEEE80211_REASON_UNSPECIFIED);
2038 ath_tgt_tid_drain(sc, tid);
2041 ath_buf_comp(sc, bf);
2045 __stats(sc, txbar_compretries);
2047 if (!bf->bf_lastds->ds_link) {
2048 __stats(sc, txbar_errlast);
2049 bf = ath_buf_toggle(sc, bf, 1);
2052 bf->bf_lastds->ds_link = 0;
2054 ath_tx_set_retry(sc, bf);
2055 ath_tgt_txq_add_ucast(sc, bf);
2058 static void ath_bar_tx_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2060 struct ath_tx_desc *ds = bf->bf_lastds;
2061 struct ath_node_target *an;
2063 struct ath_txq *txq;
2065 an = (struct ath_node_target *)bf->bf_node;
2066 tid = &an->tid[bf->bf_tidno];
2067 txq = TID_TO_ACTXQ(tid->tidno);
2069 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
2070 ath_bar_retry(sc, bf);
2074 ath_aggr_resume_tid(sc, tid);
2077 ath_buf_comp(sc, bf);
2080 static void ath_bar_tx(struct ath_softc_tgt *sc,
2081 ath_atx_tid_t *tid, struct ath_tx_buf *bf)
2084 struct ieee80211_frame_bar *bar;
2086 struct ath_tx_desc *ds, *ds0;
2087 struct ath_hal *ah = sc->sc_ah;
2088 HAL_11N_RATE_SERIES series[4];
2090 adf_nbuf_queue_t skbhead;
2094 __stats(sc, tx_bars);
2096 adf_os_mem_set(&series, 0, sizeof(series));
2098 ath_aggr_pause_tid(sc, tid);
2100 skb = adf_nbuf_queue_remove(&bf->bf_skbhead);
2101 adf_nbuf_peek_header(skb, &anbdata, &anblen);
2102 adf_nbuf_trim_tail(skb, anblen);
2103 bar = (struct ieee80211_frame_bar *) anbdata;
2107 ath_dma_unmap(sc, bf);
2108 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
2110 bar->i_fc[1] = IEEE80211_FC1_DIR_NODS;
2111 bar->i_fc[0] = IEEE80211_FC0_VERSION_0 |
2112 IEEE80211_FC0_TYPE_CTL |
2113 IEEE80211_FC0_SUBTYPE_BAR;
2114 bar->i_ctl = tid->tidno << IEEE80211_BAR_CTL_TID_S |
2115 IEEE80211_BAR_CTL_COMBA;
2116 bar->i_seq = adf_os_cpu_to_le16(tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT);
2118 bf->bf_seqno = tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT;
2120 adf_nbuf_put_tail(skb, sizeof(struct ieee80211_frame_bar));
2122 bf->bf_comp = ath_bar_tx_comp;
2123 bf->bf_tidno = tid->tidno;
2124 bf->bf_node = &tid->an->ni;
2125 ath_dma_map(sc, bf);
2126 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
2129 ah->ah_setupTxDesc(ds
2130 , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
2132 , HAL_PKT_TYPE_NORMAL
2138 | HAL_TXDESC_CLRDMASK
2141 skbhead = bf->bf_skbhead;
2145 for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) {
2146 ah->ah_clr11nAggr(ds0);
2149 ath_filltxdesc(sc, bf);
2151 for (i = 0 ; i < 4; i++) {
2152 series[i].Tries = ATH_TXMAXTRY;
2153 series[i].Rate = min_rate;
2154 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
2157 ah->ah_set11nRateScenario(bf->bf_desc, 0, 0, series, 4, 4);
2158 ath_tgt_txq_add_ucast(sc, bf);