2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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37 #include "ah_internal.h"
39 #include "ar5416reg.h"
40 #include "ar5416desc.h"
42 #define N(a) (sizeof(a)/sizeof(a[0]))
43 #define AR_INTR_SPURIOUS 0xffffffff
44 #define ar5416_desc ar5416_desc_20
45 #define AR5416_ABORT_LOOPS 1000
46 #define AR5416_ABORT_WAIT 5
47 #define AR5416DESC AR5416DESC_20
48 #define AR5416DESC_CONST AR5416DESC_CONST_20
54 static const struct ath_hal_private ar5416hal_10 = {{
55 .ah_getRateTable = ar5416GetRateTable,
56 .ah_detach = ar5416Detach,
58 /* Transmit functions */
59 .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel,
60 .ah_setTxDP = ar5416SetTxDP,
61 .ah_numTxPending = ar5416NumTxPending,
62 .ah_startTxDma = ar5416StartTxDma,
63 .ah_stopTxDma = ar5416StopTxDma,
65 .ah_abortTxDma = ar5416AbortTxDma,
68 .ah_getTsf64 = ar5416GetTsf64,
69 .ah_setRxFilter = ar5416SetRxFilter,
72 .ah_setRxDP = ar5416SetRxDP,
73 .ah_stopDmaReceive = ar5416StopDmaReceive,
74 .ah_enableReceive = ar5416EnableReceive,
75 .ah_stopPcuReceive = ar5416StopPcuReceive,
77 /* Interrupt Functions */
78 .ah_isInterruptPending = ar5416IsInterruptPending,
79 .ah_getPendingInterrupts = ar5416GetPendingInterrupts,
80 .ah_setInterrupts = ar5416SetInterrupts,
84 void ar5416Detach(struct ath_hal *ah)
86 HALASSERT(ah != AH_NULL);
91 ar5416Attach(HAL_SOFTC sc, adf_os_device_t dev, HAL_STATUS *status)
93 struct ath_hal_5416 *ahp;
96 ahp = ath_hal_malloc(sizeof (struct ath_hal_5416));
101 ah = &ahp->ah_priv.h;
103 OS_MEMCPY(&ahp->ah_priv, &ar5416hal_10, sizeof(struct ath_hal_private));
108 ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20;
109 ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20;
110 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20;
111 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20;
112 ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20;
113 ah->ah_clr11nAggr = ar5416Clr11nAggr_20;
114 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20;
115 ah->ah_setupRxDesc = ar5416SetupRxDesc_20;
116 ah->ah_procRxDescFast = ar5416ProcRxDescFast_20;
117 ah->ah_setupTxDesc = ar5416SetupTxDesc_20;
118 ah->ah_fillTxDesc = ar5416FillTxDesc_20;
119 ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20;
120 ah->ah_procTxDesc = ar5416ProcTxDesc_20;
121 ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20;
126 /**********************/
127 /* Interrupt Handling */
128 /**********************/
130 HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
132 a_uint32_t host_isr =
133 ioread32_mac(AR_INTR_ASYNC_CAUSE);
135 * Some platforms trigger our ISR before applying power to
136 * the card, so make sure.
138 return ((host_isr != AR_INTR_SPURIOUS) && (host_isr & AR_INTR_MAC_IRQ));
141 HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
145 HAL_BOOL fatal_int = AH_FALSE;
146 a_uint32_t sync_cause;
148 if (ioread32_mac(AR_INTR_ASYNC_CAUSE)
150 if ((ioread32_mac(AR_RTC_STATUS)
151 & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
160 isr = ioread32_mac(AR_ISR_RAC);
161 if (isr == 0xffffffff) {
166 *masked = isr & HAL_INT_COMMON;
168 #ifdef AR5416_INT_MITIGATION
169 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) {
170 *masked |= HAL_INT_RX;
172 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) {
173 *masked |= HAL_INT_TX;
177 if (isr & AR_ISR_BCNMISC) {
180 s2_s = ioread32_mac(AR_ISR_S2_S);
182 if (s2_s & AR_ISR_S2_GTT) {
183 *masked |= HAL_INT_GTT;
186 if (s2_s & AR_ISR_S2_CST) {
187 *masked |= HAL_INT_CST;
191 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
192 *masked |= HAL_INT_RX;
193 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
194 struct ath_hal_5416 *ahp = AH5416(ah);
195 a_uint32_t s0_s, s1_s;
197 *masked |= HAL_INT_TX;
198 s0_s = ioread32_mac(AR_ISR_S0_S);
199 s1_s = ioread32_mac(AR_ISR_S1_S);
200 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
201 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
202 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
203 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
207 sync_cause = ioread32_mac(AR_INTR_SYNC_CAUSE);
208 fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
209 (sync_cause & (AR_INTR_SYNC_HOST1_FATAL
210 | AR_INTR_SYNC_HOST1_PERR))) ? AH_TRUE : AH_FALSE;
212 if (AH_TRUE == fatal_int) {
213 iowrite32_mac(AR_INTR_SYNC_CAUSE_CLR, sync_cause);
214 (void) ioread32_mac(AR_INTR_SYNC_CAUSE_CLR);
221 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
223 struct ath_hal_5416 *ahp = AH5416(ah);
224 a_uint32_t omask = ahp->ah_maskReg;
227 if (omask & HAL_INT_GLOBAL) {
228 iowrite32_mac(AR_IER, AR_IER_DISABLE);
229 (void) ioread32_mac(AR_IER);
232 mask = ints & HAL_INT_COMMON;
233 if (ints & HAL_INT_TX) {
234 #ifdef AR5416_INT_MITIGATION
235 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
238 mask |= AR_IMR_TXDESC;
240 mask |= AR_IMR_TXERR;
241 mask |= AR_IMR_TXEOL;
243 if (ints & HAL_INT_RX) {
244 mask |= AR_IMR_RXERR;
245 #ifdef AR5416_INT_MITIGATION
246 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
248 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
252 if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
253 mask |= AR_IMR_BCNMISC;
256 iowrite32_mac(AR_IMR, mask);
257 (void) ioread32_mac(AR_IMR);
258 ahp->ah_maskReg = ints;
260 /* Re-enable interrupts if they were enabled before. */
261 if (ints & HAL_INT_GLOBAL) {
262 iowrite32_mac(AR_IER, AR_IER_ENABLE);
263 /* See explanation above... */
264 (void) ioread32_mac(AR_IER);
267 iowrite32_mac(AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
268 iowrite32_mac(AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
269 iowrite32_mac(AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
278 #define ATH9K_HTC_MAX_TSF_READ 3
280 u_int64_t ar5416GetTsf64(struct ath_hal *ah)
282 a_uint32_t tsf_lower, tsf_upper1, tsf_upper2;
285 tsf_upper1 = ioread32_mac(AR_TSF_U32);
286 for (i = 0; i < ATH9K_HTC_MAX_TSF_READ; i++) {
287 tsf_lower = ioread32_mac(AR_TSF_L32);
288 tsf_upper2 = ioread32_mac(AR_TSF_U32);
289 if (tsf_upper2 == tsf_upper1)
291 tsf_upper1 = tsf_upper2;
294 return (((u_int64_t)tsf_upper2 << 32) | tsf_lower);
300 void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
302 iowrite32_mac(AR_RXDP, rxdp);
303 HALASSERT(ioread32_mac(AR_RXDP) == rxdp);
306 HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
308 iowrite32_mac(AR_CR, AR_CR_RXD); /* Set receive disable bit */
309 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
316 void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits)
320 iowrite32_mac(AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
322 if (bits & HAL_RX_FILTER_PHYRADAR)
323 phybits |= AR_PHY_ERR_RADAR;
324 if (bits & HAL_RX_FILTER_PHYERR)
325 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
326 iowrite32_mac(AR_PHY_ERR, phybits);
328 iowrite32_mac(AR_RXCFG,
329 ioread32_mac(AR_RXCFG)
332 iowrite32_mac(AR_RXCFG,
333 ioread32_mac(AR_RXCFG)
338 void ar5416EnableReceive(struct ath_hal *ah)
340 iowrite32_mac(AR_CR, AR_CR_RXE);
343 void ar5416StopPcuReceive(struct ath_hal *ah)
345 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
348 HAL_BOOL ar5416SetupRxDesc_20(struct ath_rx_desc *ds,
349 a_uint32_t size, a_uint32_t flags)
351 struct ar5416_desc *ads = AR5416DESC(ds);
353 HALASSERT((size &~ AR_BufLen) == 0);
355 ads->ds_ctl1 = size & AR_BufLen;
356 if (flags & HAL_RXDESC_INTREQ)
357 ads->ds_ctl1 |= AR_RxIntrReq;
359 /* this should be enough */
360 ads->ds_rxstatus8 &= ~AR_RxDone;
365 HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds,
366 a_uint32_t pa, struct ath_desc *nds,
367 struct ath_rx_status *rx_stats)
369 struct ar5416_desc ads;
370 struct ar5416_desc *adsp = AR5416DESC(ds);
371 struct ar5416_desc *ands = AR5416DESC(nds);
373 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
374 return HAL_EINPROGRESS;
376 * Given the use of a self-linked tail be very sure that the hw is
377 * done with this descriptor; the hw may have done this descriptor
378 * once and picked it up again...make sure the hw has moved on.
380 if ((ands->ds_rxstatus8 & AR_RxDone) == 0
381 && ioread32_mac(AR_RXDP) == pa)
382 return HAL_EINPROGRESS;
385 * Now we need to get the stats from the descriptor. Since desc are
386 * uncached, lets make a copy of the stats first. Note that, since we
387 * touch most of the rx stats, a memcpy would always be more efficient
389 * Next we fill in all values in a caller passed stack variable.
390 * This reduces the number of uncached accesses.
391 * Do this copy here, after the check so that when the checks fail, we
392 * dont end up copying the entire stats uselessly.
394 ads.u.rx = adsp->u.rx;
396 rx_stats->rs_status = 0;
397 rx_stats->rs_flags = 0;
399 rx_stats->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
400 rx_stats->rs_tstamp = ads.AR_RcvTimestamp;
402 /* XXX what about KeyCacheMiss? */
403 rx_stats->rs_rssi_combined =
404 MS(ads.ds_rxstatus4, AR_RxRSSICombined);
405 rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
406 rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
407 rx_stats->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
408 rx_stats->rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
409 rx_stats->rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
410 rx_stats->rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
411 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
412 rx_stats->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
414 rx_stats->rs_keyix = HAL_RXKEYIX_INVALID;
415 /* NB: caller expected to do rate table mapping */
416 rx_stats->rs_rate = RXSTATUS_RATE(ah, (&ads));
417 rx_stats->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
419 rx_stats->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
420 rx_stats->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
421 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
422 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
424 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
425 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_PRE;
426 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
427 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_POST;
428 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
429 rx_stats->rs_flags |= HAL_RX_DECRYPT_BUSY;
431 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
433 * These four bits should not be set together. The
434 * 5416 spec states a Michael error can only occur if
435 * DecryptCRCErr not set (and TKIP is used). Experience
436 * indicates however that you can also get Michael errors
437 * when a CRC error is detected, but these are specious.
438 * Consequently we filter them out here so we don't
439 * confuse and/or complicate drivers.
441 if (ads.ds_rxstatus8 & AR_CRCErr)
442 rx_stats->rs_status |= HAL_RXERR_CRC;
443 else if (ads.ds_rxstatus8 & AR_PHYErr) {
446 rx_stats->rs_status |= HAL_RXERR_PHY;
447 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
448 rx_stats->rs_phyerr = phyerr;
449 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
450 rx_stats->rs_status |= HAL_RXERR_DECRYPT;
451 else if (ads.ds_rxstatus8 & AR_MichaelErr)
452 rx_stats->rs_status |= HAL_RXERR_MIC;
454 rx_stats->evm0=ads.AR_RxEVM0;
455 rx_stats->evm1=ads.AR_RxEVM1;
456 rx_stats->evm2=ads.AR_RxEVM2;
465 HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
467 struct ath_hal_5416 *ahp = AH5416(ah);
468 a_uint32_t txcfg, curLevel, newLevel;
472 * Disable interrupts while futzing with the fifo level.
474 omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
476 txcfg = ioread32_mac(AR_TXCFG);
477 curLevel = MS(txcfg, AR_FTRIG);
481 if (curLevel < MAX_TX_FIFO_THRESHOLD)
483 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
485 if (newLevel != curLevel)
486 iowrite32_mac(AR_TXCFG,
487 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
489 /* re-enable chip interrupts */
490 ar5416SetInterrupts(ah, omask);
492 return (newLevel != curLevel);
495 HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp)
497 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
498 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
501 * Make sure that TXE is deasserted before setting the TXDP. If TXE
502 * is still asserted, setting TXDP will have no effect.
504 HALASSERT((ioread32_mac(AR_Q_TXE) & (1 << q)) == 0);
506 iowrite32_mac(AR_QTXDP(q), txdp);
511 HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q)
513 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
514 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
516 /* Check to be sure we're not enabling a q that has its TXD bit set. */
517 HALASSERT((ioread32_mac(AR_Q_TXD) & (1 << q)) == 0);
519 iowrite32_mac(AR_Q_TXE, 1 << q);
524 a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q)
528 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
529 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
531 npend = ioread32_mac(AR_QSTS(q))
532 & AR_Q_STS_PEND_FR_CNT;
535 * Pending frame count (PFC) can momentarily go to zero
536 * while TXE remains asserted. In other words a PFC of
537 * zero is not sufficient to say that the queue has stopped.
539 if (ioread32_mac(AR_Q_TXE) & (1 << q))
543 if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
544 if (ioread32_mac(AR_Q_RDYTIMESHDN)
546 isrPrintf("RTSD on CAB queue\n");
547 /* Clear the ReadyTime shutdown status bits */
548 iowrite32_mac(AR_Q_RDYTIMESHDN, 1 << q);
555 HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah)
560 * set txd on all queues
562 iowrite32_mac(AR_Q_TXD, AR_Q_TXD_M);
567 OS_REG_SET_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
568 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
569 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
572 * wait on all tx queues
574 for (q = 0; q < AR_NUM_QCU; q++) {
575 for (i = 0; i < AR5416_ABORT_LOOPS; i++) {
576 if (!ar5416NumTxPending(ah, q))
579 OS_DELAY(AR5416_ABORT_WAIT);
581 if (i == AR5416_ABORT_LOOPS) {
587 * clear tx abort bits
589 OS_REG_CLR_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
590 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
591 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
596 iowrite32_mac(AR_Q_TXD, 0);
601 HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q)
605 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
607 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
609 iowrite32_mac(AR_Q_TXD, 1 << q);
610 for (i = 1000; i != 0; i--) {
611 if (ar5416NumTxPending(ah, q) == 0)
613 OS_DELAY(100); /* XXX get actual value */
616 iowrite32_mac(AR_Q_TXD, 0);
620 HAL_BOOL ar5416SetupTxDesc_20(struct ath_tx_desc *ds,
625 a_uint32_t txRate0, a_uint32_t txTries0,
628 a_uint32_t rtsctsRate,
629 a_uint32_t rtsctsDuration)
631 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
633 struct ar5416_desc *ads = AR5416DESC(ds);
637 ads->ds_txstatus9 &= ~AR_TxDone;
639 HALASSERT(txTries0 != 0);
640 HALASSERT(isValidPktType(type));
641 HALASSERT(isValidTxRate(txRate0));
642 HALASSERT((flags & RTSCTS) != RTSCTS);
647 ads->ds_ctl0 = (pktLen & AR_FrameLen)
648 | (txPower << AR_XmitPower_S)
649 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
650 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
651 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
653 ads->ds_ctl1 = (type << AR_FrameType_S)
654 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
655 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0);
656 ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S);
658 ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
659 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1)
660 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
661 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3);
663 if (keyIx != HAL_TXKEYIX_INVALID) {
664 /* XXX validate key index */
665 ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
666 ads->ds_ctl0 |= AR_DestIdxValid;
669 if (flags & RTSCTS) {
670 if (!isValidTxRate(rtsctsRate)) {
673 /* XXX validate rtsctsDuration */
674 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
675 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
676 ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur);
677 ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
684 HAL_BOOL ar5416FillTxDesc_20(struct ath_tx_desc *ds,
685 a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
686 const struct ath_tx_desc *ds0)
688 struct ar5416_desc *ads = AR5416DESC(ds);
690 HALASSERT((segLen &~ AR_BufLen) == 0);
694 * First descriptor, don't clobber xmit control data
695 * setup by ar5416SetupTxDesc.
697 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
698 } else if (lastSeg) {
700 * Last descriptor in a multi-descriptor frame,
701 * copy the multi-rate transmit parameters from
702 * the first frame for processing on completion.
705 ads->ds_ctl1 = segLen;
706 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
707 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
710 * Intermediate descriptor in a multi-descriptor frame.
713 ads->ds_ctl1 = segLen | AR_TxMore;
717 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
722 HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_tx_desc *ds,
723 HAL_KEY_TYPE keyType)
725 struct ar5416_desc *ads = AR5416DESC(ds);
727 ads->ds_ctl6 = SM(keyType, AR_EncrType);
731 HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds)
733 struct ar5416_desc *ads = AR5416DESC(gds);
734 struct ath_tx_desc *ds = (struct ath_tx_desc *)gds;
736 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
737 return HAL_EINPROGRESS;
739 ads->ds_txstatus9 &= ~AR_TxDone;
741 /* Update software copies of the HW status */
742 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
743 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
744 ds->ds_txstat.ts_status = 0;
745 ds->ds_txstat.ts_flags = 0;
747 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
748 ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
749 if (ads->ds_txstatus1 & AR_Filtered)
750 ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
751 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
752 ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
753 if (ads->ds_txstatus9 & AR_TxOpExceeded)
754 ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
755 if (ads->ds_txstatus1 & AR_TxTimerExpired)
756 ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
758 if (ads->ds_txstatus1 & AR_DescCfgErr)
759 ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
760 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
761 ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
762 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
764 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
765 ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
766 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
768 if (ads->ds_txstatus0 & AR_TxBaStatus) {
769 ds->ds_txstat.ts_flags |= HAL_TX_BA;
770 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
771 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
775 * Extract the transmit rate used and mark the rate as
776 * ``alternate'' if it wasn't the series 0 rate.
778 ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx);
779 ds->ds_txstat.ts_rssi_combined =
780 MS(ads->ds_txstatus5, AR_TxRSSICombined);
781 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
782 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
783 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
784 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
785 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
786 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
787 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
788 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
789 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
790 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
791 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
792 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
793 ds->ds_txstat.ts_antenna = 0; /* ignored for owl */
798 void ar5416Set11nTxDesc_20(struct ath_tx_desc *ds,
799 a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
800 a_uint32_t keyIx, HAL_KEY_TYPE keyType,
803 struct ar5416_desc *ads = AR5416DESC(ds);
805 HALASSERT(isValidPktType(type));
806 HALASSERT(isValidKeyType(keyType));
811 ads->ds_ctl0 = (pktLen & AR_FrameLen)
812 | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
813 | SM(txPower, AR_XmitPower)
814 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
815 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
816 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
817 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
818 | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
819 | (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0);
821 ads->ds_ctl1 = (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
822 | SM(type, AR_FrameType)
823 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
824 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
825 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
827 ads->ds_ctl6 = SM(keyType, AR_EncrType);
830 void ar5416Set11nRateScenario_20(struct ath_tx_desc *ds,
831 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
832 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
835 struct ar5416_desc *ads = AR5416DESC(ds);
838 HALASSERT(nseries == 4);
842 * Rate control settings override
844 ds_ctl0 = ads->ds_ctl0;
846 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
847 if (flags & HAL_TXDESC_RTSENA) {
848 ds_ctl0 &= ~AR_CTSEnable;
849 ds_ctl0 |= AR_RTSEnable;
851 ds_ctl0 &= ~AR_RTSEnable;
852 ds_ctl0 |= AR_CTSEnable;
855 /* this line is only difference between merlin and k2
856 * Current one is for merlin */
857 ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
860 ads->ds_ctl0 = ds_ctl0;
862 ads->ds_ctl2 = set11nTries(series, 0)
863 | set11nTries(series, 1)
864 | set11nTries(series, 2)
865 | set11nTries(series, 3)
866 | (durUpdateEn ? AR_DurUpdateEn : 0);
868 ads->ds_ctl3 = set11nRate(series, 0)
869 | set11nRate(series, 1)
870 | set11nRate(series, 2)
871 | set11nRate(series, 3);
873 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
874 | set11nPktDurRTSCTS(series, 1);
876 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
877 | set11nPktDurRTSCTS(series, 3);
879 ads->ds_ctl7 = set11nRateFlags(series, 0)
880 | set11nRateFlags(series, 1)
881 | set11nRateFlags(series, 2)
882 | set11nRateFlags(series, 3)
883 | SM(rtsctsRate, AR_RTSCTSRate);
886 void ar5416Set11nAggrFirst_20(struct ath_tx_desc *ds, a_uint32_t aggrLen,
887 a_uint32_t numDelims)
889 struct ar5416_desc *ads = AR5416DESC(ds);
891 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
893 ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim);
894 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) |
895 SM(numDelims, AR_PadDelim);
898 void ar5416Set11nAggrMiddle_20(struct ath_tx_desc *ds, a_uint32_t numDelims)
900 struct ar5416_desc *ads = AR5416DESC(ds);
903 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
906 * We use a stack variable to manipulate ctl6 to reduce uncached
907 * read modify, modfiy, write.
910 ctl6 &= ~AR_PadDelim;
911 ctl6 |= SM(numDelims, AR_PadDelim);
915 void ar5416Set11nAggrLast_20(struct ath_tx_desc *ds)
917 struct ar5416_desc *ads = AR5416DESC(ds);
919 ads->ds_ctl1 |= AR_IsAggr;
920 ads->ds_ctl1 &= ~AR_MoreAggr;
921 ads->ds_ctl6 &= ~AR_PadDelim;
924 void ar5416Clr11nAggr_20(struct ath_tx_desc *ds)
926 struct ar5416_desc *ads = AR5416DESC(ds);
928 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
931 void ar5416Set11nBurstDuration_20(struct ath_tx_desc *ds,
932 a_uint32_t burstDuration)
934 struct ar5416_desc *ads = AR5416DESC(ds);
936 ads->ds_ctl2 &= ~AR_BurstDur;
937 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
940 void ar5416Set11nVirtualMoreFrag_20(struct ath_tx_desc *ds,
943 struct ar5416_desc *ads = AR5416DESC(ds);
946 ads->ds_ctl0 |= AR_VirtMoreFrag;
948 ads->ds_ctl0 &= ~AR_VirtMoreFrag;