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25 * xtensa/config/core-matmap.h -- Memory access and translation mapping
26 * parameters (CHAL) of the Xtensa processor core configuration.
28 * If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
29 * this file) for more details.
31 * In the Xtensa processor products released to date, all parameters
32 * defined in this file are derivable (at least in theory) from
33 * information contained in the core-isa.h header file.
34 * In particular, the following core configuration parameters are relevant:
35 * XCHAL_HAVE_CACHEATTR
36 * XCHAL_HAVE_MIMIC_CACHEATTR
37 * XCHAL_HAVE_XLT_CACHEATTR
39 * XCHAL_ITLB_ARF_ENTRIES_LOG2
40 * XCHAL_DTLB_ARF_ENTRIES_LOG2
41 * XCHAL_DCACHE_IS_WRITEBACK
42 * XCHAL_ICACHE_SIZE (presence of I-cache)
43 * XCHAL_DCACHE_SIZE (presence of D-cache)
44 * XCHAL_HW_VERSION_MAJOR
45 * XCHAL_HW_VERSION_MINOR
49 #ifndef XTENSA_CONFIG_CORE_MATMAP_H
50 #define XTENSA_CONFIG_CORE_MATMAP_H
53 /*----------------------------------------------------------------------
54 CACHE (MEMORY ACCESS) ATTRIBUTES
55 ----------------------------------------------------------------------*/
58 /* Cache Attribute encodings -- lists of access modes for each cache attribute: */
59 #define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
60 XTHAL_FAM_BYPASS XCHAL_SEP \
61 XTHAL_FAM_BYPASS XCHAL_SEP \
62 XTHAL_FAM_BYPASS XCHAL_SEP \
63 XTHAL_FAM_BYPASS XCHAL_SEP \
64 XTHAL_FAM_EXCEPTION XCHAL_SEP \
65 XTHAL_FAM_EXCEPTION XCHAL_SEP \
66 XTHAL_FAM_EXCEPTION XCHAL_SEP \
67 XTHAL_FAM_EXCEPTION XCHAL_SEP \
68 XTHAL_FAM_EXCEPTION XCHAL_SEP \
69 XTHAL_FAM_EXCEPTION XCHAL_SEP \
70 XTHAL_FAM_EXCEPTION XCHAL_SEP \
71 XTHAL_FAM_EXCEPTION XCHAL_SEP \
72 XTHAL_FAM_EXCEPTION XCHAL_SEP \
73 XTHAL_FAM_EXCEPTION XCHAL_SEP \
75 #define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \
76 XTHAL_LAM_BYPASSG XCHAL_SEP \
77 XTHAL_LAM_BYPASSG XCHAL_SEP \
78 XTHAL_LAM_EXCEPTION XCHAL_SEP \
79 XTHAL_LAM_BYPASSG XCHAL_SEP \
80 XTHAL_LAM_EXCEPTION XCHAL_SEP \
81 XTHAL_LAM_EXCEPTION XCHAL_SEP \
82 XTHAL_LAM_EXCEPTION XCHAL_SEP \
83 XTHAL_LAM_EXCEPTION XCHAL_SEP \
84 XTHAL_LAM_EXCEPTION XCHAL_SEP \
85 XTHAL_LAM_EXCEPTION XCHAL_SEP \
86 XTHAL_LAM_EXCEPTION XCHAL_SEP \
87 XTHAL_LAM_EXCEPTION XCHAL_SEP \
88 XTHAL_LAM_EXCEPTION XCHAL_SEP \
89 XTHAL_LAM_BYPASSG XCHAL_SEP \
91 #define XCHAL_SCA_LIST XTHAL_SAM_BYPASS XCHAL_SEP \
92 XTHAL_SAM_BYPASS XCHAL_SEP \
93 XTHAL_SAM_BYPASS XCHAL_SEP \
94 XTHAL_SAM_EXCEPTION XCHAL_SEP \
95 XTHAL_SAM_BYPASS XCHAL_SEP \
96 XTHAL_SAM_EXCEPTION XCHAL_SEP \
97 XTHAL_SAM_EXCEPTION XCHAL_SEP \
98 XTHAL_SAM_EXCEPTION XCHAL_SEP \
99 XTHAL_SAM_EXCEPTION XCHAL_SEP \
100 XTHAL_SAM_EXCEPTION XCHAL_SEP \
101 XTHAL_SAM_EXCEPTION XCHAL_SEP \
102 XTHAL_SAM_EXCEPTION XCHAL_SEP \
103 XTHAL_SAM_EXCEPTION XCHAL_SEP \
104 XTHAL_SAM_EXCEPTION XCHAL_SEP \
105 XTHAL_SAM_BYPASS XCHAL_SEP \
110 * Specific encoded cache attribute values of general interest.
111 * If a specific cache mode is not available, the closest available
112 * one is returned instead (eg. writethru instead of writeback,
113 * bypass instead of writethru).
115 #define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
116 #define XCHAL_CA_WRITETHRU 2 /* cache enabled (write-through) mode */
117 #define XCHAL_CA_WRITEBACK 2 /* cache enabled (write-back) mode */
118 #define XCHAL_CA_BYPASS_RW 0 /* cache disabled (bypassed) mode (no exec) */
119 #define XCHAL_CA_WRITETHRU_RW 0 /* cache enabled (write-through) mode (no exec) */
120 #define XCHAL_CA_WRITEBACK_RW 0 /* cache enabled (write-back) mode (no exec) */
121 #define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
122 #define XCHAL_CA_ISOLATE 0 /* cache isolate (accesses go to cache not memory) mode */
125 /*----------------------------------------------------------------------
127 ----------------------------------------------------------------------*/
130 * General notes on MMU parameters.
133 * ASID = address-space ID (acts as an "extension" of virtual addresses)
134 * VPN = virtual page number
135 * PPN = physical page number
136 * CA = encoded cache attribute (access modes)
137 * TLB = translation look-aside buffer (term is stretched somewhat here)
138 * I = instruction (fetch accesses)
139 * D = data (load and store accesses)
140 * way = each TLB (ITLB and DTLB) consists of a number of "ways"
141 * that simultaneously match the virtual address of an access;
142 * a TLB successfully translates a virtual address if exactly
143 * one way matches the vaddr; if none match, it is a miss;
144 * if multiple match, one gets a "multihit" exception;
145 * each way can be independently configured in terms of number of
146 * entries, page sizes, which fields are writable or constant, etc.
147 * set = group of contiguous ways with exactly identical parameters
148 * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
149 * from the page table and storing it in one of the auto-refill ways;
150 * if this PTE load also misses, a miss exception is posted for s/w.
151 * min-wired = a "min-wired" way can be used to map a single (minimum-sized)
152 * page arbitrarily under program control; it has a single entry,
153 * is non-auto-refill (some other way(s) must be auto-refill),
154 * all its fields (VPN, PPN, ASID, CA) are all writable, and it
155 * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
156 * restriction is that this be the only page size it supports).
158 * TLB way entries are virtually indexed.
159 * TLB ways that support multiple page sizes:
160 * - must have all writable VPN and PPN fields;
161 * - can only use one page size at any given time (eg. setup at startup),
162 * selected by the respective ITLBCFG or DTLBCFG special register,
163 * whose bits n*4+3 .. n*4 index the list of page sizes for way n
164 * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
165 * this list may be sparse for auto-refill ways because auto-refill
166 * ways have independent lists of supported page sizes sharing a
167 * common encoding with PTE entries; the encoding is the index into
168 * this list; unsupported sizes for a given way are zero in the list;
169 * selecting unsupported sizes results in undefined hardware behaviour;
170 * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
173 #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
174 #define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
175 #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
176 #define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
177 #define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */
178 #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */
181 /*** Instruction TLB: ***/
183 #define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
184 #define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
185 #define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
186 #define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */
188 /* Way set to which each way belongs: */
189 #define XCHAL_ITLB_WAY0_SET 0
191 /* Ways sets that are used by hardware auto-refill (ARF): */
192 #define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
194 /* Way sets that are "min-wired" (see terminology comment above): */
195 #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
198 /* ITLB way set 0 (group of ways 0 thru 0): */
199 #define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
200 #define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
201 #define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
202 #define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
203 #define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
204 #define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
205 #define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
206 #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
207 #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
208 #define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
209 2^PAGESZ_BITS entries in list, unsupported entries are zero */
210 #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
211 #define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
212 #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
213 #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
214 #define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
215 #define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
216 #define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
217 #define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
218 /* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */
219 #define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
220 #define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
221 #define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
222 #define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
223 #define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
224 #define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
225 #define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
226 #define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
227 /* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */
228 #define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000
229 #define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000
230 #define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000
231 #define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000
232 #define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000
233 #define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000
234 #define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000
235 #define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000
236 /* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */
237 #define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
238 #define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
239 #define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
240 #define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
241 #define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
242 #define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
243 #define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
244 #define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
249 #define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
250 #define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
251 #define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
252 #define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */
254 /* Way set to which each way belongs: */
255 #define XCHAL_DTLB_WAY0_SET 0
257 /* Ways sets that are used by hardware auto-refill (ARF): */
258 #define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
260 /* Way sets that are "min-wired" (see terminology comment above): */
261 #define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
264 /* DTLB way set 0 (group of ways 0 thru 0): */
265 #define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
266 #define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
267 #define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
268 #define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
269 #define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
270 #define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
271 #define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
272 #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
273 #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
274 #define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
275 2^PAGESZ_BITS entries in list, unsupported entries are zero */
276 #define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
277 #define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
278 #define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
279 #define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
280 #define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
281 #define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
282 #define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
283 #define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
284 /* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */
285 #define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
286 #define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
287 #define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
288 #define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
289 #define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
290 #define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
291 #define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
292 #define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
293 /* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */
294 #define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000
295 #define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000
296 #define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000
297 #define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000
298 #define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000
299 #define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000
300 #define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000
301 #define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000
302 /* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */
303 #define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
304 #define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
305 #define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
306 #define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
307 #define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
308 #define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
309 #define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
310 #define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
315 #endif /*XTENSA_CONFIG_CORE_MATMAP_H*/