2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 /*************************************************************************/
36 /* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */
38 /* Module Name : uart.h */
41 /* This file contains definition of uart registers, marco and api. */
46 /*************************************************************************/
51 #include "k2/reg_defs.h"
53 /************************** Register deinition ***************************/
54 #define RBR_ADDRESS 0x00051000
55 #define RBR_OFFSET 0x00000000
58 #define RBR_RBR_MASK 0x000000ff
59 #define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB)
60 #define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK)
62 #define THR_ADDRESS 0x00051000
63 #define THR_OFFSET 0x00000000
66 #define THR_THR_MASK 0x000000ff
67 #define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB)
68 #define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK)
70 #define DLL_ADDRESS 0x00051000
71 #define DLL_OFFSET 0x00000000
74 #define DLL_DLL_MASK 0x000000ff
75 #define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB)
76 #define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK)
78 #define DLH_ADDRESS 0x00051004
79 #define DLH_OFFSET 0x00000004
82 #define DLH_DLH_MASK 0x000000ff
83 #define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB)
84 #define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK)
86 #define IER_ADDRESS 0x00051004
87 #define IER_OFFSET 0x00000004
88 #define IER_EDDSI_MSB 3
89 #define IER_EDDSI_LSB 3
90 #define IER_EDDSI_MASK 0x00000008
91 #define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB)
92 #define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK)
93 #define IER_ELSI_MSB 2
94 #define IER_ELSI_LSB 2
95 #define IER_ELSI_MASK 0x00000004
96 #define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB)
97 #define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK)
98 #define IER_ETBEI_MSB 1
99 #define IER_ETBEI_LSB 1
100 #define IER_ETBEI_MASK 0x00000002
101 #define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB)
102 #define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK)
103 #define IER_ERBFI_MSB 0
104 #define IER_ERBFI_LSB 0
105 #define IER_ERBFI_MASK 0x00000001
106 #define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB)
107 #define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK)
109 #define IIR_ADDRESS 0x00051008
110 #define IIR_OFFSET 0x00000008
111 #define IIR_FIFO_STATUS_MSB 7
112 #define IIR_FIFO_STATUS_LSB 6
113 #define IIR_FIFO_STATUS_MASK 0x000000c0
114 #define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB)
115 #define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK)
116 #define IIR_IID_MSB 3
117 #define IIR_IID_LSB 0
118 #define IIR_IID_MASK 0x0000000f
119 #define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB)
120 #define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK)
122 #define FCR_ADDRESS 0x00051008
123 #define FCR_OFFSET 0x00000008
124 #define FCR_RCVR_TRIG_MSB 7
125 #define FCR_RCVR_TRIG_LSB 6
126 #define FCR_RCVR_TRIG_MASK 0x000000c0
127 #define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB)
128 #define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK)
129 #define FCR_DMA_MODE_MSB 3
130 #define FCR_DMA_MODE_LSB 3
131 #define FCR_DMA_MODE_MASK 0x00000008
132 #define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB)
133 #define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK)
134 #define FCR_XMIT_FIFO_RST_MSB 2
135 #define FCR_XMIT_FIFO_RST_LSB 2
136 #define FCR_XMIT_FIFO_RST_MASK 0x00000004
137 #define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB)
138 #define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK)
139 #define FCR_RCVR_FIFO_RST_MSB 1
140 #define FCR_RCVR_FIFO_RST_LSB 1
141 #define FCR_RCVR_FIFO_RST_MASK 0x00000002
142 #define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB)
143 #define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK)
144 #define FCR_FIFO_EN_MSB 0
145 #define FCR_FIFO_EN_LSB 0
146 #define FCR_FIFO_EN_MASK 0x00000001
147 #define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB)
148 #define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK)
150 #define LCR_ADDRESS 0x0005100c
151 #define LCR_OFFSET 0x0000000c
152 #define LCR_DLAB_MSB 7
153 #define LCR_DLAB_LSB 7
154 #define LCR_DLAB_MASK 0x00000080
155 #define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB)
156 #define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK)
157 #define LCR_BREAK_MSB 6
158 #define LCR_BREAK_LSB 6
159 #define LCR_BREAK_MASK 0x00000040
160 #define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB)
161 #define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK)
162 #define LCR_EPS_MSB 4
163 #define LCR_EPS_LSB 4
164 #define LCR_EPS_MASK 0x00000010
165 #define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB)
166 #define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK)
167 #define LCR_PEN_MSB 3
168 #define LCR_PEN_LSB 3
169 #define LCR_PEN_MASK 0x00000008
170 #define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB)
171 #define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK)
172 #define LCR_STOP_MSB 2
173 #define LCR_STOP_LSB 2
174 #define LCR_STOP_MASK 0x00000004
175 #define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB)
176 #define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK)
177 #define LCR_CLS_MSB 1
178 #define LCR_CLS_LSB 0
179 #define LCR_CLS_MASK 0x00000003
180 #define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB)
181 #define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK)
183 #define MCR_ADDRESS 0x00051010
184 #define MCR_OFFSET 0x00000010
185 #define MCR_LOOPBACK_MSB 5
186 #define MCR_LOOPBACK_LSB 5
187 #define MCR_LOOPBACK_MASK 0x00000020
188 #define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB)
189 #define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK)
190 #define MCR_OUT2_MSB 3
191 #define MCR_OUT2_LSB 3
192 #define MCR_OUT2_MASK 0x00000008
193 #define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB)
194 #define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK)
195 #define MCR_OUT1_MSB 2
196 #define MCR_OUT1_LSB 2
197 #define MCR_OUT1_MASK 0x00000004
198 #define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB)
199 #define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK)
200 #define MCR_RTS_MSB 1
201 #define MCR_RTS_LSB 1
202 #define MCR_RTS_MASK 0x00000002
203 #define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB)
204 #define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK)
205 #define MCR_DTR_MSB 0
206 #define MCR_DTR_LSB 0
207 #define MCR_DTR_MASK 0x00000001
208 #define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB)
209 #define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK)
211 #define LSR_ADDRESS 0x00051014
212 #define LSR_OFFSET 0x00000014
213 #define LSR_FERR_MSB 7
214 #define LSR_FERR_LSB 7
215 #define LSR_FERR_MASK 0x00000080
216 #define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB)
217 #define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK)
218 #define LSR_TEMT_MSB 6
219 #define LSR_TEMT_LSB 6
220 #define LSR_TEMT_MASK 0x00000040
221 #define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB)
222 #define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK)
223 #define LSR_THRE_MSB 5
224 #define LSR_THRE_LSB 5
225 #define LSR_THRE_MASK 0x00000020
226 #define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB)
227 #define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK)
230 #define LSR_BI_MASK 0x00000010
231 #define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB)
232 #define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK)
235 #define LSR_FE_MASK 0x00000008
236 #define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB)
237 #define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK)
240 #define LSR_PE_MASK 0x00000004
241 #define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB)
242 #define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK)
245 #define LSR_OE_MASK 0x00000002
246 #define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB)
247 #define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK)
250 #define LSR_DR_MASK 0x00000001
251 #define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB)
252 #define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK)
254 #define MSR_ADDRESS 0x00051018
255 #define MSR_OFFSET 0x00000018
256 #define MSR_DCD_MSB 7
257 #define MSR_DCD_LSB 7
258 #define MSR_DCD_MASK 0x00000080
259 #define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB)
260 #define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK)
263 #define MSR_RI_MASK 0x00000040
264 #define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB)
265 #define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK)
266 #define MSR_DSR_MSB 5
267 #define MSR_DSR_LSB 5
268 #define MSR_DSR_MASK 0x00000020
269 #define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB)
270 #define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK)
271 #define MSR_CTS_MSB 4
272 #define MSR_CTS_LSB 4
273 #define MSR_CTS_MASK 0x00000010
274 #define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB)
275 #define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK)
276 #define MSR_DDCD_MSB 3
277 #define MSR_DDCD_LSB 3
278 #define MSR_DDCD_MASK 0x00000008
279 #define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB)
280 #define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK)
281 #define MSR_TERI_MSB 2
282 #define MSR_TERI_LSB 2
283 #define MSR_TERI_MASK 0x00000004
284 #define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB)
285 #define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK)
286 #define MSR_DDSR_MSB 1
287 #define MSR_DDSR_LSB 1
288 #define MSR_DDSR_MASK 0x00000002
289 #define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB)
290 #define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK)
291 #define MSR_DCTS_MSB 0
292 #define MSR_DCTS_LSB 0
293 #define MSR_DCTS_MASK 0x00000001
294 #define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB)
295 #define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK)
298 /************************** config definition ***************************/
299 #define UART_FIFO_SIZE 512 //Must be 2^N
301 #define USE_POST_BUFFER 0 // ENABLE a tx buffer for post processing,
302 /*********************** data struction definition ************************/
303 // data struction definition
306 uint8_t buf[UART_FIFO_SIZE];
308 uint16_t start_index;
310 uint32_t overrun_err;
317 struct uart_api *_uart;
318 struct uart_fifo _tx;
321 /******** hardware API table structure (API descriptions below) *************/
323 uint32_t (*_uart_init)(void);
324 void (*_uart_char_put)(uint8_t ch);
325 uint16_t (*_uart_char_get)(uint8_t* ch);
326 void (*_uart_str_out)(uint8_t* str);
327 void (*_uart_task)(void);
328 uint32_t (*_uart_status)(void);
329 void (*_uart_config)(uint16_t flag);
330 void (*_uart_hwinit)(uint32_t freq, uint32_t baud);
333 #endif // end of _UART_API_H_