2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
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9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 /*************************************************************************/
36 /* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */
38 /* Module Name : rom_cfg.h */
41 /* This file contains definition of platform and sysmte config . */
46 /*************************************************************************/
51 /************************** FPGA version **************************/
52 #define MAGPIE_FPGA_RAM_256K 0
54 /************************** SYSTEM WIDE ***************************/
56 * D : Daily build (Development)
57 * R : Official Release
59 #define ATH_VER_RELEASE_CODE "D"
60 #define ATH_VER_PLATFORM_NUMBER "0"
61 #define ATH_VER_MAJOR_NUMBER "0"
62 #define ATH_VER_MINOR_NUMBER "0"
63 #define ATH_VER_BUILD_NUMBER "3"
65 #define ATH_VERSION_STR "["ATH_VER_RELEASE_CODE "." \
66 ATH_VER_PLATFORM_NUMBER "." \
67 ATH_VER_MAJOR_NUMBER "." \
68 ATH_VER_MINOR_NUMBER "." \
69 ATH_VER_BUILD_NUMBER "]"
71 /* ROM Code Version (16 bit)
72 * Bit 15 : 0 means ASIC, 1 means FPGA
73 * Bit 14 : 0 means ROM, 1 means FLASH
74 * Bit 13-8 : Major Version Number
75 * Bit 7-0 : Minor Version Number
78 #define ROM_PLATFORM (1)
80 #define ROM_PLATFORM (0)
83 #if defined(SFLASH_BOOT)
89 /* Define ROM Code Version Number here */
90 #define ROM_MAJOR_VER_NUM (1)
91 #define ROM_MINOR_VER_NUM (8)
93 #define BOOTROM_VER ( (ROM_PLATFORM<<15) | (ROM_TYPE<<14) | (ROM_MAJOR_VER_NUM<<8) | ROM_MINOR_VER_NUM )
97 #define SYSTEM_FREQ 10 // For FPGA, it is 10 MHz; For SoC, it is 40 MHz during ROM booting, and then change to 117 MHz during firmware execution
99 #define SYSTEM_FREQ 40 // For FPGA, it is 10 MHz; For SoC, it is 40 MHz during ROM booting, and then change to 117 MHz during firmware execution
102 #define SYSTEM_CLK SYSTEM_FREQ*1000*1000 //40mhz
104 #define ONE_MSEC (SYSTEM_FREQ*1000)
106 /////////////////////////////////////////////////////////////////
108 * Supported reference clock speeds.
110 * Note: MAC HAL code has multiple tables indexed by these values,
111 * so do not rearrange them. Add any new refclk values at the end.
114 SYS_CFG_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */
115 SYS_CFG_REFCLK_10_MHZ = 0,
116 SYS_CFG_REFCLK_20_MHZ = 1,
117 SYS_CFG_REFCLK_40_MHZ = 2,
120 /////////////////////////////////////////////////////////////////
123 /////////////////////////////////////////////////////////////////
126 #define SYSTEM_MODULE_MEM 1
128 #define SYSTEM_MODULE_MISC 1
130 #define SYSTEM_MODULE_USB 1
132 #if SYSTEM_MODULE_USB
133 #define SYSTEM_MODULE_HP_EP1 1
134 #define SYSTEM_MODULE_HP_EP5 1
135 #define SYSTEM_MODULE_HP_EP6 1
138 #define SYSTEM_MODULE_INTR 1
140 #define SYSTEM_MODULE_CLOCK 1
142 #define SYSTEM_MODULE_DESC 0
144 #define SYSTEM_MODULE_ALLOCRAM 1
146 #define SYSTEM_MODULE_UART 1 //uart module to dump the dbg message
148 #define SYSTEM_MODULE_TIMER 1 // a virtual timer, before we don't have the real timer
150 #define SYSTEM_MODULE_WDT 1 // a watchdog timer
152 #define SYSTEM_MODULE_EEPROM 1 // a eeprom interface (pcie_rc's eeprom not apb eeprom)
154 #define SYSTEM_MODULE_SFLASH 1 // a serial flash interface
156 #if SYSTEM_MODULE_UART
157 #define SYSTEM_MODULE_PRINT 1 // dependency on UART module
158 #define MOVE_PRINT_TO_RAM 1 // dependency on PRINT & UART module
159 #define SYSTEM_MODULE_DBG 1 // dependency on PRINT & UART module
160 #define MOVE_DBG_TO_RAM 1 // dependency on PRINT & UART module
163 #define SYSTEM_MODULE_ROM_PATCH 1 // patch install module
165 #define SYSTEM_MODULE_PCI 0
167 #define SYSTEM_MODULE_GMAC 0
169 #define SYSTEM_MODULE_TESTING 0 // backdoor test module
171 #if SYSTEM_MODULE_TESTING
172 #define SYSTEM_MODULE_MEMORY_TEST 0
173 #define SYSTEM_MODULE_DHRYSTONE_TEST 0
175 #define SYSTEM_MODULE_SYS_MONITOR 0
176 #define SYSTEM_MODULE_IDLE_TASK 0
178 #endif /* SYSTEM_MODULE_TESTING */
180 /****************************** UART ******************************/
181 #define UART_INPUT_CLK SYSTEM_CLK
182 #define UART_DEFAULT_BAUD 19200
183 #define UART_RETRY_COUNT 10000
185 /****************************** USB *******************************/
187 /* Firmware Loopback */
188 #define ZM_FM_LOOPBACK 0
189 #define ZM_SELF_TEST_MODE 1 // USB-IF Eye Pattern Test
191 #define ENABLE_SWAP_DATA_MODE 1 // byte swap function
192 #define ENABLE_SW_SWAP_DATA_MODE 1
194 #define ENABLE_STREAM_MODE 0 // stream mode
196 #define USB_STREAM_MODE_AGG_CNT 0 // 2 packets, 2: 3packets, 3: 4packets etc...
197 #define USB_STREAM_MODE_TIMEOUT_CTRL 0x0 // the unit is 32 USB (30Mhz) clock cycles
198 #define USB_STREAM_MODE_HOST_BUF_SZ (BIT4) // define the host dma buffer size (bit5,bit4)- 4096(0,0) 8192 (0,1) 16384(1,0) 32768(1,1) bytes
200 /************************* MEMORY DEFS ***************************/
202 #if defined(PROJECT_MAGPIE)
203 #include "magpie_mem.h"
204 #elif defined(PROJECT_K2)
209 // the end of 16 bytes are used to record some debug state and watchdog event and counter
210 #define WATCH_DOG_MAGIC_PATTERN_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x4) // 0x53fffc,magic pattern address
211 #define WATCH_DOG_RESET_COUNTER_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x8) // 0x53fff8,record the reset counter
212 #define DEBUG_SYSTEM_STATE_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0xc) // 0x53fff4,record the state of system
213 #define CURRENT_PROGRAM_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x10) // 0x53fff0,reserved
215 #define WATCH_DOG_MAGIC_PATTERN (*((volatile u32_t*)(WATCH_DOG_MAGIC_PATTERN_ADDR)))
216 #define WATCH_DOG_RESET_COUNTER (*((volatile u32_t*)(WATCH_DOG_RESET_COUNTER_ADDR)))
217 #define DEBUG_SYSTEM_STATE (*((volatile u32_t*)(DEBUG_SYSTEM_STATE_ADDR)))
218 #define CURRENT_PROGRAM (*((volatile u32_t*)(CURRENT_PROGRAM_ADDR)))
220 #define WDT_MAGIC_PATTERN 0x5F574454 //_WDT
221 #define SUS_MAGIC_PATTERN 0x5F535553 //_SUS
223 /****************************** WATCH DOG *******************************/
224 #define WDT_DEFAULT_TIMEOUT_VALUE 3*ONE_MSEC*1000 // Initial value is 3 seconds, firmware changes it to 65 milliseconds
226 #endif /* _ROM_CFG_H_ */