2 * xtensa/config/core-matmap.h -- Memory access and translation mapping
3 * parameters (CHAL) of the Xtensa processor core configuration.
5 * If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
6 * this file) for more details.
8 * In the Xtensa processor products released to date, all parameters
9 * defined in this file are derivable (at least in theory) from
10 * information contained in the core-isa.h header file.
11 * In particular, the following core configuration parameters are relevant:
12 * XCHAL_HAVE_CACHEATTR
13 * XCHAL_HAVE_MIMIC_CACHEATTR
14 * XCHAL_HAVE_XLT_CACHEATTR
16 * XCHAL_ITLB_ARF_ENTRIES_LOG2
17 * XCHAL_DTLB_ARF_ENTRIES_LOG2
18 * XCHAL_DCACHE_IS_WRITEBACK
19 * XCHAL_ICACHE_SIZE (presence of I-cache)
20 * XCHAL_DCACHE_SIZE (presence of D-cache)
21 * XCHAL_HW_VERSION_MAJOR
22 * XCHAL_HW_VERSION_MINOR
26 * Customer ID=4748; Build=0x2230f; Copyright (c) 1999-2008 by Tensilica Inc. ALL RIGHTS RESERVED.
27 * These coded instructions, statements, and computer programs are the
28 * copyrighted works and confidential proprietary information of Tensilica Inc.
29 * They may not be modified, copied, reproduced, distributed, or disclosed to
30 * third parties in any manner, medium, or form, in whole or in part, without
31 * the prior written consent of Tensilica Inc.
35 #ifndef XTENSA_CONFIG_CORE_MATMAP_H
36 #define XTENSA_CONFIG_CORE_MATMAP_H
39 /*----------------------------------------------------------------------
40 CACHE (MEMORY ACCESS) ATTRIBUTES
41 ----------------------------------------------------------------------*/
44 /* Cache Attribute encodings -- lists of access modes for each cache attribute: */
45 #define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
46 XTHAL_FAM_BYPASS XCHAL_SEP \
47 XTHAL_FAM_BYPASS XCHAL_SEP \
48 XTHAL_FAM_BYPASS XCHAL_SEP \
49 XTHAL_FAM_BYPASS XCHAL_SEP \
50 XTHAL_FAM_EXCEPTION XCHAL_SEP \
51 XTHAL_FAM_EXCEPTION XCHAL_SEP \
52 XTHAL_FAM_EXCEPTION XCHAL_SEP \
53 XTHAL_FAM_EXCEPTION XCHAL_SEP \
54 XTHAL_FAM_EXCEPTION XCHAL_SEP \
55 XTHAL_FAM_EXCEPTION XCHAL_SEP \
56 XTHAL_FAM_EXCEPTION XCHAL_SEP \
57 XTHAL_FAM_EXCEPTION XCHAL_SEP \
58 XTHAL_FAM_EXCEPTION XCHAL_SEP \
59 XTHAL_FAM_EXCEPTION XCHAL_SEP \
61 #define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \
62 XTHAL_LAM_BYPASSG XCHAL_SEP \
63 XTHAL_LAM_BYPASSG XCHAL_SEP \
64 XTHAL_LAM_EXCEPTION XCHAL_SEP \
65 XTHAL_LAM_BYPASSG XCHAL_SEP \
66 XTHAL_LAM_EXCEPTION XCHAL_SEP \
67 XTHAL_LAM_EXCEPTION XCHAL_SEP \
68 XTHAL_LAM_EXCEPTION XCHAL_SEP \
69 XTHAL_LAM_EXCEPTION XCHAL_SEP \
70 XTHAL_LAM_EXCEPTION XCHAL_SEP \
71 XTHAL_LAM_EXCEPTION XCHAL_SEP \
72 XTHAL_LAM_EXCEPTION XCHAL_SEP \
73 XTHAL_LAM_EXCEPTION XCHAL_SEP \
74 XTHAL_LAM_EXCEPTION XCHAL_SEP \
75 XTHAL_LAM_BYPASSG XCHAL_SEP \
77 #define XCHAL_SCA_LIST XTHAL_SAM_BYPASS XCHAL_SEP \
78 XTHAL_SAM_BYPASS XCHAL_SEP \
79 XTHAL_SAM_BYPASS XCHAL_SEP \
80 XTHAL_SAM_EXCEPTION XCHAL_SEP \
81 XTHAL_SAM_BYPASS XCHAL_SEP \
82 XTHAL_SAM_EXCEPTION XCHAL_SEP \
83 XTHAL_SAM_EXCEPTION XCHAL_SEP \
84 XTHAL_SAM_EXCEPTION XCHAL_SEP \
85 XTHAL_SAM_EXCEPTION XCHAL_SEP \
86 XTHAL_SAM_EXCEPTION XCHAL_SEP \
87 XTHAL_SAM_EXCEPTION XCHAL_SEP \
88 XTHAL_SAM_EXCEPTION XCHAL_SEP \
89 XTHAL_SAM_EXCEPTION XCHAL_SEP \
90 XTHAL_SAM_EXCEPTION XCHAL_SEP \
91 XTHAL_SAM_BYPASS XCHAL_SEP \
96 * Specific encoded cache attribute values of general interest.
97 * If a specific cache mode is not available, the closest available
98 * one is returned instead (eg. writethru instead of writeback,
99 * bypass instead of writethru).
101 #define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
102 #define XCHAL_CA_WRITETHRU 2 /* cache enabled (write-through) mode */
103 #define XCHAL_CA_WRITEBACK 2 /* cache enabled (write-back) mode */
104 #define XCHAL_CA_BYPASS_RW 0 /* cache disabled (bypassed) mode (no exec) */
105 #define XCHAL_CA_WRITETHRU_RW 0 /* cache enabled (write-through) mode (no exec) */
106 #define XCHAL_CA_WRITEBACK_RW 0 /* cache enabled (write-back) mode (no exec) */
107 #define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
108 #define XCHAL_CA_ISOLATE 0 /* cache isolate (accesses go to cache not memory) mode */
111 /*----------------------------------------------------------------------
113 ----------------------------------------------------------------------*/
116 * General notes on MMU parameters.
119 * ASID = address-space ID (acts as an "extension" of virtual addresses)
120 * VPN = virtual page number
121 * PPN = physical page number
122 * CA = encoded cache attribute (access modes)
123 * TLB = translation look-aside buffer (term is stretched somewhat here)
124 * I = instruction (fetch accesses)
125 * D = data (load and store accesses)
126 * way = each TLB (ITLB and DTLB) consists of a number of "ways"
127 * that simultaneously match the virtual address of an access;
128 * a TLB successfully translates a virtual address if exactly
129 * one way matches the vaddr; if none match, it is a miss;
130 * if multiple match, one gets a "multihit" exception;
131 * each way can be independently configured in terms of number of
132 * entries, page sizes, which fields are writable or constant, etc.
133 * set = group of contiguous ways with exactly identical parameters
134 * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
135 * from the page table and storing it in one of the auto-refill ways;
136 * if this PTE load also misses, a miss exception is posted for s/w.
137 * min-wired = a "min-wired" way can be used to map a single (minimum-sized)
138 * page arbitrarily under program control; it has a single entry,
139 * is non-auto-refill (some other way(s) must be auto-refill),
140 * all its fields (VPN, PPN, ASID, CA) are all writable, and it
141 * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
142 * restriction is that this be the only page size it supports).
144 * TLB way entries are virtually indexed.
145 * TLB ways that support multiple page sizes:
146 * - must have all writable VPN and PPN fields;
147 * - can only use one page size at any given time (eg. setup at startup),
148 * selected by the respective ITLBCFG or DTLBCFG special register,
149 * whose bits n*4+3 .. n*4 index the list of page sizes for way n
150 * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
151 * this list may be sparse for auto-refill ways because auto-refill
152 * ways have independent lists of supported page sizes sharing a
153 * common encoding with PTE entries; the encoding is the index into
154 * this list; unsupported sizes for a given way are zero in the list;
155 * selecting unsupported sizes results in undefined hardware behaviour;
156 * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
159 #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
160 #define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
161 #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
162 #define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
163 #define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */
164 #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */
167 /*** Instruction TLB: ***/
169 #define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
170 #define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
171 #define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
172 #define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */
174 /* Way set to which each way belongs: */
175 #define XCHAL_ITLB_WAY0_SET 0
177 /* Ways sets that are used by hardware auto-refill (ARF): */
178 #define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
180 /* Way sets that are "min-wired" (see terminology comment above): */
181 #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
184 /* ITLB way set 0 (group of ways 0 thru 0): */
185 #define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
186 #define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
187 #define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
188 #define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
189 #define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
190 #define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
191 #define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
192 #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
193 #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
194 #define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
195 2^PAGESZ_BITS entries in list, unsupported entries are zero */
196 #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
197 #define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
198 #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
199 #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
200 #define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
201 #define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
202 #define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
203 #define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
204 /* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */
205 #define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
206 #define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
207 #define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
208 #define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
209 #define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
210 #define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
211 #define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
212 #define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
213 /* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */
214 #define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000
215 #define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000
216 #define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000
217 #define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000
218 #define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000
219 #define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000
220 #define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000
221 #define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000
222 /* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */
223 #define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
224 #define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
225 #define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
226 #define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
227 #define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
228 #define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
229 #define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
230 #define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
235 #define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
236 #define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
237 #define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
238 #define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */
240 /* Way set to which each way belongs: */
241 #define XCHAL_DTLB_WAY0_SET 0
243 /* Ways sets that are used by hardware auto-refill (ARF): */
244 #define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
246 /* Way sets that are "min-wired" (see terminology comment above): */
247 #define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
250 /* DTLB way set 0 (group of ways 0 thru 0): */
251 #define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
252 #define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
253 #define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
254 #define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
255 #define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
256 #define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
257 #define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
258 #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
259 #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
260 #define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
261 2^PAGESZ_BITS entries in list, unsupported entries are zero */
262 #define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
263 #define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
264 #define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
265 #define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
266 #define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
267 #define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
268 #define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
269 #define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
270 /* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */
271 #define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
272 #define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
273 #define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
274 #define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
275 #define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
276 #define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
277 #define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
278 #define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
279 /* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */
280 #define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000
281 #define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000
282 #define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000
283 #define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000
284 #define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000
285 #define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000
286 #define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000
287 #define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000
288 /* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */
289 #define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
290 #define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
291 #define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
292 #define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
293 #define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
294 #define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
295 #define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
296 #define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
301 #endif /*XTENSA_CONFIG_CORE_MATMAP_H*/