1 ;;; -*- Mode: Midas -*-
2 ;;; Copyright (c) 1999 Massachusetts Institute of Technology
4 ;;; This program is free software; you can redistribute it and/or
5 ;;; modify it under the terms of the GNU General Public License as
6 ;;; published by the Free Software Foundation; either version 2 of the
7 ;;; License, or (at your option) any later version.
9 ;;; This program is distributed in the hope that it will be useful,
10 ;;; but WITHOUT ANY WARRANTY; without even the implied warranty of
11 ;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 ;;; General Public License for more details.
14 ;;; You should have received a copy of the GNU General Public License
15 ;;; along with this program; if not, write to the Free Software
16 ;;; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 ;;; Canonical symbol definition macro, FOO==BAR with error check.
27 IFN Z-$$TEM1,.ERR Z MULTIPLY .QUOTE`.QUOTE/DEFINED/`
35 ; The ACC IMP interface on the KS implements two separate Unibus IO
36 ; devices, for input and output. Both of these devices transfer data in
37 ; 32-bit mode only over the Unibus via DMA. Because of the DMA data
38 ; transfer the interrupt structure is trivial, and uses NETCHN only.
40 ; Apparently the reset bits in the two CSRs are wired together, so
41 ; resetting one side of the machine resets both. This action also drops
42 ; the HOST READY line to the IMP.
44 ; You must set %LHSE whenever hte HOST READY line is high, or the IMP
45 ; will be allowed to freely throw away data. This is true across IMP
46 ; message boundaries, and even if no input request is active.
49 ;ACC LH-DH IMP Interface Bits
51 ;Interrupt information
52 DEFSYM %LHVEC==250 ;Input side interrupt vector (non-standard)
53 ;Output side assumed to be %LHVEC+4
54 DEFSYM %LHPRI==6 ;Interrupt priority (non-standard)
56 DEFSYM %LHBAS==767600 ;Base of LH/DH Unibus register address space
59 DEFSYM %LHICS==%LHBAS ;Control and Status, Input side
60 DEFSYM %LHIDB==%LHBAS+2 ;Data Buffer, Input
61 DEFSYM %LHICA==%LHBAS+4 ;Current Word Address, Input
62 DEFSYM %LHIWC==%LHBAS+6 ;Word Count, Input
64 DEFSYM %LHOCS==%LHBAS+10 ;Control and Status, Output side
65 DEFSYM %LHODB==%LHBAS+12 ;Data Buffer, Output
66 DEFSYM %LHOCA==%LHBAS+14 ;Current Word Address, Output
67 DEFSYM %LHOWC==%LHBAS+16 ;Word Count, Output
70 ; Bits common to input and output
71 DEFSYM %LHERR==1_15. ;Error present
72 DEFSYM %LHNXM==1_14. ;Non Existant Memory on DMA
73 DEFSYM %LHMRE==1_9. ;Master Ready Error (ready bounce during xfr)
74 DEFSYM %LHRDY==1_7. ;Device Ready (modifying LHDH regs allowed)
75 DEFSYM %LHIE==1_6. ;Interrupt Enable
76 DEFSYM %LHA17==1_5. ;Address bit 17 for extended unibus xfrs
77 DEFSYM %LHA16==1_4. ;Address bit 16 for extended unibus xfrs
78 DEFSYM %LHRST==1_1. ;Interface Reset
79 DEFSYM %LHGO==1 ;GO - Start DMA Transfer
82 DEFSYM %LHEOM==1_13. ;End-of-Message received from IMP
83 DEFSYM %LHHR==1_11. ;Host Ready (ACC's relay closed, debounced)
84 DEFSYM %LHINR==1_10. ;IMP not ready
85 DEFSYM %LHIBF==1_8. ;Input Buffer Full
86 DEFSYM %LHSE==1_3. ;Store Enable (0 == flush data instead)
87 DEFSYM %LHHRC==1_2. ;Host Ready Relay Control (1 to close relay)
90 DEFSYM %LHWC0==1_13. ;Output Word Count is zero
91 DEFSYM %LHOBE==1_8. ;Output Buffer Empty
92 DEFSYM %LHBB==1_3. ;Bus Back (loopback enable for testing)
93 DEFSYM %LHELB==1_2. ;Send EOM indication to IMP at end of xfr
94 ; (enable Last Bit Flag)
95 IFN $$TEMP,EXPUNG DEFSYM