1 Copyright (c) 1999 Massachusetts Institute of Technology
3 This program is free software; you can redistribute it and/or modify
4 it under the terms of the GNU General Public License as published by
5 the Free Software Foundation; either version 2 of the License, or (at
6 your option) any later version.
8 This program is distributed in the hope that it will be useful, but
9 WITHOUT ANY WARRANTY; without even the implied warranty of
10 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 General Public License for more details.
13 You should have received a copy of the GNU General Public License
14 along with this program; if not, write to the Free Software
15 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
16 ------------------------------
20 This file attempts to maintain up-to-date documentation on
21 ITS interrupts. Those wonderful
22 souls who update the information in any way (additions,
23 deletions, corrections) should describe their
24 modifications in a brief note to INFO-ITS@AI so
25 that interested parties can correct their copies or
26 conceptions without needing to print or read the
27 entire file again. For example:
29 :QMAIL INFO-ITS@AI I added more details to the %PIJST interrupt ^C
31 If you want to be put on the INFO-ITS mailing list,
32 just say so in a message to it.
33 -------------------------------------------------
35 <Most of ITS INTRUP is not here...>
37 FIRST The Interrupt Bits in the First Interrupt Word.
39 The interrupt classes are:
40 [1] stops job and interrupts superior (fatal intr)
41 [2] stops job and interrupts superior unless enabled and undeferred
42 [3] does nothing unless enabled; waits if deferred.
44 Bits in the left half have two names: %PI... as a bit in the word,
45 and %PJ... shifted down by 18. bits.
47 The following interrupts abort the instruction, and leave the PC pointing
48 before the instruction if %OPOPC is 1 (as is winning), or after it if
49 %OPOPC is 0: %PIMPV, %PIOOB, %PIIOC, %PIILO, %PITTY, %PIWRO, %PIFET, %PITRP.
51 "(S)" indicates a synchronous interrupt; "(A)", an asynchronous one.
52 An interrupt is synchronous if its occurrence is always directly related
53 to the instruction that is being executed when it is signaled.
55 SECOND The Interrupt Bits in the Second Interrupt Word.
57 The right half of the second word (.IFPIR) is used for I/O channel
58 interrupts that signal the arrival of or need for data.
59 They should not be confused with I/O channel error interrupts
60 or IOCERRors. Each channel has its own bit: 1.1 is for channel
61 0; 1.2, for channel 1; ... 2.7, for channel 17 .
62 They are all class 3, and their significance depends on the device
65 The left half of the second word (.IFPIR) is used for
66 "inferior got a fatal interrupt" interrupts. Each of a job's
67 inferiors is assigned its own interrupt bit from among the
68 bottom 8 bits of the left half. When an inferior job is created,
69 its interrupt bit should be read and remembered by reading the
70 .INTB variable with a .USET. Every time that inferior gets a fatal
71 interrupt, it will be stopped and the superior will receive an
72 interrupt on that inferior's bit in .IFPIR. The inferior may
73 be restarted by zeroing its .USTP variable, but if the fatal
74 interrupts remain and are still fatal the inferior will simply
75 stop and interrupt the superior again. "Inferior got a fatal
76 interrupt" interrupts are all class 3.
78 The reason that inferiors interrupt through a special set of bits
79 instead of using I/O channel interrupts is that it makes it possible
80 to receive interrupts from all one's inferiors without having them
81 all open on I/O channels at all times. DDT normally keeps only
82 its current job open, and when it receives an interrupt from some
83 other job it opens that job temporarily.
85 STACK The format of the new-style interrupt stack
87 -----------------------------------
88 | 1st word interrupt bits |
89 -----------------------------------
90 | 2nd word interrupt bits |
91 -----------------------------------
93 -----------------------------------
95 -----------------------------------
96 | Saved program counter |
97 -----------------------------------
99 | Saved accumulators, if any |
101 -----------------------------------
102 | Saved .JPC, if requested |
103 -----------------------------------
104 | Saved .SUUOH, if requested |
105 -----------------------------------
106 Top -> | Saved LSPCL, if requested |
107 -----------------------------------
109 %PI1PR Single-instruction proceed [1] (S)
111 If a job is started with the one-proceed flag
112 (%PC1PR on KA-10's) set, after one instruction
113 is completed a %PI1PR interrupt will occur.
114 DDT's ^N command uses this feature.
116 %PIARO Arithmetic overflow [3] (S)
118 The PDP-10's built-in arithmetic overflow
119 condition was detected by the hardware.
120 In fact, overflow occurs so often
121 that enabling this interrupt causes the
122 machine to slow down considerably,
123 and it should be avoided.
125 %PIATY TTY returned. [3] (A)
127 This interrupt happens when the TTY is
128 returned by the superior, after having
129 been taken away. TECO uses this to know
130 that it must redisplay the entire screen.
132 %PIB42 BADPI (Bad location 42) [1] (S)
134 If in attempting to interrupt a job it turns out
135 to be necessary to refer to nonexistent memory
136 or write in read-only memory, this interrupt
137 is signaled, instead of MPV or WIRO.
138 This is so that the program will return to DDT
139 instead of mysteriously looping.
141 %PIBRK .BREAK instruction executed. [1] (S)
143 .BREAK is used for DDT breakpoints, and for explicit
144 program requests to DDT.
146 %PIC.Z ^Z or CALL typed on terminal [1] (A)
148 %PICLI CLI interrupt [3] (A)
150 Some job opened the CLI device with filenames equal
151 to the uname and jname of this job.
153 %PICLK Slow (1/2 sec) clock [3] (A)
155 %PIDBG System being debugged state change [3] (A)
157 When the system enters or leaves "debugging mode",
158 this interrupt is signaled.
160 %PIDCL Deferred call. [1] (S)
162 An attempt was made to read TTY input
163 and the next character was a deferred-call
164 character (^_D or Control-CALL).
165 This deferred-call character is never seen
166 by the program; it just causes the interrupt.
167 It differs from ordinary CALL or ^Z
168 in that it takes effect when the program
169 gets around to reading it, not immediately.
171 %PIDIS Display memory protect [2] (A)
173 The 340 or E&S display got an MPV.
174 This is now obsolete since the 340 and E&S
177 %PIDWN System-going-down status change [3] (A)
179 If the system changes its mind about whether
180 or when it is scheduled to go down, this interrupt
183 %PIFET Fetched insn from impure page [2] (S)
185 On KA-10's, if bit %PCPUR of the PC flags is 1,
186 fetching an instruction from an impure page
187 will cause this interrupt. This is supposed to
188 facilitate catching jumps to randomness.
189 The guilty instruction is aborted, and the PC is
190 left set according to %OPOPC.
192 %PIFOV ARFOV (Floating overflow) [3] (S)
194 This is a non-aborting PDP-10 hardware condition.
196 %PIILO ILOPR, ILUUO (illegal operation) [2] (S)
198 This can be caused by a returnable uuo when the
199 program's 41 doesn't seem suitable for handling one
200 (see ITS UUOS). It can also be used to report
201 the failure of certain more archaic system calls.
202 The guilty instruction was aborted, and the PC was
203 left set according to %OPOPC.
205 %PIIOC IOCERR (I/O channel error) [2] (S)
207 This indicates the failure of an I/O system
208 call. The channel that was being operated on is
209 in .BCHN, and its .IOS word should contain, in
210 bits 4.5 - 4.1, an error code.
211 The guilty instruction was aborted, and the PC was
212 left set according to %OPOPC.
214 %PIJST Job Status display request. [3] (A)
216 The sequence ^_J was typed on the
217 console owned by this process or some inferior.
219 %PILOS Lossage signaled. [2] (S)
221 A .LOSE UUO or a LOSE system call was executed.
223 %PILTP 340 or E&S light pen hit [3] (A)
225 %PIMAR MAR hit. [2] (S)
227 The MAR is a hardware feature that allows
228 references to a specific memory location to
229 be trapped. This is the interrupt that happens
230 when such a reference is detected. The guilty
231 instuction is usually not aborted; if it is, the
232 PC is SOS'ed regardless of the setting of %OPOPC.
233 See the .MARA and .MARPC variables.
235 %PIMPV MPV (memory protect violation) [2] (S)
237 The job referenced a non-existent memory location.
238 The address of that location (roundd down to
239 a page boundary on KA-10's) may be found in .MPVA.
240 The guilty instruction was aborted, and the PC was
241 left set according to %OPOPC.
243 %PINXI Non-existent IO register [2] (S)
245 A Job in User IOT mode referenced a non-existent IO
246 register on the KS10 Unibus. The PC is left pointing
247 before the guilty instruction. The address of the
248 non-existant register may be found in .MPVA.
250 %PIOOB Address out of bounds [2] (S)
252 This is an obscure condition that used to
253 happen on USR device IOT's, when an attempt
254 was made to refer to a nonexistent location in the
255 other job. Now this always causes an MPV.
256 The guilty instruction was aborted, and the PC was
257 left set according to %OPOPC.
259 %PIPAR Memory parity error [2] (A)
261 Programs are not intended to try to recover
262 from parity errors, on the assumption that they
263 are probably permanently screwed up.
264 This interrupt is asynchronous because it can
265 be caused by a parity error in another job
266 which destroys data in a page shared with this job.
268 %PIPDL PDL overflow [3] (S)
270 %PIRLT Real-time timer went off [3] (A)
272 These interrupts are controlled by the .REALT
275 %PIRUN Run-time timer went off [3] (A)
277 This interrupt is requested (in advance)
280 %PITRP SYSUUO (System uuo in trap mode) [1] (S)
282 A job whose .UTRAP variable was nonzero either
283 attempted to execute an instruction that trapped
284 to the system, or was about to be interrupted.
285 This feature is intended to be used by the superior
286 to provide a non-ITS environment for the inferior.
287 The guilty instruction was aborted, and the PC was
288 left set according to %OPOPC.
290 %PITTY Don't have TTY [2] (S)
292 This results from an attempt to use the job's
293 console tty when the job does not own it, if
294 %TBINT is 1 and %TBWAT is 0. See ITS TTY.
295 The guilty instruction is aborted, and the PC is
296 left set according to %OPOPC.
298 %PITYI TTY input (obsolete) [3] (A)
300 %PIVAL .VALUE instruction executed [1] (S)
302 %PIWRO WIRO (Write in read-only page) [2] (S)
304 The guilty instruction was aborted, and the PC was
305 left set according to %OPOPC. The address of read
306 only location (rounded down to a page boundary on
307 KA-10's) may be found in .MPVA.