2 * HD audio interface patch for Creative CA0132 chip
4 * Copyright (c) 2011, Creative Technology Ltd.
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/mutex.h>
28 #include <linux/module.h>
29 #include <linux/firmware.h>
30 #include <sound/core.h>
31 #include "hda_codec.h"
32 #include "hda_local.h"
33 #include "hda_auto_parser.h"
36 #include "ca0132_regs.h"
38 /* Enable this to see controls for tuning purpose. */
39 /*#define ENABLE_TUNING_CONTROLS*/
41 #ifdef ENABLE_TUNING_CONTROLS
42 #include <sound/tlv.h>
45 #define FLOAT_ZERO 0x00000000
46 #define FLOAT_ONE 0x3f800000
47 #define FLOAT_TWO 0x40000000
48 #define FLOAT_MINUS_5 0xc0a00000
50 #define UNSOL_TAG_DSP 0x16
52 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
53 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
55 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
56 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
57 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
59 #define MASTERCONTROL 0x80
60 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
61 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
63 #define WIDGET_CHIP_CTRL 0x15
64 #define WIDGET_DSP_CTRL 0x16
66 #define MEM_CONNID_MICIN1 3
67 #define MEM_CONNID_MICIN2 5
68 #define MEM_CONNID_MICOUT1 12
69 #define MEM_CONNID_MICOUT2 14
70 #define MEM_CONNID_WUH 10
71 #define MEM_CONNID_DSP 16
72 #define MEM_CONNID_DMIC 100
77 #define EFX_FILE "/*(DEBLOBBED)*/"
79 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
83 static char *dirstr[2] = { "Playback", "Capture" };
96 #define VNODE_START_NID 0x80
97 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
104 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
106 #define EFFECT_START_NID 0x90
107 #define OUT_EFFECT_START_NID EFFECT_START_NID
108 SURROUND = OUT_EFFECT_START_NID,
115 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
117 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
118 ECHO_CANCELLATION = IN_EFFECT_START_NID,
123 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
125 VOICEFX = IN_EFFECT_END_NID,
129 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
132 /* Effects values size*/
133 #define EFFECT_VALS_MAX_COUNT 12
135 /* Latency introduced by DSP blocks in milliseconds. */
136 #define DSP_CAPTURE_INIT_LATENCY 0
137 #define DSP_CRYSTAL_VOICE_LATENCY 124
138 #define DSP_PLAYBACK_INIT_LATENCY 13
139 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
140 #define DSP_SPEAKER_OUT_LATENCY 7
143 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
145 int mid; /*effect module ID*/
146 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
147 int direct; /* 0:output; 1:input*/
148 int params; /* number of default non-on/off params */
149 /*effect default values, 1st is on/off. */
150 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
153 #define EFX_DIR_OUT 0
156 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
157 { .name = "Surround",
161 .direct = EFX_DIR_OUT,
163 .def_vals = {0x3F800000, 0x3F2B851F}
165 { .name = "Crystalizer",
169 .direct = EFX_DIR_OUT,
171 .def_vals = {0x3F800000, 0x3F266666}
173 { .name = "Dialog Plus",
177 .direct = EFX_DIR_OUT,
179 .def_vals = {0x00000000, 0x3F000000}
181 { .name = "Smart Volume",
185 .direct = EFX_DIR_OUT,
187 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
192 .reqs = {24, 23, 25},
193 .direct = EFX_DIR_OUT,
195 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
197 { .name = "Equalizer",
200 .reqs = {9, 10, 11, 12, 13, 14,
201 15, 16, 17, 18, 19, 20},
202 .direct = EFX_DIR_OUT,
204 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
205 0x00000000, 0x00000000, 0x00000000, 0x00000000,
206 0x00000000, 0x00000000, 0x00000000, 0x00000000}
208 { .name = "Echo Cancellation",
209 .nid = ECHO_CANCELLATION,
211 .reqs = {0, 1, 2, 3},
212 .direct = EFX_DIR_IN,
214 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
216 { .name = "Voice Focus",
219 .reqs = {6, 7, 8, 9},
220 .direct = EFX_DIR_IN,
222 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
228 .direct = EFX_DIR_IN,
230 .def_vals = {0x00000000, 0x3F3D70A4}
232 { .name = "Noise Reduction",
233 .nid = NOISE_REDUCTION,
236 .direct = EFX_DIR_IN,
238 .def_vals = {0x3F800000, 0x3F000000}
243 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
244 .direct = EFX_DIR_IN,
246 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
247 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
252 /* Tuning controls */
253 #ifdef ENABLE_TUNING_CONTROLS
256 #define TUNING_CTL_START_NID 0xC0
257 WEDGE_ANGLE = TUNING_CTL_START_NID,
270 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
273 struct ct_tuning_ctl {
274 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
275 hda_nid_t parent_nid;
277 int mid; /*effect module ID*/
278 int req; /*effect module request*/
279 int direct; /* 0:output; 1:input*/
280 unsigned int def_val;/*effect default values*/
283 static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
284 { .name = "Wedge Angle",
285 .parent_nid = VOICE_FOCUS,
289 .direct = EFX_DIR_IN,
290 .def_val = 0x41F00000
292 { .name = "SVM Level",
293 .parent_nid = MIC_SVM,
297 .direct = EFX_DIR_IN,
298 .def_val = 0x3F3D70A4
300 { .name = "EQ Band0",
301 .parent_nid = EQUALIZER,
302 .nid = EQUALIZER_BAND_0,
305 .direct = EFX_DIR_OUT,
306 .def_val = 0x00000000
308 { .name = "EQ Band1",
309 .parent_nid = EQUALIZER,
310 .nid = EQUALIZER_BAND_1,
313 .direct = EFX_DIR_OUT,
314 .def_val = 0x00000000
316 { .name = "EQ Band2",
317 .parent_nid = EQUALIZER,
318 .nid = EQUALIZER_BAND_2,
321 .direct = EFX_DIR_OUT,
322 .def_val = 0x00000000
324 { .name = "EQ Band3",
325 .parent_nid = EQUALIZER,
326 .nid = EQUALIZER_BAND_3,
329 .direct = EFX_DIR_OUT,
330 .def_val = 0x00000000
332 { .name = "EQ Band4",
333 .parent_nid = EQUALIZER,
334 .nid = EQUALIZER_BAND_4,
337 .direct = EFX_DIR_OUT,
338 .def_val = 0x00000000
340 { .name = "EQ Band5",
341 .parent_nid = EQUALIZER,
342 .nid = EQUALIZER_BAND_5,
345 .direct = EFX_DIR_OUT,
346 .def_val = 0x00000000
348 { .name = "EQ Band6",
349 .parent_nid = EQUALIZER,
350 .nid = EQUALIZER_BAND_6,
353 .direct = EFX_DIR_OUT,
354 .def_val = 0x00000000
356 { .name = "EQ Band7",
357 .parent_nid = EQUALIZER,
358 .nid = EQUALIZER_BAND_7,
361 .direct = EFX_DIR_OUT,
362 .def_val = 0x00000000
364 { .name = "EQ Band8",
365 .parent_nid = EQUALIZER,
366 .nid = EQUALIZER_BAND_8,
369 .direct = EFX_DIR_OUT,
370 .def_val = 0x00000000
372 { .name = "EQ Band9",
373 .parent_nid = EQUALIZER,
374 .nid = EQUALIZER_BAND_9,
377 .direct = EFX_DIR_OUT,
378 .def_val = 0x00000000
383 /* Voice FX Presets */
384 #define VOICEFX_MAX_PARAM_COUNT 9
390 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
393 struct ct_voicefx_preset {
394 char *name; /*preset name*/
395 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
398 static struct ct_voicefx ca0132_voicefx = {
399 .name = "VoiceFX Capture Switch",
402 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
405 static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
407 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
408 0x44FA0000, 0x3F800000, 0x3F800000,
409 0x3F800000, 0x00000000, 0x00000000 }
411 { .name = "Female2Male",
412 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
413 0x44FA0000, 0x3F19999A, 0x3F866666,
414 0x3F800000, 0x00000000, 0x00000000 }
416 { .name = "Male2Female",
417 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
418 0x450AC000, 0x4017AE14, 0x3F6B851F,
419 0x3F800000, 0x00000000, 0x00000000 }
421 { .name = "ScrappyKid",
422 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
423 0x44FA0000, 0x40400000, 0x3F28F5C3,
424 0x3F800000, 0x00000000, 0x00000000 }
427 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
428 0x44E10000, 0x3FB33333, 0x3FB9999A,
429 0x3F800000, 0x3E3A2E43, 0x00000000 }
432 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
433 0x45098000, 0x3F266666, 0x3FC00000,
434 0x3F800000, 0x00000000, 0x00000000 }
437 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
438 0x45193000, 0x3F8E147B, 0x3F75C28F,
439 0x3F800000, 0x00000000, 0x00000000 }
442 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
443 0x45007000, 0x3F451EB8, 0x3F7851EC,
444 0x3F800000, 0x00000000, 0x00000000 }
446 { .name = "AlienBrute",
447 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
448 0x451F6000, 0x3F266666, 0x3FA7D945,
449 0x3F800000, 0x3CF5C28F, 0x00000000 }
452 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
453 0x44FA0000, 0x3FB2718B, 0x3F800000,
454 0xBC07010E, 0x00000000, 0x00000000 }
457 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
458 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
459 0x3F0A3D71, 0x00000000, 0x00000000 }
462 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
463 0x44FA0000, 0x3F800000, 0x3F800000,
464 0x3E4CCCCD, 0x00000000, 0x00000000 }
466 { .name = "DeepVoice",
467 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
468 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
469 0x3F800000, 0x00000000, 0x00000000 }
471 { .name = "Munchkin",
472 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
473 0x44FA0000, 0x3F800000, 0x3F1A043C,
474 0x3F800000, 0x00000000, 0x00000000 }
478 enum hda_cmd_vendor_io {
480 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
481 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
483 VENDOR_DSPIO_STATUS = 0xF01,
484 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
485 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
486 VENDOR_DSPIO_DSP_INIT = 0x703,
487 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
488 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
490 /* for ChipIO node */
491 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
492 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
493 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
494 VENDOR_CHIPIO_DATA_LOW = 0x300,
495 VENDOR_CHIPIO_DATA_HIGH = 0x400,
497 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
498 VENDOR_CHIPIO_STATUS = 0xF01,
499 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
500 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
502 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
503 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
505 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
506 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
508 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
509 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
510 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
511 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
512 VENDOR_CHIPIO_FLAG_SET = 0x70F,
513 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
514 VENDOR_CHIPIO_PARAM_SET = 0x710,
515 VENDOR_CHIPIO_PARAM_GET = 0xF10,
517 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
518 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
519 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
520 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
522 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
523 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
524 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
525 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
527 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
528 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
529 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
530 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
531 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
532 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
534 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
540 enum control_flag_id {
541 /* Connection manager stream setup is bypassed/enabled */
542 CONTROL_FLAG_C_MGR = 0,
543 /* DSP DMA is bypassed/enabled */
544 CONTROL_FLAG_DMA = 1,
545 /* 8051 'idle' mode is disabled/enabled */
546 CONTROL_FLAG_IDLE_ENABLE = 2,
547 /* Tracker for the SPDIF-in path is bypassed/enabled */
548 CONTROL_FLAG_TRACKER = 3,
549 /* DigitalOut to Spdif2Out connection is disabled/enabled */
550 CONTROL_FLAG_SPDIF2OUT = 4,
551 /* Digital Microphone is disabled/enabled */
552 CONTROL_FLAG_DMIC = 5,
553 /* ADC_B rate is 48 kHz/96 kHz */
554 CONTROL_FLAG_ADC_B_96KHZ = 6,
555 /* ADC_C rate is 48 kHz/96 kHz */
556 CONTROL_FLAG_ADC_C_96KHZ = 7,
557 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
558 CONTROL_FLAG_DAC_96KHZ = 8,
559 /* DSP rate is 48 kHz/96 kHz */
560 CONTROL_FLAG_DSP_96KHZ = 9,
561 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
562 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
563 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
564 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
565 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
566 CONTROL_FLAG_DECODE_LOOP = 12,
567 /* De-emphasis filter on DAC-1 disabled/enabled */
568 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
569 /* De-emphasis filter on DAC-2 disabled/enabled */
570 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
571 /* De-emphasis filter on DAC-3 disabled/enabled */
572 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
573 /* High-pass filter on ADC_B disabled/enabled */
574 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
575 /* High-pass filter on ADC_C disabled/enabled */
576 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
577 /* Common mode on Port_A disabled/enabled */
578 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
579 /* Common mode on Port_D disabled/enabled */
580 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
581 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
582 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
583 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
584 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
585 /* ASI rate is 48kHz/96kHz */
586 CONTROL_FLAG_ASI_96KHZ = 22,
587 /* DAC power settings able to control attached ports no/yes */
588 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
589 /* Clock Stop OK reporting is disabled/enabled */
590 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
591 /* Number of control flags */
592 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
596 * Control parameter IDs
598 enum control_param_id {
599 /* 0: None, 1: Mic1In*/
600 CONTROL_PARAM_VIP_SOURCE = 1,
601 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
602 CONTROL_PARAM_SPDIF1_SOURCE = 2,
603 /* Port A output stage gain setting to use when 16 Ohm output
604 * impedance is selected*/
605 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
606 /* Port D output stage gain setting to use when 16 Ohm output
607 * impedance is selected*/
608 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
612 /* Select stream with the given ID */
613 CONTROL_PARAM_STREAM_ID = 24,
614 /* Source connection point for the selected stream */
615 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
616 /* Destination connection point for the selected stream */
617 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
618 /* Number of audio channels in the selected stream */
619 CONTROL_PARAM_STREAMS_CHANNELS = 27,
620 /*Enable control for the selected stream */
621 CONTROL_PARAM_STREAM_CONTROL = 28,
623 /* Connection Point Control */
625 /* Select connection point with the given ID */
626 CONTROL_PARAM_CONN_POINT_ID = 29,
627 /* Connection point sample rate */
628 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
632 /* Select HDA node with the given ID */
633 CONTROL_PARAM_NODE_ID = 31
637 * Dsp Io Status codes
639 enum hda_vendor_status_dspio {
641 VENDOR_STATUS_DSPIO_OK = 0x00,
642 /* Busy, unable to accept new command, the host must retry */
643 VENDOR_STATUS_DSPIO_BUSY = 0x01,
644 /* SCP command queue is full */
645 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
646 /* SCP response queue is empty */
647 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
651 * Chip Io Status codes
653 enum hda_vendor_status_chipio {
655 VENDOR_STATUS_CHIPIO_OK = 0x00,
656 /* Busy, unable to accept new command, the host must retry */
657 VENDOR_STATUS_CHIPIO_BUSY = 0x01
663 enum ca0132_sample_rate {
683 SR_RATE_UNKNOWN = 0x1F
686 enum dsp_download_state {
687 DSP_DOWNLOAD_FAILED = -1,
688 DSP_DOWNLOAD_INIT = 0,
693 /* retrieve parameters from hda format */
694 #define get_hdafmt_chs(fmt) (fmt & 0xf)
695 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
696 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
697 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
704 struct snd_kcontrol_new *mixers[5];
705 unsigned int num_mixers;
706 const struct hda_verb *base_init_verbs;
707 const struct hda_verb *base_exit_verbs;
708 const struct hda_verb *chip_init_verbs;
709 struct hda_verb *spec_init_verbs;
710 struct auto_pin_cfg autocfg;
712 /* Nodes configurations */
713 struct hda_multi_out multiout;
714 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
715 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
716 unsigned int num_outputs;
717 hda_nid_t input_pins[AUTO_PIN_LAST];
718 hda_nid_t adcs[AUTO_PIN_LAST];
721 unsigned int num_inputs;
722 hda_nid_t shared_mic_nid;
723 hda_nid_t shared_out_nid;
724 hda_nid_t unsol_tag_hp;
725 hda_nid_t unsol_tag_amic1;
728 struct mutex chipio_mutex; /* chip access mutex */
731 /* DSP download related */
732 enum dsp_download_state dsp_state;
733 unsigned int dsp_stream_id;
734 unsigned int wait_scp;
735 unsigned int wait_scp_header;
736 unsigned int wait_num_data;
737 unsigned int scp_resp_header;
738 unsigned int scp_resp_data[4];
739 unsigned int scp_resp_count;
741 /* mixer and effects related */
742 unsigned char dmic_ctl;
745 long vnode_lvol[VNODES_COUNT];
746 long vnode_rvol[VNODES_COUNT];
747 long vnode_lswitch[VNODES_COUNT];
748 long vnode_rswitch[VNODES_COUNT];
749 long effects_switch[EFFECTS_COUNT];
753 struct hda_codec *codec;
754 struct delayed_work unsol_hp_work;
757 #ifdef ENABLE_TUNING_CONTROLS
758 long cur_ctl_vals[TUNING_CTLS_COUNT];
763 * CA0132 quirks table
770 static const struct hda_pintbl alienware_pincfgs[] = {
771 { 0x0b, 0x90170110 }, /* Builtin Speaker */
772 { 0x0c, 0x411111f0 }, /* N/A */
773 { 0x0d, 0x411111f0 }, /* N/A */
774 { 0x0e, 0x411111f0 }, /* N/A */
775 { 0x0f, 0x0321101f }, /* HP */
776 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
777 { 0x11, 0x03a11021 }, /* Mic */
778 { 0x12, 0xd5a30140 }, /* Builtin Mic */
779 { 0x13, 0x411111f0 }, /* N/A */
780 { 0x18, 0x411111f0 }, /* N/A */
784 static const struct snd_pci_quirk ca0132_quirks[] = {
785 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
786 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
787 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
792 * CA0132 codec access
794 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
795 unsigned int verb, unsigned int parm, unsigned int *res)
797 unsigned int response;
798 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
801 return ((response == -1) ? -1 : 0);
804 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
805 unsigned short converter_format, unsigned int *res)
807 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
808 converter_format & 0xffff, res);
811 static int codec_set_converter_stream_channel(struct hda_codec *codec,
812 hda_nid_t nid, unsigned char stream,
813 unsigned char channel, unsigned int *res)
815 unsigned char converter_stream_channel = 0;
817 converter_stream_channel = (stream << 4) | (channel & 0x0f);
818 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
819 converter_stream_channel, res);
822 /* Chip access helper function */
823 static int chipio_send(struct hda_codec *codec,
828 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
830 /* send bits of data specified by reg */
832 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
834 if (res == VENDOR_STATUS_CHIPIO_OK)
837 } while (time_before(jiffies, timeout));
843 * Write chip address through the vendor widget -- NOT protected by the Mutex!
845 static int chipio_write_address(struct hda_codec *codec,
846 unsigned int chip_addx)
848 struct ca0132_spec *spec = codec->spec;
851 if (spec->curr_chip_addx == chip_addx)
854 /* send low 16 bits of the address */
855 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
859 /* send high 16 bits of the address */
860 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
864 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
870 * Write data through the vendor widget -- NOT protected by the Mutex!
872 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
874 struct ca0132_spec *spec = codec->spec;
877 /* send low 16 bits of the data */
878 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
881 /* send high 16 bits of the data */
882 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
886 /*If no error encountered, automatically increment the address
887 as per chip behaviour*/
888 spec->curr_chip_addx = (res != -EIO) ?
889 (spec->curr_chip_addx + 4) : ~0UL;
894 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
896 static int chipio_write_data_multiple(struct hda_codec *codec,
903 codec_dbg(codec, "chipio_write_data null ptr\n");
907 while ((count-- != 0) && (status == 0))
908 status = chipio_write_data(codec, *data++);
915 * Read data through the vendor widget -- NOT protected by the Mutex!
917 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
919 struct ca0132_spec *spec = codec->spec;
923 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
927 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
932 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
933 VENDOR_CHIPIO_HIC_READ_DATA,
937 /*If no error encountered, automatically increment the address
938 as per chip behaviour*/
939 spec->curr_chip_addx = (res != -EIO) ?
940 (spec->curr_chip_addx + 4) : ~0UL;
945 * Write given value to the given address through the chip I/O widget.
946 * protected by the Mutex
948 static int chipio_write(struct hda_codec *codec,
949 unsigned int chip_addx, const unsigned int data)
951 struct ca0132_spec *spec = codec->spec;
954 mutex_lock(&spec->chipio_mutex);
956 /* write the address, and if successful proceed to write data */
957 err = chipio_write_address(codec, chip_addx);
961 err = chipio_write_data(codec, data);
966 mutex_unlock(&spec->chipio_mutex);
971 * Write multiple values to the given address through the chip I/O widget.
972 * protected by the Mutex
974 static int chipio_write_multiple(struct hda_codec *codec,
979 struct ca0132_spec *spec = codec->spec;
982 mutex_lock(&spec->chipio_mutex);
983 status = chipio_write_address(codec, chip_addx);
987 status = chipio_write_data_multiple(codec, data, count);
989 mutex_unlock(&spec->chipio_mutex);
995 * Read the given address through the chip I/O widget
996 * protected by the Mutex
998 static int chipio_read(struct hda_codec *codec,
999 unsigned int chip_addx, unsigned int *data)
1001 struct ca0132_spec *spec = codec->spec;
1004 mutex_lock(&spec->chipio_mutex);
1006 /* write the address, and if successful proceed to write data */
1007 err = chipio_write_address(codec, chip_addx);
1011 err = chipio_read_data(codec, data);
1016 mutex_unlock(&spec->chipio_mutex);
1021 * Set chip control flags through the chip I/O widget.
1023 static void chipio_set_control_flag(struct hda_codec *codec,
1024 enum control_flag_id flag_id,
1028 unsigned int flag_bit;
1030 flag_bit = (flag_state ? 1 : 0);
1031 val = (flag_bit << 7) | (flag_id);
1032 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1033 VENDOR_CHIPIO_FLAG_SET, val);
1037 * Set chip parameters through the chip I/O widget.
1039 static void chipio_set_control_param(struct hda_codec *codec,
1040 enum control_param_id param_id, int param_val)
1042 struct ca0132_spec *spec = codec->spec;
1045 if ((param_id < 32) && (param_val < 8)) {
1046 val = (param_val << 5) | (param_id);
1047 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1048 VENDOR_CHIPIO_PARAM_SET, val);
1050 mutex_lock(&spec->chipio_mutex);
1051 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1052 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1053 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1055 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1056 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1059 mutex_unlock(&spec->chipio_mutex);
1064 * Set sampling rate of the connection point.
1066 static void chipio_set_conn_rate(struct hda_codec *codec,
1067 int connid, enum ca0132_sample_rate rate)
1069 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1070 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1077 static void chipio_enable_clocks(struct hda_codec *codec)
1079 struct ca0132_spec *spec = codec->spec;
1081 mutex_lock(&spec->chipio_mutex);
1082 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1083 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1084 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1085 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1086 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1087 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1088 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1089 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1090 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1091 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1092 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1093 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1094 mutex_unlock(&spec->chipio_mutex);
1098 * CA0132 DSP IO stuffs
1100 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1104 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1106 /* send bits of data specified by reg to dsp */
1108 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1109 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1112 } while (time_before(jiffies, timeout));
1118 * Wait for DSP to be ready for commands
1120 static void dspio_write_wait(struct hda_codec *codec)
1123 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1126 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1127 VENDOR_DSPIO_STATUS, 0);
1128 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1129 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1132 } while (time_before(jiffies, timeout));
1136 * Write SCP data to DSP
1138 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1140 struct ca0132_spec *spec = codec->spec;
1143 dspio_write_wait(codec);
1145 mutex_lock(&spec->chipio_mutex);
1146 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1151 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1156 /* OK, now check if the write itself has executed*/
1157 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1158 VENDOR_DSPIO_STATUS, 0);
1160 mutex_unlock(&spec->chipio_mutex);
1162 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1167 * Write multiple SCP data to DSP
1169 static int dspio_write_multiple(struct hda_codec *codec,
1170 unsigned int *buffer, unsigned int size)
1175 if ((buffer == NULL))
1179 while (count < size) {
1180 status = dspio_write(codec, *buffer++);
1189 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1193 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1197 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1198 if (status == -EIO ||
1199 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1202 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1203 VENDOR_DSPIO_SCP_READ_DATA, 0);
1208 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1209 unsigned int *buf_size, unsigned int size_count)
1212 unsigned int size = *buf_size;
1214 unsigned int skip_count;
1217 if ((buffer == NULL))
1221 while (count < size && count < size_count) {
1222 status = dspio_read(codec, buffer++);
1230 while (skip_count < size) {
1231 status = dspio_read(codec, &dummy);
1243 * Construct the SCP header using corresponding fields
1245 static inline unsigned int
1246 make_scp_header(unsigned int target_id, unsigned int source_id,
1247 unsigned int get_flag, unsigned int req,
1248 unsigned int device_flag, unsigned int resp_flag,
1249 unsigned int error_flag, unsigned int data_size)
1251 unsigned int header = 0;
1253 header = (data_size & 0x1f) << 27;
1254 header |= (error_flag & 0x01) << 26;
1255 header |= (resp_flag & 0x01) << 25;
1256 header |= (device_flag & 0x01) << 24;
1257 header |= (req & 0x7f) << 17;
1258 header |= (get_flag & 0x01) << 16;
1259 header |= (source_id & 0xff) << 8;
1260 header |= target_id & 0xff;
1266 * Extract corresponding fields from SCP header
1269 extract_scp_header(unsigned int header,
1270 unsigned int *target_id, unsigned int *source_id,
1271 unsigned int *get_flag, unsigned int *req,
1272 unsigned int *device_flag, unsigned int *resp_flag,
1273 unsigned int *error_flag, unsigned int *data_size)
1276 *data_size = (header >> 27) & 0x1f;
1278 *error_flag = (header >> 26) & 0x01;
1280 *resp_flag = (header >> 25) & 0x01;
1282 *device_flag = (header >> 24) & 0x01;
1284 *req = (header >> 17) & 0x7f;
1286 *get_flag = (header >> 16) & 0x01;
1288 *source_id = (header >> 8) & 0xff;
1290 *target_id = header & 0xff;
1293 #define SCP_MAX_DATA_WORDS (16)
1295 /* Structure to contain any SCP message */
1298 unsigned int data[SCP_MAX_DATA_WORDS];
1301 static void dspio_clear_response_queue(struct hda_codec *codec)
1303 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1304 unsigned int dummy = 0;
1307 /* clear all from the response queue */
1309 status = dspio_read(codec, &dummy);
1310 } while (status == 0 && time_before(jiffies, timeout));
1313 static int dspio_get_response_data(struct hda_codec *codec)
1315 struct ca0132_spec *spec = codec->spec;
1316 unsigned int data = 0;
1319 if (dspio_read(codec, &data) < 0)
1322 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1323 spec->scp_resp_header = data;
1324 spec->scp_resp_count = data >> 27;
1325 count = spec->wait_num_data;
1326 dspio_read_multiple(codec, spec->scp_resp_data,
1327 &spec->scp_resp_count, count);
1335 * Send SCP message to DSP
1337 static int dspio_send_scp_message(struct hda_codec *codec,
1338 unsigned char *send_buf,
1339 unsigned int send_buf_size,
1340 unsigned char *return_buf,
1341 unsigned int return_buf_size,
1342 unsigned int *bytes_returned)
1344 struct ca0132_spec *spec = codec->spec;
1346 unsigned int scp_send_size = 0;
1347 unsigned int total_size;
1348 bool waiting_for_resp = false;
1349 unsigned int header;
1350 struct scp_msg *ret_msg;
1351 unsigned int resp_src_id, resp_target_id;
1352 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1355 *bytes_returned = 0;
1357 /* get scp header from buffer */
1358 header = *((unsigned int *)send_buf);
1359 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1360 &device_flag, NULL, NULL, &data_size);
1361 scp_send_size = data_size + 1;
1362 total_size = (scp_send_size * 4);
1364 if (send_buf_size < total_size)
1367 if (get_flag || device_flag) {
1368 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1371 spec->wait_scp_header = *((unsigned int *)send_buf);
1373 /* swap source id with target id */
1374 resp_target_id = src_id;
1375 resp_src_id = target_id;
1376 spec->wait_scp_header &= 0xffff0000;
1377 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1378 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1380 waiting_for_resp = true;
1383 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1390 if (waiting_for_resp) {
1391 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1392 memset(return_buf, 0, return_buf_size);
1395 } while (spec->wait_scp && time_before(jiffies, timeout));
1396 waiting_for_resp = false;
1397 if (!spec->wait_scp) {
1398 ret_msg = (struct scp_msg *)return_buf;
1399 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1400 memcpy(&ret_msg->data, spec->scp_resp_data,
1401 spec->wait_num_data);
1402 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1414 * Prepare and send the SCP message to DSP
1415 * @codec: the HDA codec
1416 * @mod_id: ID of the DSP module to send the command
1417 * @req: ID of request to send to the DSP module
1419 * @data: pointer to the data to send with the request, request specific
1420 * @len: length of the data, in bytes
1421 * @reply: point to the buffer to hold data returned for a reply
1422 * @reply_len: length of the reply buffer returned from GET
1424 * Returns zero or a negative error code.
1426 static int dspio_scp(struct hda_codec *codec,
1427 int mod_id, int req, int dir, void *data, unsigned int len,
1428 void *reply, unsigned int *reply_len)
1431 struct scp_msg scp_send, scp_reply;
1432 unsigned int ret_bytes, send_size, ret_size;
1433 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1434 unsigned int reply_data_size;
1436 memset(&scp_send, 0, sizeof(scp_send));
1437 memset(&scp_reply, 0, sizeof(scp_reply));
1439 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1442 if (dir == SCP_GET && reply == NULL) {
1443 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1447 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1448 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1452 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1453 0, 0, 0, len/sizeof(unsigned int));
1454 if (data != NULL && len > 0) {
1455 len = min((unsigned int)(sizeof(scp_send.data)), len);
1456 memcpy(scp_send.data, data, len);
1460 send_size = sizeof(unsigned int) + len;
1461 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1462 send_size, (unsigned char *)&scp_reply,
1463 sizeof(scp_reply), &ret_bytes);
1466 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1470 /* extract send and reply headers members */
1471 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1472 NULL, NULL, NULL, NULL, NULL);
1473 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1474 &reply_resp_flag, &reply_error_flag,
1480 if (reply_resp_flag && !reply_error_flag) {
1481 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1482 / sizeof(unsigned int);
1484 if (*reply_len < ret_size*sizeof(unsigned int)) {
1485 codec_dbg(codec, "reply too long for buf\n");
1487 } else if (ret_size != reply_data_size) {
1488 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1490 } else if (!reply) {
1491 codec_dbg(codec, "NULL reply\n");
1494 *reply_len = ret_size*sizeof(unsigned int);
1495 memcpy(reply, scp_reply.data, *reply_len);
1498 codec_dbg(codec, "reply ill-formed or errflag set\n");
1506 * Set DSP parameters
1508 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1509 int req, void *data, unsigned int len)
1511 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1514 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1515 int req, unsigned int data)
1517 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1521 * Allocate a DSP DMA channel via an SCP message
1523 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1526 unsigned int size = sizeof(dma_chan);
1528 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
1529 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1530 SCP_GET, NULL, 0, dma_chan, &size);
1533 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1537 if ((*dma_chan + 1) == 0) {
1538 codec_dbg(codec, "no free dma channels to allocate\n");
1542 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1543 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
1549 * Free a DSP DMA via an SCP message
1551 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1554 unsigned int dummy = 0;
1556 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1557 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1559 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1560 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1563 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1567 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
1575 static int dsp_set_run_state(struct hda_codec *codec)
1577 unsigned int dbg_ctrl_reg;
1578 unsigned int halt_state;
1581 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1585 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1586 DSP_DBGCNTL_STATE_LOBIT;
1588 if (halt_state != 0) {
1589 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1590 DSP_DBGCNTL_SS_MASK);
1591 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1596 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1597 DSP_DBGCNTL_EXEC_MASK;
1598 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1610 static int dsp_reset(struct hda_codec *codec)
1615 codec_dbg(codec, "dsp_reset\n");
1617 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1619 } while (res == -EIO && retry);
1622 codec_dbg(codec, "dsp_reset timeout\n");
1630 * Convert chip address to DSP address
1632 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1633 bool *code, bool *yram)
1635 *code = *yram = false;
1637 if (UC_RANGE(chip_addx, 1)) {
1639 return UC_OFF(chip_addx);
1640 } else if (X_RANGE_ALL(chip_addx, 1)) {
1641 return X_OFF(chip_addx);
1642 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1644 return Y_OFF(chip_addx);
1647 return INVALID_CHIP_ADDRESS;
1651 * Check if the DSP DMA is active
1653 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1655 unsigned int dma_chnlstart_reg;
1657 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1659 return ((dma_chnlstart_reg & (1 <<
1660 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1663 static int dsp_dma_setup_common(struct hda_codec *codec,
1664 unsigned int chip_addx,
1665 unsigned int dma_chan,
1666 unsigned int port_map_mask,
1670 unsigned int chnl_prop;
1671 unsigned int dsp_addx;
1672 unsigned int active;
1675 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
1677 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1678 codec_dbg(codec, "dma chan num invalid\n");
1682 if (dsp_is_dma_active(codec, dma_chan)) {
1683 codec_dbg(codec, "dma already active\n");
1687 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1689 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1690 codec_dbg(codec, "invalid chip addr\n");
1694 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1697 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
1700 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1704 codec_dbg(codec, "read CHNLPROP Reg fail\n");
1707 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
1711 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1713 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1715 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1717 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1719 codec_dbg(codec, "write CHNLPROP Reg fail\n");
1722 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
1725 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1729 codec_dbg(codec, "read ACTIVE Reg fail\n");
1732 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
1735 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1736 DSPDMAC_ACTIVE_AAR_MASK;
1738 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1740 codec_dbg(codec, "write ACTIVE Reg fail\n");
1744 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
1746 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1749 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
1752 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
1754 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1755 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1757 codec_dbg(codec, "write IRQCNT Reg fail\n");
1760 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
1763 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1764 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1765 chip_addx, dsp_addx, dma_chan,
1766 port_map_mask, chnl_prop, active);
1768 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
1774 * Setup the DSP DMA per-transfer-specific registers
1776 static int dsp_dma_setup(struct hda_codec *codec,
1777 unsigned int chip_addx,
1779 unsigned int dma_chan)
1783 unsigned int dsp_addx;
1784 unsigned int addr_field;
1785 unsigned int incr_field;
1786 unsigned int base_cnt;
1787 unsigned int cur_cnt;
1788 unsigned int dma_cfg = 0;
1789 unsigned int adr_ofs = 0;
1790 unsigned int xfr_cnt = 0;
1791 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1792 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1794 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
1796 if (count > max_dma_count) {
1797 codec_dbg(codec, "count too big\n");
1801 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1802 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1803 codec_dbg(codec, "invalid chip addr\n");
1807 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
1809 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1815 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1817 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1820 dma_cfg = addr_field + incr_field;
1821 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1824 codec_dbg(codec, "write DMACFG Reg fail\n");
1827 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
1829 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1832 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1835 codec_dbg(codec, "write DSPADROFS Reg fail\n");
1838 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
1840 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1842 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1844 xfr_cnt = base_cnt | cur_cnt;
1846 status = chipio_write(codec,
1847 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1849 codec_dbg(codec, "write XFRCNT Reg fail\n");
1852 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
1855 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1856 "ADROFS=0x%x, XFRCNT=0x%x\n",
1857 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1859 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
1867 static int dsp_dma_start(struct hda_codec *codec,
1868 unsigned int dma_chan, bool ovly)
1870 unsigned int reg = 0;
1873 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
1876 status = chipio_read(codec,
1877 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
1880 codec_dbg(codec, "read CHNLSTART reg fail\n");
1883 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
1885 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1886 DSPDMAC_CHNLSTART_DIS_MASK);
1889 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1890 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1892 codec_dbg(codec, "write CHNLSTART reg fail\n");
1895 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
1903 static int dsp_dma_stop(struct hda_codec *codec,
1904 unsigned int dma_chan, bool ovly)
1906 unsigned int reg = 0;
1909 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
1912 status = chipio_read(codec,
1913 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
1916 codec_dbg(codec, "read CHNLSTART reg fail\n");
1919 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
1920 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1921 DSPDMAC_CHNLSTART_DIS_MASK);
1924 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1925 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1927 codec_dbg(codec, "write CHNLSTART reg fail\n");
1930 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
1936 * Allocate router ports
1938 * @codec: the HDA codec
1939 * @num_chans: number of channels in the stream
1940 * @ports_per_channel: number of ports per channel
1941 * @start_device: start device
1942 * @port_map: pointer to the port list to hold the allocated ports
1944 * Returns zero or a negative error code.
1946 static int dsp_allocate_router_ports(struct hda_codec *codec,
1947 unsigned int num_chans,
1948 unsigned int ports_per_channel,
1949 unsigned int start_device,
1950 unsigned int *port_map)
1956 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1960 val = start_device << 6;
1961 val |= (ports_per_channel - 1) << 4;
1962 val |= num_chans - 1;
1964 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1965 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1968 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1969 VENDOR_CHIPIO_PORT_ALLOC_SET,
1972 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1976 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1977 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1981 return (res < 0) ? res : 0;
1987 static int dsp_free_router_ports(struct hda_codec *codec)
1991 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1995 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1996 VENDOR_CHIPIO_PORT_FREE_SET,
1999 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2005 * Allocate DSP ports for the download stream
2007 static int dsp_allocate_ports(struct hda_codec *codec,
2008 unsigned int num_chans,
2009 unsigned int rate_multi, unsigned int *port_map)
2013 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
2015 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2016 codec_dbg(codec, "bad rate multiple\n");
2020 status = dsp_allocate_router_ports(codec, num_chans,
2021 rate_multi, 0, port_map);
2023 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2028 static int dsp_allocate_ports_format(struct hda_codec *codec,
2029 const unsigned short fmt,
2030 unsigned int *port_map)
2033 unsigned int num_chans;
2035 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2036 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2037 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2039 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2040 codec_dbg(codec, "bad rate multiple\n");
2044 num_chans = get_hdafmt_chs(fmt) + 1;
2046 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2054 static int dsp_free_ports(struct hda_codec *codec)
2058 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2060 status = dsp_free_router_ports(codec);
2062 codec_dbg(codec, "free router ports fail\n");
2065 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2071 * HDA DMA engine stuffs for DSP code download
2074 struct hda_codec *codec;
2075 unsigned short m_converter_format;
2076 struct snd_dma_buffer *dmab;
2077 unsigned int buf_size;
2086 static int dma_convert_to_hda_format(struct hda_codec *codec,
2087 unsigned int sample_rate,
2088 unsigned short channels,
2089 unsigned short *hda_format)
2091 unsigned int format_val;
2093 format_val = snd_hdac_calc_stream_format(sample_rate,
2094 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2097 *hda_format = (unsigned short)format_val;
2103 * Reset DMA for DSP download
2105 static int dma_reset(struct dma_engine *dma)
2107 struct hda_codec *codec = dma->codec;
2108 struct ca0132_spec *spec = codec->spec;
2111 if (dma->dmab->area)
2112 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2114 status = snd_hda_codec_load_dsp_prepare(codec,
2115 dma->m_converter_format,
2120 spec->dsp_stream_id = status;
2124 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2129 case DMA_STATE_STOP:
2139 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2143 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2145 return dma->dmab->bytes;
2148 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2150 return dma->dmab->area;
2153 static int dma_xfer(struct dma_engine *dma,
2154 const unsigned int *data,
2157 memcpy(dma->dmab->area, data, count);
2161 static void dma_get_converter_format(
2162 struct dma_engine *dma,
2163 unsigned short *format)
2166 *format = dma->m_converter_format;
2169 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2171 struct ca0132_spec *spec = dma->codec->spec;
2173 return spec->dsp_stream_id;
2176 struct dsp_image_seg {
2183 static const u32 g_magic_value = 0x4c46584d;
2184 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2186 static bool is_valid(const struct dsp_image_seg *p)
2188 return p->magic == g_magic_value;
2191 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2193 return g_chip_addr_magic_value == p->chip_addr;
2196 static bool is_last(const struct dsp_image_seg *p)
2198 return p->count == 0;
2201 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2203 return sizeof(*p) + p->count*sizeof(u32);
2206 static const struct dsp_image_seg *get_next_seg_ptr(
2207 const struct dsp_image_seg *p)
2209 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2213 * CA0132 chip DSP transfer stuffs. For DSP download.
2215 #define INVALID_DMA_CHANNEL (~0U)
2218 * Program a list of address/data pairs via the ChipIO widget.
2219 * The segment data is in the format of successive pairs of words.
2220 * These are repeated as indicated by the segment's count field.
2222 static int dspxfr_hci_write(struct hda_codec *codec,
2223 const struct dsp_image_seg *fls)
2229 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2230 codec_dbg(codec, "hci_write invalid params\n");
2235 data = (u32 *)(fls->data);
2236 while (count >= 2) {
2237 status = chipio_write(codec, data[0], data[1]);
2239 codec_dbg(codec, "hci_write chipio failed\n");
2249 * Write a block of data into DSP code or data RAM using pre-allocated
2252 * @codec: the HDA codec
2253 * @fls: pointer to a fast load image
2254 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2256 * @dma_engine: pointer to DMA engine to be used for DSP download
2257 * @dma_chan: The number of DMA channels used for DSP download
2258 * @port_map_mask: port mapping
2259 * @ovly: TRUE if overlay format is required
2261 * Returns zero or a negative error code.
2263 static int dspxfr_one_seg(struct hda_codec *codec,
2264 const struct dsp_image_seg *fls,
2266 struct dma_engine *dma_engine,
2267 unsigned int dma_chan,
2268 unsigned int port_map_mask,
2272 bool comm_dma_setup_done = false;
2273 const unsigned int *data;
2274 unsigned int chip_addx;
2275 unsigned int words_to_write;
2276 unsigned int buffer_size_words;
2277 unsigned char *buffer_addx;
2278 unsigned short hda_format;
2279 unsigned int sample_rate_div;
2280 unsigned int sample_rate_mul;
2281 unsigned int num_chans;
2282 unsigned int hda_frame_size_words;
2283 unsigned int remainder_words;
2284 const u32 *data_remainder;
2285 u32 chip_addx_remainder;
2286 unsigned int run_size_words;
2287 const struct dsp_image_seg *hci_write = NULL;
2288 unsigned long timeout;
2293 if (is_hci_prog_list_seg(fls)) {
2295 fls = get_next_seg_ptr(fls);
2298 if (hci_write && (!fls || is_last(fls))) {
2299 codec_dbg(codec, "hci_write\n");
2300 return dspxfr_hci_write(codec, hci_write);
2303 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2304 codec_dbg(codec, "Invalid Params\n");
2309 chip_addx = fls->chip_addr,
2310 words_to_write = fls->count;
2312 if (!words_to_write)
2313 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2315 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2317 if (!UC_RANGE(chip_addx, words_to_write) &&
2318 !X_RANGE_ALL(chip_addx, words_to_write) &&
2319 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2320 codec_dbg(codec, "Invalid chip_addx Params\n");
2324 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2327 buffer_addx = dma_get_buffer_addr(dma_engine);
2329 if (buffer_addx == NULL) {
2330 codec_dbg(codec, "dma_engine buffer NULL\n");
2334 dma_get_converter_format(dma_engine, &hda_format);
2335 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2336 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2337 num_chans = get_hdafmt_chs(hda_format) + 1;
2339 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2340 (num_chans * sample_rate_mul / sample_rate_div));
2342 if (hda_frame_size_words == 0) {
2343 codec_dbg(codec, "frmsz zero\n");
2347 buffer_size_words = min(buffer_size_words,
2348 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2350 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2352 "chpadr=0x%08x frmsz=%u nchan=%u "
2353 "rate_mul=%u div=%u bufsz=%u\n",
2354 chip_addx, hda_frame_size_words, num_chans,
2355 sample_rate_mul, sample_rate_div, buffer_size_words);
2357 if (buffer_size_words < hda_frame_size_words) {
2358 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2362 remainder_words = words_to_write % hda_frame_size_words;
2363 data_remainder = data;
2364 chip_addx_remainder = chip_addx;
2366 data += remainder_words;
2367 chip_addx += remainder_words*sizeof(u32);
2368 words_to_write -= remainder_words;
2370 while (words_to_write != 0) {
2371 run_size_words = min(buffer_size_words, words_to_write);
2372 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2373 words_to_write, run_size_words, remainder_words);
2374 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2375 if (!comm_dma_setup_done) {
2376 status = dsp_dma_stop(codec, dma_chan, ovly);
2379 status = dsp_dma_setup_common(codec, chip_addx,
2380 dma_chan, port_map_mask, ovly);
2383 comm_dma_setup_done = true;
2386 status = dsp_dma_setup(codec, chip_addx,
2387 run_size_words, dma_chan);
2390 status = dsp_dma_start(codec, dma_chan, ovly);
2393 if (!dsp_is_dma_active(codec, dma_chan)) {
2394 codec_dbg(codec, "dspxfr:DMA did not start\n");
2397 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2400 if (remainder_words != 0) {
2401 status = chipio_write_multiple(codec,
2402 chip_addx_remainder,
2407 remainder_words = 0;
2410 status = dspxfr_hci_write(codec, hci_write);
2416 timeout = jiffies + msecs_to_jiffies(2000);
2418 dma_active = dsp_is_dma_active(codec, dma_chan);
2422 } while (time_before(jiffies, timeout));
2426 codec_dbg(codec, "+++++ DMA complete\n");
2427 dma_set_state(dma_engine, DMA_STATE_STOP);
2428 status = dma_reset(dma_engine);
2433 data += run_size_words;
2434 chip_addx += run_size_words*sizeof(u32);
2435 words_to_write -= run_size_words;
2438 if (remainder_words != 0) {
2439 status = chipio_write_multiple(codec, chip_addx_remainder,
2440 data_remainder, remainder_words);
2447 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2449 * @codec: the HDA codec
2450 * @fls_data: pointer to a fast load image
2451 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2453 * @sample_rate: sampling rate of the stream used for DSP download
2454 * @channels: channels of the stream used for DSP download
2455 * @ovly: TRUE if overlay format is required
2457 * Returns zero or a negative error code.
2459 static int dspxfr_image(struct hda_codec *codec,
2460 const struct dsp_image_seg *fls_data,
2462 unsigned int sample_rate,
2463 unsigned short channels,
2466 struct ca0132_spec *spec = codec->spec;
2468 unsigned short hda_format = 0;
2469 unsigned int response;
2470 unsigned char stream_id = 0;
2471 struct dma_engine *dma_engine;
2472 unsigned int dma_chan;
2473 unsigned int port_map_mask;
2475 if (fls_data == NULL)
2478 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2482 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2483 if (!dma_engine->dmab) {
2488 dma_engine->codec = codec;
2489 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2490 dma_engine->m_converter_format = hda_format;
2491 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2492 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2494 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2496 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2497 hda_format, &response);
2500 codec_dbg(codec, "set converter format fail\n");
2504 status = snd_hda_codec_load_dsp_prepare(codec,
2505 dma_engine->m_converter_format,
2506 dma_engine->buf_size,
2510 spec->dsp_stream_id = status;
2513 status = dspio_alloc_dma_chan(codec, &dma_chan);
2515 codec_dbg(codec, "alloc dmachan fail\n");
2516 dma_chan = INVALID_DMA_CHANNEL;
2522 status = dsp_allocate_ports_format(codec, hda_format,
2525 codec_dbg(codec, "alloc ports fail\n");
2529 stream_id = dma_get_stream_id(dma_engine);
2530 status = codec_set_converter_stream_channel(codec,
2531 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2533 codec_dbg(codec, "set stream chan fail\n");
2537 while ((fls_data != NULL) && !is_last(fls_data)) {
2538 if (!is_valid(fls_data)) {
2539 codec_dbg(codec, "FLS check fail\n");
2543 status = dspxfr_one_seg(codec, fls_data, reloc,
2544 dma_engine, dma_chan,
2545 port_map_mask, ovly);
2549 if (is_hci_prog_list_seg(fls_data))
2550 fls_data = get_next_seg_ptr(fls_data);
2552 if ((fls_data != NULL) && !is_last(fls_data))
2553 fls_data = get_next_seg_ptr(fls_data);
2556 if (port_map_mask != 0)
2557 status = dsp_free_ports(codec);
2562 status = codec_set_converter_stream_channel(codec,
2563 WIDGET_CHIP_CTRL, 0, 0, &response);
2566 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2567 dspio_free_dma_chan(codec, dma_chan);
2569 if (dma_engine->dmab->area)
2570 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2571 kfree(dma_engine->dmab);
2578 * CA0132 DSP download stuffs.
2580 static void dspload_post_setup(struct hda_codec *codec)
2582 codec_dbg(codec, "---- dspload_post_setup ------\n");
2584 /*set DSP speaker to 2.0 configuration*/
2585 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2586 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2588 /*update write pointer*/
2589 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2593 * dspload_image - Download DSP from a DSP Image Fast Load structure.
2595 * @codec: the HDA codec
2596 * @fls: pointer to a fast load image
2597 * @ovly: TRUE if overlay format is required
2598 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2600 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2601 * @router_chans: number of audio router channels to be allocated (0 means use
2602 * internal defaults; max is 32)
2604 * Download DSP from a DSP Image Fast Load structure. This structure is a
2605 * linear, non-constant sized element array of structures, each of which
2606 * contain the count of the data to be loaded, the data itself, and the
2607 * corresponding starting chip address of the starting data location.
2608 * Returns zero or a negative error code.
2610 static int dspload_image(struct hda_codec *codec,
2611 const struct dsp_image_seg *fls,
2618 unsigned int sample_rate;
2619 unsigned short channels;
2621 codec_dbg(codec, "---- dspload_image begin ------\n");
2622 if (router_chans == 0) {
2624 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2626 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2629 sample_rate = 48000;
2630 channels = (unsigned short)router_chans;
2632 while (channels > 16) {
2638 codec_dbg(codec, "Ready to program DMA\n");
2640 status = dsp_reset(codec);
2645 codec_dbg(codec, "dsp_reset() complete\n");
2646 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2652 codec_dbg(codec, "dspxfr_image() complete\n");
2653 if (autostart && !ovly) {
2654 dspload_post_setup(codec);
2655 status = dsp_set_run_state(codec);
2658 codec_dbg(codec, "LOAD FINISHED\n");
2664 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
2665 static bool dspload_is_loaded(struct hda_codec *codec)
2667 unsigned int data = 0;
2670 status = chipio_read(codec, 0x40004, &data);
2671 if ((status < 0) || (data != 1))
2677 #define dspload_is_loaded(codec) false
2680 static bool dspload_wait_loaded(struct hda_codec *codec)
2682 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
2685 if (dspload_is_loaded(codec)) {
2686 codec_info(codec, "ca0132 DSP downloaded and running\n");
2690 } while (time_before(jiffies, timeout));
2692 codec_err(codec, "ca0132 failed to download DSP\n");
2699 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2700 struct hda_codec *codec,
2701 unsigned int stream_tag,
2702 unsigned int format,
2703 struct snd_pcm_substream *substream)
2705 struct ca0132_spec *spec = codec->spec;
2707 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2712 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2713 struct hda_codec *codec,
2714 struct snd_pcm_substream *substream)
2716 struct ca0132_spec *spec = codec->spec;
2718 if (spec->dsp_state == DSP_DOWNLOADING)
2721 /*If Playback effects are on, allow stream some time to flush
2723 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2726 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
2731 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2732 struct hda_codec *codec,
2733 struct snd_pcm_substream *substream)
2735 struct ca0132_spec *spec = codec->spec;
2736 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2737 struct snd_pcm_runtime *runtime = substream->runtime;
2739 if (spec->dsp_state != DSP_DOWNLOADED)
2742 /* Add latency if playback enhancement and either effect is enabled. */
2743 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2744 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2745 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2746 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2749 /* Applying Speaker EQ adds latency as well. */
2750 if (spec->cur_out_type == SPEAKER_OUT)
2751 latency += DSP_SPEAKER_OUT_LATENCY;
2753 return (latency * runtime->rate) / 1000;
2759 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2760 struct hda_codec *codec,
2761 struct snd_pcm_substream *substream)
2763 struct ca0132_spec *spec = codec->spec;
2764 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2767 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2768 struct hda_codec *codec,
2769 unsigned int stream_tag,
2770 unsigned int format,
2771 struct snd_pcm_substream *substream)
2773 struct ca0132_spec *spec = codec->spec;
2774 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2775 stream_tag, format, substream);
2778 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2779 struct hda_codec *codec,
2780 struct snd_pcm_substream *substream)
2782 struct ca0132_spec *spec = codec->spec;
2783 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
2786 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2787 struct hda_codec *codec,
2788 struct snd_pcm_substream *substream)
2790 struct ca0132_spec *spec = codec->spec;
2791 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2797 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2798 struct hda_codec *codec,
2799 unsigned int stream_tag,
2800 unsigned int format,
2801 struct snd_pcm_substream *substream)
2803 snd_hda_codec_setup_stream(codec, hinfo->nid,
2804 stream_tag, 0, format);
2809 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2810 struct hda_codec *codec,
2811 struct snd_pcm_substream *substream)
2813 struct ca0132_spec *spec = codec->spec;
2815 if (spec->dsp_state == DSP_DOWNLOADING)
2818 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2822 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2823 struct hda_codec *codec,
2824 struct snd_pcm_substream *substream)
2826 struct ca0132_spec *spec = codec->spec;
2827 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2828 struct snd_pcm_runtime *runtime = substream->runtime;
2830 if (spec->dsp_state != DSP_DOWNLOADED)
2833 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2834 latency += DSP_CRYSTAL_VOICE_LATENCY;
2836 return (latency * runtime->rate) / 1000;
2844 * Mixer controls helpers.
2846 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2847 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2849 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2850 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2851 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2852 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2853 .info = ca0132_volume_info, \
2854 .get = ca0132_volume_get, \
2855 .put = ca0132_volume_put, \
2856 .tlv = { .c = ca0132_volume_tlv }, \
2857 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2859 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2860 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2862 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2863 .info = snd_hda_mixer_amp_switch_info, \
2864 .get = ca0132_switch_get, \
2865 .put = ca0132_switch_put, \
2866 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2869 #define CA0132_CODEC_VOL(xname, nid, dir) \
2870 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2871 #define CA0132_CODEC_MUTE(xname, nid, dir) \
2872 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2874 /* The followings are for tuning of products */
2875 #ifdef ENABLE_TUNING_CONTROLS
2877 static unsigned int voice_focus_vals_lookup[] = {
2878 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
2879 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
2880 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
2881 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
2882 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
2883 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
2884 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
2885 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
2886 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
2887 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
2888 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
2889 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
2890 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
2891 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
2892 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
2893 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
2894 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
2895 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
2896 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
2897 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
2898 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
2899 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
2900 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
2901 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
2902 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
2903 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
2904 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2907 static unsigned int mic_svm_vals_lookup[] = {
2908 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
2909 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
2910 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
2911 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
2912 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
2913 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
2914 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
2915 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
2916 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
2917 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
2918 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
2919 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
2920 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
2921 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
2922 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
2923 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
2924 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2927 static unsigned int equalizer_vals_lookup[] = {
2928 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
2929 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
2930 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
2931 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
2932 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
2933 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
2934 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
2935 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
2939 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2940 unsigned int *lookup, int idx)
2944 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2945 if (nid == ca0132_tuning_ctls[i].nid)
2948 snd_hda_power_up(codec);
2949 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2950 ca0132_tuning_ctls[i].req,
2951 &(lookup[idx]), sizeof(unsigned int));
2952 snd_hda_power_down(codec);
2957 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2958 struct snd_ctl_elem_value *ucontrol)
2960 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2961 struct ca0132_spec *spec = codec->spec;
2962 hda_nid_t nid = get_amp_nid(kcontrol);
2963 long *valp = ucontrol->value.integer.value;
2964 int idx = nid - TUNING_CTL_START_NID;
2966 *valp = spec->cur_ctl_vals[idx];
2970 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2971 struct snd_ctl_elem_info *uinfo)
2973 int chs = get_amp_channels(kcontrol);
2974 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2975 uinfo->count = chs == 3 ? 2 : 1;
2976 uinfo->value.integer.min = 20;
2977 uinfo->value.integer.max = 180;
2978 uinfo->value.integer.step = 1;
2983 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2984 struct snd_ctl_elem_value *ucontrol)
2986 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2987 struct ca0132_spec *spec = codec->spec;
2988 hda_nid_t nid = get_amp_nid(kcontrol);
2989 long *valp = ucontrol->value.integer.value;
2992 idx = nid - TUNING_CTL_START_NID;
2994 if (spec->cur_ctl_vals[idx] == *valp)
2997 spec->cur_ctl_vals[idx] = *valp;
3000 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3005 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3006 struct snd_ctl_elem_info *uinfo)
3008 int chs = get_amp_channels(kcontrol);
3009 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3010 uinfo->count = chs == 3 ? 2 : 1;
3011 uinfo->value.integer.min = 0;
3012 uinfo->value.integer.max = 100;
3013 uinfo->value.integer.step = 1;
3018 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3019 struct snd_ctl_elem_value *ucontrol)
3021 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3022 struct ca0132_spec *spec = codec->spec;
3023 hda_nid_t nid = get_amp_nid(kcontrol);
3024 long *valp = ucontrol->value.integer.value;
3027 idx = nid - TUNING_CTL_START_NID;
3029 if (spec->cur_ctl_vals[idx] == *valp)
3032 spec->cur_ctl_vals[idx] = *valp;
3035 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3040 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3041 struct snd_ctl_elem_info *uinfo)
3043 int chs = get_amp_channels(kcontrol);
3044 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3045 uinfo->count = chs == 3 ? 2 : 1;
3046 uinfo->value.integer.min = 0;
3047 uinfo->value.integer.max = 48;
3048 uinfo->value.integer.step = 1;
3053 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3054 struct snd_ctl_elem_value *ucontrol)
3056 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3057 struct ca0132_spec *spec = codec->spec;
3058 hda_nid_t nid = get_amp_nid(kcontrol);
3059 long *valp = ucontrol->value.integer.value;
3062 idx = nid - TUNING_CTL_START_NID;
3064 if (spec->cur_ctl_vals[idx] == *valp)
3067 spec->cur_ctl_vals[idx] = *valp;
3070 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3075 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3076 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
3078 static int add_tuning_control(struct hda_codec *codec,
3079 hda_nid_t pnid, hda_nid_t nid,
3080 const char *name, int dir)
3082 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3083 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3084 struct snd_kcontrol_new knew =
3085 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3087 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3088 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3093 knew.info = voice_focus_ctl_info;
3094 knew.get = tuning_ctl_get;
3095 knew.put = voice_focus_ctl_put;
3096 knew.tlv.p = voice_focus_db_scale;
3099 knew.info = mic_svm_ctl_info;
3100 knew.get = tuning_ctl_get;
3101 knew.put = mic_svm_ctl_put;
3104 knew.info = equalizer_ctl_info;
3105 knew.get = tuning_ctl_get;
3106 knew.put = equalizer_ctl_put;
3107 knew.tlv.p = eq_db_scale;
3112 knew.private_value =
3113 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3114 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3115 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3118 static int add_tuning_ctls(struct hda_codec *codec)
3123 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3124 err = add_tuning_control(codec,
3125 ca0132_tuning_ctls[i].parent_nid,
3126 ca0132_tuning_ctls[i].nid,
3127 ca0132_tuning_ctls[i].name,
3128 ca0132_tuning_ctls[i].direct);
3136 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3138 struct ca0132_spec *spec = codec->spec;
3141 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3142 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3143 /* SVM level defaults to 0.74. */
3144 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3146 /* EQ defaults to 0dB. */
3147 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3148 spec->cur_ctl_vals[i] = 24;
3150 #endif /*ENABLE_TUNING_CONTROLS*/
3153 * Select the active output.
3154 * If autodetect is enabled, output will be selected based on jack detection.
3155 * If jack inserted, headphone will be selected, else built-in speakers
3156 * If autodetect is disabled, output will be selected based on selection.
3158 static int ca0132_select_out(struct hda_codec *codec)
3160 struct ca0132_spec *spec = codec->spec;
3161 unsigned int pin_ctl;
3167 codec_dbg(codec, "ca0132_select_out\n");
3169 snd_hda_power_up_pm(codec);
3171 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3174 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
3177 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3180 spec->cur_out_type = HEADPHONE_OUT;
3182 spec->cur_out_type = SPEAKER_OUT;
3184 if (spec->cur_out_type == SPEAKER_OUT) {
3185 codec_dbg(codec, "ca0132_select_out speaker\n");
3186 /*speaker out config*/
3188 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3191 /*enable speaker EQ*/
3193 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3198 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3199 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3200 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3201 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3202 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3203 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3204 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3205 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3207 /* disable headphone node */
3208 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3209 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3210 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3212 /* enable speaker node */
3213 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3214 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3215 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3218 codec_dbg(codec, "ca0132_select_out hp\n");
3219 /*headphone out config*/
3221 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3224 /*disable speaker EQ*/
3226 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3231 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3232 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3233 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3234 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3235 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3236 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3237 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3238 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3240 /* disable speaker*/
3241 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3242 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3243 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3245 /* enable headphone*/
3246 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3247 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3248 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3253 snd_hda_power_down_pm(codec);
3255 return err < 0 ? err : 0;
3258 static void ca0132_unsol_hp_delayed(struct work_struct *work)
3260 struct ca0132_spec *spec = container_of(
3261 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
3262 struct hda_jack_tbl *jack;
3264 ca0132_select_out(spec->codec);
3265 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
3267 jack->block_report = 0;
3268 snd_hda_jack_report_sync(spec->codec);
3272 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3273 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3274 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3277 * Select the active VIP source
3279 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3281 struct ca0132_spec *spec = codec->spec;
3284 if (spec->dsp_state != DSP_DOWNLOADED)
3287 /* if CrystalVoice if off, vipsource should be 0 */
3288 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3290 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3291 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3292 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3293 if (spec->cur_mic_type == DIGITAL_MIC)
3297 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3299 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3301 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3302 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3303 if (spec->cur_mic_type == DIGITAL_MIC)
3307 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3309 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3311 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3318 * Select the active microphone.
3319 * If autodetect is enabled, mic will be selected based on jack detection.
3320 * If jack inserted, ext.mic will be selected, else built-in mic
3321 * If autodetect is disabled, mic will be selected based on selection.
3323 static int ca0132_select_mic(struct hda_codec *codec)
3325 struct ca0132_spec *spec = codec->spec;
3329 codec_dbg(codec, "ca0132_select_mic\n");
3331 snd_hda_power_up_pm(codec);
3333 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3336 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
3339 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3342 spec->cur_mic_type = LINE_MIC_IN;
3344 spec->cur_mic_type = DIGITAL_MIC;
3346 if (spec->cur_mic_type == DIGITAL_MIC) {
3347 /* enable digital Mic */
3348 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3349 ca0132_set_dmic(codec, 1);
3350 ca0132_mic_boost_set(codec, 0);
3351 /* set voice focus */
3352 ca0132_effects_set(codec, VOICE_FOCUS,
3353 spec->effects_switch
3354 [VOICE_FOCUS - EFFECT_START_NID]);
3356 /* disable digital Mic */
3357 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3358 ca0132_set_dmic(codec, 0);
3359 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3360 /* disable voice focus */
3361 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3364 snd_hda_power_down_pm(codec);
3370 * Check if VNODE settings take effect immediately.
3372 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3374 hda_nid_t *shared_nid)
3376 struct ca0132_spec *spec = codec->spec;
3381 nid = spec->shared_out_nid;
3384 nid = spec->shared_mic_nid;
3397 * The following functions are control change helpers.
3398 * They return 0 if no changed. Return 1 if changed.
3400 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3402 struct ca0132_spec *spec = codec->spec;
3405 /* based on CrystalVoice state to enable VoiceFX. */
3407 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3408 FLOAT_ONE : FLOAT_ZERO;
3413 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3414 ca0132_voicefx.reqs[0], tmp);
3420 * Set the effects parameters
3422 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3424 struct ca0132_spec *spec = codec->spec;
3426 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3428 int idx = nid - EFFECT_START_NID;
3430 if ((idx < 0) || (idx >= num_fx))
3431 return 0; /* no changed */
3433 /* for out effect, qualify with PE */
3434 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3435 /* if PE if off, turn off out effects. */
3436 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3440 /* for in effect, qualify with CrystalVoice */
3441 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3442 /* if CrystalVoice if off, turn off in effects. */
3443 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3446 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3447 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3451 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
3454 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3455 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3456 ca0132_effects[idx].reqs[0], on);
3459 return 0; /* no changed */
3465 * Turn on/off Playback Enhancements
3467 static int ca0132_pe_switch_set(struct hda_codec *codec)
3469 struct ca0132_spec *spec = codec->spec;
3473 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
3474 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3476 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3477 nid = OUT_EFFECT_START_NID;
3478 /* PE affects all out effects */
3479 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3480 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3485 /* Check if Mic1 is streaming, if so, stop streaming */
3486 static int stop_mic1(struct hda_codec *codec)
3488 struct ca0132_spec *spec = codec->spec;
3489 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3490 AC_VERB_GET_CONV, 0);
3492 snd_hda_codec_write(codec, spec->adcs[0], 0,
3493 AC_VERB_SET_CHANNEL_STREAMID,
3498 /* Resume Mic1 streaming if it was stopped. */
3499 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3501 struct ca0132_spec *spec = codec->spec;
3502 /* Restore the previous stream and channel */
3504 snd_hda_codec_write(codec, spec->adcs[0], 0,
3505 AC_VERB_SET_CHANNEL_STREAMID,
3510 * Turn on/off CrystalVoice
3512 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3514 struct ca0132_spec *spec = codec->spec;
3517 unsigned int oldval;
3519 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
3520 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3522 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3523 nid = IN_EFFECT_START_NID;
3524 /* CrystalVoice affects all in effects */
3525 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3526 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3528 /* including VoiceFX */
3529 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3531 /* set correct vipsource */
3532 oldval = stop_mic1(codec);
3533 ret |= ca0132_set_vipsource(codec, 1);
3534 resume_mic1(codec, oldval);
3538 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3540 struct ca0132_spec *spec = codec->spec;
3544 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3545 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3547 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3548 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3553 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3554 struct snd_ctl_elem_value *ucontrol)
3556 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3557 hda_nid_t nid = get_amp_nid(kcontrol);
3558 hda_nid_t shared_nid = 0;
3561 struct ca0132_spec *spec = codec->spec;
3564 if (nid == VNID_HP_SEL) {
3566 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3568 ca0132_select_out(codec);
3572 if (nid == VNID_AMIC1_SEL) {
3574 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3576 ca0132_select_mic(codec);
3580 if (nid == VNID_HP_ASEL) {
3581 ca0132_select_out(codec);
3585 if (nid == VNID_AMIC1_ASEL) {
3586 ca0132_select_mic(codec);
3590 /* if effective conditions, then update hw immediately. */
3591 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3593 int dir = get_amp_direction(kcontrol);
3594 int ch = get_amp_channels(kcontrol);
3597 mutex_lock(&codec->control_mutex);
3598 pval = kcontrol->private_value;
3599 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3601 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3602 kcontrol->private_value = pval;
3603 mutex_unlock(&codec->control_mutex);
3608 /* End of control change helpers. */
3610 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3611 struct snd_ctl_elem_info *uinfo)
3613 unsigned int items = sizeof(ca0132_voicefx_presets)
3614 / sizeof(struct ct_voicefx_preset);
3616 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3618 uinfo->value.enumerated.items = items;
3619 if (uinfo->value.enumerated.item >= items)
3620 uinfo->value.enumerated.item = items - 1;
3621 strcpy(uinfo->value.enumerated.name,
3622 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3626 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
3627 struct snd_ctl_elem_value *ucontrol)
3629 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3630 struct ca0132_spec *spec = codec->spec;
3632 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
3636 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
3637 struct snd_ctl_elem_value *ucontrol)
3639 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3640 struct ca0132_spec *spec = codec->spec;
3642 int sel = ucontrol->value.enumerated.item[0];
3643 unsigned int items = sizeof(ca0132_voicefx_presets)
3644 / sizeof(struct ct_voicefx_preset);
3649 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
3650 sel, ca0132_voicefx_presets[sel].name);
3654 * Default needs to qualify with CrystalVoice state.
3656 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3657 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3658 ca0132_voicefx.reqs[i],
3659 ca0132_voicefx_presets[sel].vals[i]);
3665 spec->voicefx_val = sel;
3666 /* enable voice fx */
3667 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3673 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3674 struct snd_ctl_elem_value *ucontrol)
3676 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3677 struct ca0132_spec *spec = codec->spec;
3678 hda_nid_t nid = get_amp_nid(kcontrol);
3679 int ch = get_amp_channels(kcontrol);
3680 long *valp = ucontrol->value.integer.value;
3683 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3685 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3689 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3695 /* effects, include PE and CrystalVoice */
3696 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3697 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3702 if (nid == spec->input_pins[0]) {
3703 *valp = spec->cur_mic_boost;
3710 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3711 struct snd_ctl_elem_value *ucontrol)
3713 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3714 struct ca0132_spec *spec = codec->spec;
3715 hda_nid_t nid = get_amp_nid(kcontrol);
3716 int ch = get_amp_channels(kcontrol);
3717 long *valp = ucontrol->value.integer.value;
3720 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
3723 snd_hda_power_up(codec);
3725 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3727 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3731 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3734 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3739 if (nid == PLAY_ENHANCEMENT) {
3740 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3741 changed = ca0132_pe_switch_set(codec);
3746 if (nid == CRYSTAL_VOICE) {
3747 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3748 changed = ca0132_cvoice_switch_set(codec);
3752 /* out and in effects */
3753 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3754 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3755 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3756 changed = ca0132_effects_set(codec, nid, *valp);
3761 if (nid == spec->input_pins[0]) {
3762 spec->cur_mic_boost = *valp;
3764 /* Mic boost does not apply to Digital Mic */
3765 if (spec->cur_mic_type != DIGITAL_MIC)
3766 changed = ca0132_mic_boost_set(codec, *valp);
3771 snd_hda_power_down(codec);
3778 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3779 struct snd_ctl_elem_info *uinfo)
3781 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3782 struct ca0132_spec *spec = codec->spec;
3783 hda_nid_t nid = get_amp_nid(kcontrol);
3784 int ch = get_amp_channels(kcontrol);
3785 int dir = get_amp_direction(kcontrol);
3791 /* follow shared_out info */
3792 nid = spec->shared_out_nid;
3793 mutex_lock(&codec->control_mutex);
3794 pval = kcontrol->private_value;
3795 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3796 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3797 kcontrol->private_value = pval;
3798 mutex_unlock(&codec->control_mutex);
3801 /* follow shared_mic info */
3802 nid = spec->shared_mic_nid;
3803 mutex_lock(&codec->control_mutex);
3804 pval = kcontrol->private_value;
3805 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3806 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3807 kcontrol->private_value = pval;
3808 mutex_unlock(&codec->control_mutex);
3811 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3816 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
3817 struct snd_ctl_elem_value *ucontrol)
3819 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3820 struct ca0132_spec *spec = codec->spec;
3821 hda_nid_t nid = get_amp_nid(kcontrol);
3822 int ch = get_amp_channels(kcontrol);
3823 long *valp = ucontrol->value.integer.value;
3825 /* store the left and right volume */
3827 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3831 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3837 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
3838 struct snd_ctl_elem_value *ucontrol)
3840 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3841 struct ca0132_spec *spec = codec->spec;
3842 hda_nid_t nid = get_amp_nid(kcontrol);
3843 int ch = get_amp_channels(kcontrol);
3844 long *valp = ucontrol->value.integer.value;
3845 hda_nid_t shared_nid = 0;
3849 /* store the left and right volume */
3851 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3855 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3859 /* if effective conditions, then update hw immediately. */
3860 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3862 int dir = get_amp_direction(kcontrol);
3865 snd_hda_power_up(codec);
3866 mutex_lock(&codec->control_mutex);
3867 pval = kcontrol->private_value;
3868 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3870 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3871 kcontrol->private_value = pval;
3872 mutex_unlock(&codec->control_mutex);
3873 snd_hda_power_down(codec);
3879 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3880 unsigned int size, unsigned int __user *tlv)
3882 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3883 struct ca0132_spec *spec = codec->spec;
3884 hda_nid_t nid = get_amp_nid(kcontrol);
3885 int ch = get_amp_channels(kcontrol);
3886 int dir = get_amp_direction(kcontrol);
3892 /* follow shared_out tlv */
3893 nid = spec->shared_out_nid;
3894 mutex_lock(&codec->control_mutex);
3895 pval = kcontrol->private_value;
3896 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3897 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3898 kcontrol->private_value = pval;
3899 mutex_unlock(&codec->control_mutex);
3902 /* follow shared_mic tlv */
3903 nid = spec->shared_mic_nid;
3904 mutex_lock(&codec->control_mutex);
3905 pval = kcontrol->private_value;
3906 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3907 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3908 kcontrol->private_value = pval;
3909 mutex_unlock(&codec->control_mutex);
3912 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3917 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3918 const char *pfx, int dir)
3920 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3921 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3922 struct snd_kcontrol_new knew =
3923 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3924 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
3925 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3928 static int add_voicefx(struct hda_codec *codec)
3930 struct snd_kcontrol_new knew =
3931 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3932 VOICEFX, 1, 0, HDA_INPUT);
3933 knew.info = ca0132_voicefx_info;
3934 knew.get = ca0132_voicefx_get;
3935 knew.put = ca0132_voicefx_put;
3936 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
3940 * When changing Node IDs for Mixer Controls below, make sure to update
3941 * Node IDs in ca0132_config() as well.
3943 static struct snd_kcontrol_new ca0132_mixer[] = {
3944 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3945 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3946 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3947 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3948 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3949 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3950 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3951 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3952 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3953 0x12, 1, HDA_INPUT),
3954 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3955 VNID_HP_SEL, 1, HDA_OUTPUT),
3956 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3957 VNID_AMIC1_SEL, 1, HDA_INPUT),
3958 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3959 VNID_HP_ASEL, 1, HDA_OUTPUT),
3960 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3961 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3965 static int ca0132_build_controls(struct hda_codec *codec)
3967 struct ca0132_spec *spec = codec->spec;
3971 /* Add Mixer controls */
3972 for (i = 0; i < spec->num_mixers; i++) {
3973 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3978 /* Add in and out effects controls.
3979 * VoiceFX, PE and CrystalVoice are added separately.
3981 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3982 for (i = 0; i < num_fx; i++) {
3983 err = add_fx_switch(codec, ca0132_effects[i].nid,
3984 ca0132_effects[i].name,
3985 ca0132_effects[i].direct);
3990 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3994 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
4000 #ifdef ENABLE_TUNING_CONTROLS
4001 add_tuning_ctls(codec);
4004 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
4008 if (spec->dig_out) {
4009 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
4013 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
4016 /* spec->multiout.share_spdif = 1; */
4020 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
4030 static struct hda_pcm_stream ca0132_pcm_analog_playback = {
4035 .prepare = ca0132_playback_pcm_prepare,
4036 .cleanup = ca0132_playback_pcm_cleanup,
4037 .get_delay = ca0132_playback_pcm_delay,
4041 static struct hda_pcm_stream ca0132_pcm_analog_capture = {
4046 .prepare = ca0132_capture_pcm_prepare,
4047 .cleanup = ca0132_capture_pcm_cleanup,
4048 .get_delay = ca0132_capture_pcm_delay,
4052 static struct hda_pcm_stream ca0132_pcm_digital_playback = {
4057 .open = ca0132_dig_playback_pcm_open,
4058 .close = ca0132_dig_playback_pcm_close,
4059 .prepare = ca0132_dig_playback_pcm_prepare,
4060 .cleanup = ca0132_dig_playback_pcm_cleanup
4064 static struct hda_pcm_stream ca0132_pcm_digital_capture = {
4070 static int ca0132_build_pcms(struct hda_codec *codec)
4072 struct ca0132_spec *spec = codec->spec;
4073 struct hda_pcm *info;
4075 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
4078 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4079 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4080 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4081 spec->multiout.max_channels;
4082 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4083 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4084 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4086 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
4089 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4090 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4091 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4093 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
4096 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4097 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4098 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4100 if (!spec->dig_out && !spec->dig_in)
4103 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
4106 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4107 if (spec->dig_out) {
4108 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4109 ca0132_pcm_digital_playback;
4110 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4113 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4114 ca0132_pcm_digital_capture;
4115 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4121 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4124 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
4125 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4126 snd_hda_codec_write(codec, pin, 0,
4127 AC_VERB_SET_AMP_GAIN_MUTE,
4130 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4131 snd_hda_codec_write(codec, dac, 0,
4132 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4135 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4138 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
4139 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4140 snd_hda_codec_write(codec, pin, 0,
4141 AC_VERB_SET_AMP_GAIN_MUTE,
4144 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4145 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4148 /* init to 0 dB and unmute. */
4149 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4150 HDA_AMP_VOLMASK, 0x5a);
4151 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4156 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4160 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4161 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4162 snd_hda_override_amp_caps(codec, nid, dir, caps);
4166 * Switch between Digital built-in mic and analog mic.
4168 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4170 struct ca0132_spec *spec = codec->spec;
4173 unsigned int oldval;
4175 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
4177 oldval = stop_mic1(codec);
4178 ca0132_set_vipsource(codec, 0);
4180 /* set DMic input as 2-ch */
4182 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4184 val = spec->dmic_ctl;
4186 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4187 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4189 if (!(spec->dmic_ctl & 0x20))
4190 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4192 /* set AMic input as mono */
4194 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4196 val = spec->dmic_ctl;
4197 /* clear bit7 and bit5 to disable dmic */
4199 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4200 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4202 if (!(spec->dmic_ctl & 0x20))
4203 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4205 ca0132_set_vipsource(codec, 1);
4206 resume_mic1(codec, oldval);
4210 * Initialization for Digital Mic.
4212 static void ca0132_init_dmic(struct hda_codec *codec)
4214 struct ca0132_spec *spec = codec->spec;
4217 /* Setup Digital Mic here, but don't enable.
4218 * Enable based on jack detect.
4221 /* MCLK uses MPIO1, set to enable.
4222 * Bit 2-0: MPIO select
4223 * Bit 3: set to disable
4227 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4228 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4230 /* Data1 uses MPIO3. Data2 not use
4231 * Bit 2-0: Data1 MPIO select
4232 * Bit 3: set disable Data1
4233 * Bit 6-4: Data2 MPIO select
4234 * Bit 7: set disable Data2
4237 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4238 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4240 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4241 * Bit 3-0: Channel mask
4242 * Bit 4: set for 48KHz, clear for 32KHz
4244 * Bit 6: set to select Data2, clear for Data1
4245 * Bit 7: set to enable DMic, clear for AMic
4248 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4249 spec->dmic_ctl = val;
4250 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4251 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4255 * Initialization for Analog Mic 2
4257 static void ca0132_init_analog_mic2(struct hda_codec *codec)
4259 struct ca0132_spec *spec = codec->spec;
4261 mutex_lock(&spec->chipio_mutex);
4262 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4263 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4264 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4265 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4266 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4267 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4268 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4269 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4270 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4271 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4272 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4273 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4274 mutex_unlock(&spec->chipio_mutex);
4277 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4279 struct ca0132_spec *spec = codec->spec;
4282 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
4283 snd_hda_codec_update_widgets(codec);
4285 for (i = 0; i < spec->multiout.num_dacs; i++)
4286 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4288 for (i = 0; i < spec->num_outputs; i++)
4289 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4291 for (i = 0; i < spec->num_inputs; i++) {
4292 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4293 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4298 * Setup default parameters for DSP
4300 static void ca0132_setup_defaults(struct hda_codec *codec)
4302 struct ca0132_spec *spec = codec->spec;
4307 if (spec->dsp_state != DSP_DOWNLOADED)
4310 /* out, in effects + voicefx */
4311 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4312 for (idx = 0; idx < num_fx; idx++) {
4313 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4314 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4315 ca0132_effects[idx].reqs[i],
4316 ca0132_effects[idx].def_vals[i]);
4320 /*remove DSP headroom*/
4322 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4324 /*set speaker EQ bypass attenuation*/
4325 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4327 /* set AMic1 and AMic2 as mono mic */
4329 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4330 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4332 /* set AMic1 as CrystalVoice input */
4334 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4336 /* set WUH source */
4338 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4342 * Initialization of flags in chip
4344 static void ca0132_init_flags(struct hda_codec *codec)
4346 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4347 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4348 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4349 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4350 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4351 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4355 * Initialization of parameters in chip
4357 static void ca0132_init_params(struct hda_codec *codec)
4359 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4360 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4363 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4365 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4366 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4367 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4368 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4369 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4370 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4372 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4373 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4374 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4377 static bool ca0132_download_dsp_images(struct hda_codec *codec)
4379 bool dsp_loaded = false;
4380 const struct dsp_image_seg *dsp_os_image;
4381 const struct firmware *fw_entry;
4383 if (reject_firmware(&fw_entry, EFX_FILE, codec->card->dev) != 0)
4386 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
4387 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
4388 codec_err(codec, "ca0132 DSP load image failed\n");
4392 dsp_loaded = dspload_wait_loaded(codec);
4395 release_firmware(fw_entry);
4400 static void ca0132_download_dsp(struct hda_codec *codec)
4402 struct ca0132_spec *spec = codec->spec;
4404 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4408 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
4409 return; /* don't retry failures */
4411 chipio_enable_clocks(codec);
4412 spec->dsp_state = DSP_DOWNLOADING;
4413 if (!ca0132_download_dsp_images(codec))
4414 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4416 spec->dsp_state = DSP_DOWNLOADED;
4418 if (spec->dsp_state == DSP_DOWNLOADED)
4419 ca0132_set_dsp_msr(codec, true);
4422 static void ca0132_process_dsp_response(struct hda_codec *codec,
4423 struct hda_jack_callback *callback)
4425 struct ca0132_spec *spec = codec->spec;
4427 codec_dbg(codec, "ca0132_process_dsp_response\n");
4428 snd_hda_power_up_pm(codec);
4429 if (spec->wait_scp) {
4430 if (dspio_get_response_data(codec) >= 0)
4434 dspio_clear_response_queue(codec);
4435 snd_hda_power_down_pm(codec);
4438 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4440 struct ca0132_spec *spec = codec->spec;
4441 struct hda_jack_tbl *tbl;
4443 /* Delay enabling the HP amp, to let the mic-detection
4444 * state machine run.
4446 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
4448 tbl->block_report = 1;
4449 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
4452 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4454 ca0132_select_mic(codec);
4457 static void ca0132_init_unsol(struct hda_codec *codec)
4459 struct ca0132_spec *spec = codec->spec;
4460 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
4461 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
4463 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
4464 ca0132_process_dsp_response);
4471 /* Sends before DSP download. */
4472 static struct hda_verb ca0132_base_init_verbs[] = {
4473 /*enable ct extension*/
4474 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4479 static struct hda_verb ca0132_base_exit_verbs[] = {
4481 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4482 /*disable ct extension*/
4483 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4487 /* Other verbs tables. Sends after DSP download. */
4488 static struct hda_verb ca0132_init_verbs0[] = {
4489 /* chip init verbs */
4490 {0x15, 0x70D, 0xF0},
4491 {0x15, 0x70E, 0xFE},
4492 {0x15, 0x707, 0x75},
4493 {0x15, 0x707, 0xD3},
4494 {0x15, 0x707, 0x09},
4495 {0x15, 0x707, 0x53},
4496 {0x15, 0x707, 0xD4},
4497 {0x15, 0x707, 0xEF},
4498 {0x15, 0x707, 0x75},
4499 {0x15, 0x707, 0xD3},
4500 {0x15, 0x707, 0x09},
4501 {0x15, 0x707, 0x02},
4502 {0x15, 0x707, 0x37},
4503 {0x15, 0x707, 0x78},
4504 {0x15, 0x53C, 0xCE},
4505 {0x15, 0x575, 0xC9},
4506 {0x15, 0x53D, 0xCE},
4507 {0x15, 0x5B7, 0xC9},
4508 {0x15, 0x70D, 0xE8},
4509 {0x15, 0x70E, 0xFE},
4510 {0x15, 0x707, 0x02},
4511 {0x15, 0x707, 0x68},
4512 {0x15, 0x707, 0x62},
4513 {0x15, 0x53A, 0xCE},
4514 {0x15, 0x546, 0xC9},
4515 {0x15, 0x53B, 0xCE},
4516 {0x15, 0x5E8, 0xC9},
4517 {0x15, 0x717, 0x0D},
4518 {0x15, 0x718, 0x20},
4522 static void ca0132_init_chip(struct hda_codec *codec)
4524 struct ca0132_spec *spec = codec->spec;
4529 mutex_init(&spec->chipio_mutex);
4531 spec->cur_out_type = SPEAKER_OUT;
4532 spec->cur_mic_type = DIGITAL_MIC;
4533 spec->cur_mic_boost = 0;
4535 for (i = 0; i < VNODES_COUNT; i++) {
4536 spec->vnode_lvol[i] = 0x5a;
4537 spec->vnode_rvol[i] = 0x5a;
4538 spec->vnode_lswitch[i] = 0;
4539 spec->vnode_rswitch[i] = 0;
4543 * Default states for effects are in ca0132_effects[].
4545 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4546 for (i = 0; i < num_fx; i++) {
4547 on = (unsigned int)ca0132_effects[i].reqs[0];
4548 spec->effects_switch[i] = on ? 1 : 0;
4551 spec->voicefx_val = 0;
4552 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4553 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4555 #ifdef ENABLE_TUNING_CONTROLS
4556 ca0132_init_tuning_defaults(codec);
4560 static void ca0132_exit_chip(struct hda_codec *codec)
4562 /* put any chip cleanup stuffs here. */
4564 if (dspload_is_loaded(codec))
4568 static int ca0132_init(struct hda_codec *codec)
4570 struct ca0132_spec *spec = codec->spec;
4571 struct auto_pin_cfg *cfg = &spec->autocfg;
4574 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
4575 spec->dsp_state = DSP_DOWNLOAD_INIT;
4576 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
4578 snd_hda_power_up_pm(codec);
4580 ca0132_init_unsol(codec);
4582 ca0132_init_params(codec);
4583 ca0132_init_flags(codec);
4584 snd_hda_sequence_write(codec, spec->base_init_verbs);
4585 ca0132_download_dsp(codec);
4586 ca0132_refresh_widget_caps(codec);
4587 ca0132_setup_defaults(codec);
4588 ca0132_init_analog_mic2(codec);
4589 ca0132_init_dmic(codec);
4591 for (i = 0; i < spec->num_outputs; i++)
4592 init_output(codec, spec->out_pins[i], spec->dacs[0]);
4594 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4596 for (i = 0; i < spec->num_inputs; i++)
4597 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4599 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4601 snd_hda_sequence_write(codec, spec->chip_init_verbs);
4602 snd_hda_sequence_write(codec, spec->spec_init_verbs);
4604 ca0132_select_out(codec);
4605 ca0132_select_mic(codec);
4607 snd_hda_jack_report_sync(codec);
4609 snd_hda_power_down_pm(codec);
4614 static void ca0132_free(struct hda_codec *codec)
4616 struct ca0132_spec *spec = codec->spec;
4618 cancel_delayed_work_sync(&spec->unsol_hp_work);
4619 snd_hda_power_up(codec);
4620 snd_hda_sequence_write(codec, spec->base_exit_verbs);
4621 ca0132_exit_chip(codec);
4622 snd_hda_power_down(codec);
4623 kfree(spec->spec_init_verbs);
4628 static int ca0132_suspend(struct hda_codec *codec)
4630 struct ca0132_spec *spec = codec->spec;
4632 cancel_delayed_work_sync(&spec->unsol_hp_work);
4637 static struct hda_codec_ops ca0132_patch_ops = {
4638 .build_controls = ca0132_build_controls,
4639 .build_pcms = ca0132_build_pcms,
4640 .init = ca0132_init,
4641 .free = ca0132_free,
4642 .unsol_event = snd_hda_jack_unsol_event,
4644 .suspend = ca0132_suspend,
4648 static void ca0132_config(struct hda_codec *codec)
4650 struct ca0132_spec *spec = codec->spec;
4651 struct auto_pin_cfg *cfg = &spec->autocfg;
4653 spec->dacs[0] = 0x2;
4654 spec->dacs[1] = 0x3;
4655 spec->dacs[2] = 0x4;
4657 spec->multiout.dac_nids = spec->dacs;
4658 spec->multiout.num_dacs = 3;
4659 spec->multiout.max_channels = 2;
4661 if (spec->quirk == QUIRK_ALIENWARE) {
4662 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
4663 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
4665 spec->num_outputs = 2;
4666 spec->out_pins[0] = 0x0b; /* speaker out */
4667 spec->out_pins[1] = 0x0f;
4668 spec->shared_out_nid = 0x2;
4669 spec->unsol_tag_hp = 0x0f;
4671 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4672 spec->adcs[1] = 0x8; /* analog mic2 */
4673 spec->adcs[2] = 0xa; /* what u hear */
4675 spec->num_inputs = 3;
4676 spec->input_pins[0] = 0x12;
4677 spec->input_pins[1] = 0x11;
4678 spec->input_pins[2] = 0x13;
4679 spec->shared_mic_nid = 0x7;
4680 spec->unsol_tag_amic1 = 0x11;
4682 spec->num_outputs = 2;
4683 spec->out_pins[0] = 0x0b; /* speaker out */
4684 spec->out_pins[1] = 0x10; /* headphone out */
4685 spec->shared_out_nid = 0x2;
4686 spec->unsol_tag_hp = spec->out_pins[1];
4688 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4689 spec->adcs[1] = 0x8; /* analog mic2 */
4690 spec->adcs[2] = 0xa; /* what u hear */
4692 spec->num_inputs = 3;
4693 spec->input_pins[0] = 0x12;
4694 spec->input_pins[1] = 0x11;
4695 spec->input_pins[2] = 0x13;
4696 spec->shared_mic_nid = 0x7;
4697 spec->unsol_tag_amic1 = spec->input_pins[0];
4700 spec->dig_out = 0x05;
4701 spec->multiout.dig_out_nid = spec->dig_out;
4702 cfg->dig_out_pins[0] = 0x0c;
4704 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4705 spec->dig_in = 0x09;
4706 cfg->dig_in_pin = 0x0e;
4707 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4711 static int ca0132_prepare_verbs(struct hda_codec *codec)
4713 /* Verbs + terminator (an empty element) */
4714 #define NUM_SPEC_VERBS 4
4715 struct ca0132_spec *spec = codec->spec;
4717 spec->chip_init_verbs = ca0132_init_verbs0;
4718 spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL);
4719 if (!spec->spec_init_verbs)
4722 /* HP jack autodetection */
4723 spec->spec_init_verbs[0].nid = spec->unsol_tag_hp;
4724 spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4725 spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp;
4727 /* MIC1 jack autodetection */
4728 spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1;
4729 spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4730 spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1;
4733 spec->spec_init_verbs[2].nid = 0x0b;
4734 spec->spec_init_verbs[2].param = 0x78D;
4735 spec->spec_init_verbs[2].verb = 0x00;
4737 /* Previously commented configuration */
4739 spec->spec_init_verbs[3].nid = 0x0b;
4740 spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE;
4741 spec->spec_init_verbs[3].verb = 0x02;
4743 spec->spec_init_verbs[4].nid = 0x10;
4744 spec->spec_init_verbs[4].param = 0x78D;
4745 spec->spec_init_verbs[4].verb = 0x02;
4747 spec->spec_init_verbs[5].nid = 0x10;
4748 spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE;
4749 spec->spec_init_verbs[5].verb = 0x02;
4752 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
4756 static int patch_ca0132(struct hda_codec *codec)
4758 struct ca0132_spec *spec;
4760 const struct snd_pci_quirk *quirk;
4762 codec_dbg(codec, "patch_ca0132\n");
4764 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4768 spec->codec = codec;
4770 codec->patch_ops = ca0132_patch_ops;
4771 codec->pcm_format_first = 1;
4772 codec->no_sticky_stream = 1;
4774 /* Detect codec quirk */
4775 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
4777 spec->quirk = quirk->value;
4779 spec->quirk = QUIRK_NONE;
4781 spec->dsp_state = DSP_DOWNLOAD_INIT;
4782 spec->num_mixers = 1;
4783 spec->mixers[0] = ca0132_mixer;
4785 spec->base_init_verbs = ca0132_base_init_verbs;
4786 spec->base_exit_verbs = ca0132_base_exit_verbs;
4788 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4790 ca0132_init_chip(codec);
4792 ca0132_config(codec);
4794 err = ca0132_prepare_verbs(codec);
4798 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4808 static struct hda_device_id snd_hda_id_ca0132[] = {
4809 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
4812 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
4814 MODULE_LICENSE("GPL");
4815 MODULE_DESCRIPTION("Creative Sound Core3D codec");
4817 static struct hda_codec_driver ca0132_driver = {
4818 .id = snd_hda_id_ca0132,
4821 module_hda_codec_driver(ca0132_driver);