2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #ifndef __INTR_API_H__
36 #define __INTR_API_H__
39 * Interrupt handler, for application-managed interrupts.
40 * When an interrupt occurs, it is automatically disabled.
41 * See A_WMAC_INTR_ATTACH() and A_MBOX_INTR_ATTACH().
43 * If a handler returns A_HANDLER_DONE, the interrupt is
44 * re-enabled. The OS calls the handler next time service
45 * is required. This is the normal case for a handler.
47 * If a handler returns A_HANDLER_YIELD, the interrupt
48 * remains masked. The handler is called again when
49 * it is "convenient". This gives the OS an opportunity
50 * to run other code/handlers. A handler should return
51 * A_HANDLER_YIELD if it might dominate the CPU for too
54 * If a handler returns A_HANDLER_NOENABLE, the interrupt
55 * remains disabled. It is up to the application to re-enable
56 * the interrupt (via A_*_INTR_UNMASK) when it's appropriate.
58 * Note that many combinations of interrupt functions and
59 * interrupt vectors are NOT supported: Callers should use
60 * only the macros defined in cmnos_api.h to access the
63 #include "cmnos_api.h"
65 typedef uint32_t A_old_intr_t;
67 //////////////////////////////////////////////////////////////////
68 // this is copied from mercury/cmnos_xtensa.h
70 * These are CMNOS interrupt manifest constants.
71 * They have specially-chosen values that align with hardware and or
72 * operating system values (see cmnos_interrupt_info).
74 #if defined(__XTENSA__)
76 * Enumeration of low and medium priority interrupt numbers
77 * which match the CPU hardware configuration:
80 /* XTensa Level 1 interrupt */
81 #define A_INUM_SOFTWARE 0 /* currently unused */
83 /* XTensa Level2 interrupts */
84 #define A_INUM_XTTIMER 1 /* currently unused */
86 #define A_INUM_TBD_0 2 /* TBD */
87 #define A_INUM_CPU_WDT 3 /* RST_CPU watchodg interrupt */
88 #define A_INUM_GMAC_DMA 4 /* GMAC DMA interrupt */
89 #define A_INUM_GMAC_MDIO 5 /* GMAC MDIO interrupt */
90 #define A_INUM_HOST_DMA 6 /* HOST DMA */
91 #define A_INUM_CPU_GEN_TIMER 7 /* CPU general timer */
92 #define A_INUM_TBD_8 8 /* TBD */
93 #define A_INUM_TBD_9 9 /* TBD */
94 #define A_INUM_USB_CTRL 10 /* USB core control */
95 #define A_INUM_USB_DMA 11 /* USB DMA */
96 #define A_INUM_TBD_12 12 /* TBD */
97 #define A_INUM_TBD_13 13 /* TBD */
98 #define A_INUM_EMUX_CPU 14 /* EMUX CPU */
99 #define A_INUM_GPIO_CPU 15 /* GPIO CPU interrupt */
100 #define A_INUM_TBD_16 16 /* TBD */
101 #define A_INUM_PCIE_CPU 17 /* CPU PCIE interrupt */
102 #define A_INUM_RST_CPU_NMI 18 /* RST CPU nmi interrupt */
104 /* Number of interrupts that map directly into CPU/hal interrupt bits. */
105 #define NUM_DIRECT_INTR 19
108 //////////////////////////////////////////////////////////////////
110 #define CMNOS_IMASK_XTTIMER (1<<A_INUM_XTTIMER)
111 #define CMNOS_IMASK_USB_CTRL (1<<A_INUM_USB_CTRL)
112 #define CMNOS_IMASK_GMAC_DMA (1<<A_INUM_GMAC_DMA)
113 #define CMNOS_IMASK_GMAC_MDIO (1<<A_INUM_GMAC_MDIO)
114 #define CMNOS_IMASK_HOST_DMA (1<<A_INUM_HOST_DMA)
115 #define CMNOS_IMASK_CPU_GEN_TIMER (1<<A_INUM_CPU_GEN_TIMER)
117 #define CMNOS_IMASK_EMUX_CPU (1<<A_INUM_EMUX_CPU)
118 #define CMNOS_IMASK_GPIO_CPU (1<<A_INUM_GPIO_CPU)
119 #define CMNOS_IMASK_PCIE_CPU (1<<A_INUM_PCIE_CPU)
120 #define CMNOS_IMASK_RST_CPU_NMI (1<<A_INUM_RST_CPU_NMI)
124 typedef enum inum_intr {
129 /* add intr above here */
133 //////////////////////////////////////////////////////////////////
136 * An interrupt handler, which is a function called in response
137 * to a hardware interrupt, possibly as a Delayed Service Routine.
139 typedef int (* A_handler_t)(void *);
140 /* Return values from a handler/DSR, A_handler_t */
141 #define A_HANDLER_NOENABLE 0 /* do not re-enable interrupts */
142 #define A_HANDLER_DONE 1 /* all intrs handled, call on next intr */
143 #define A_HANDLER_YIELD 2 /* leave intrs disabled and
144 call back later regardless of intr state */
147 * An Interrupt Service Routine, which must be called
148 * directly in interrupt context (not delayed), and which
149 * must be very small and may not have access to all OS
150 * functions. These are for use only when interrupt
151 * latency is critical; otherwise, an A_handler_t ("dsr")
154 typedef uint32_t (* A_isr_t)(void *);
155 /* Return values from an ISR */
156 #if defined(CYG_ISR_HANDLED)
157 #define A_ISR_HANDLED CYG_ISR_HANDLED
158 #define A_ISR_CALL_DSR CYG_ISR_CALL_DSR
160 #define A_ISR_HANDLED 1
161 #define A_ISR_CALL_DSR 2
165 void (*_intr_init)(void);
166 uint32_t (* _intr_invoke_isr)(uint32_t inum);
167 A_old_intr_t(* _intr_disable)(void);
168 void (* _intr_restore)(A_old_intr_t);
170 void (* _intr_mask_inum)(uint32_t inum);
171 void (* _intr_unmask_inum)(uint32_t inum);
172 void (* _intr_attach_isr)(uint32_t inum, A_isr_t isr, void *arg);
174 BOOLEAN (*_intr_dsrs_pending)(void);
175 void (* _intr_handle_pending_dsrs)(void);
176 uint32_t (* _intr_nmi)(void *);
178 /* Low-level interrupt access, intended for use by OS modules */
179 unsigned int (* _get_intrenable)(void);
180 void (* _set_intrenable)(unsigned int);
181 unsigned int (* _get_intrpending)(void);
182 void (* _unblock_all_intrlvl)(void);
184 #endif /* __INTR_API_H__ */