2 * xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
4 * (In previous releases, these were defined in specreg.h, a generated file.
5 * This file is not generated, ie. it is processor configuration independent.)
8 /* $Id: //depot/rel/BadgerPass/Xtensa/OS/include/xtensa/corebits.h#3 $ */
11 * Copyright (c) 2005-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
12 * These coded instructions, statements, and computer programs are the
13 * copyrighted works and confidential proprietary information of Tensilica Inc.
14 * They may not be modified, copied, reproduced, distributed, or disclosed to
15 * third parties in any manner, medium, or form, in whole or in part, without
16 * the prior written consent of Tensilica Inc.
19 #ifndef XTENSA_COREBITS_H
20 #define XTENSA_COREBITS_H
22 /* EXCCAUSE register fields: */
23 #define EXCCAUSE_EXCCAUSE_SHIFT 0
24 #define EXCCAUSE_EXCCAUSE_MASK 0x3F
25 /* EXCCAUSE register values: */
27 * General Exception Causes
28 * (values of EXCCAUSE special register set by general exceptions,
29 * which vector to the user, kernel, or double-exception vectors).
31 #define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */
32 #define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */
33 #define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */
34 # define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */
35 #define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
36 # define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */
37 #define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
38 # define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */
39 #define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
40 #define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
41 #define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */
42 #define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
43 #define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
45 #define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
46 #define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
47 #define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
48 #define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */
49 #define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
50 #define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
51 #define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
52 /* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */
53 #define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */
55 #define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
56 #define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
57 #define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
58 /* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */
59 #define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */
60 #define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */
62 #define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */
63 #define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */
64 #define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */
65 #define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */
66 #define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */
67 #define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */
68 #define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */
69 #define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */
70 #define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */
71 /*#define EXCCAUSE_FLOATING_POINT 40*/ /* Floating Point Exception (not implemented) */
74 /* PS register fields: */
75 #define PS_WOE_SHIFT 18
76 #define PS_WOE_MASK 0x00040000
77 #define PS_WOE PS_WOE_MASK
78 #define PS_CALLINC_SHIFT 16
79 #define PS_CALLINC_MASK 0x00030000
80 #define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
81 #define PS_OWB_SHIFT 8
82 #define PS_OWB_MASK 0x00000F00
83 #define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
84 #define PS_RING_SHIFT 6
85 #define PS_RING_MASK 0x000000C0
86 #define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
88 #define PS_UM_MASK 0x00000020
89 #define PS_UM PS_UM_MASK
90 #define PS_EXCM_SHIFT 4
91 #define PS_EXCM_MASK 0x00000010
92 #define PS_EXCM PS_EXCM_MASK
93 #define PS_INTLEVEL_SHIFT 0
94 #define PS_INTLEVEL_MASK 0x0000000F
95 #define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
96 /* Backward compatibility (deprecated): */
97 #define PS_PROGSTACK_SHIFT PS_UM_SHIFT
98 #define PS_PROGSTACK_MASK PS_UM_MASK
99 #define PS_PROG_SHIFT PS_UM_SHIFT
100 #define PS_PROG_MASK PS_UM_MASK
101 #define PS_PROG PS_UM
103 /* DBREAKCn register fields: */
104 #define DBREAKC_MASK_SHIFT 0
105 #define DBREAKC_MASK_MASK 0x0000003F
106 #define DBREAKC_LOADBREAK_SHIFT 30
107 #define DBREAKC_LOADBREAK_MASK 0x40000000
108 #define DBREAKC_STOREBREAK_SHIFT 31
109 #define DBREAKC_STOREBREAK_MASK 0x80000000
111 /* DEBUGCAUSE register fields: */
112 #define DEBUGCAUSE_DEBUGINT_SHIFT 5
113 #define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
114 #define DEBUGCAUSE_BREAKN_SHIFT 4
115 #define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
116 #define DEBUGCAUSE_BREAK_SHIFT 3
117 #define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
118 #define DEBUGCAUSE_DBREAK_SHIFT 2
119 #define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
120 #define DEBUGCAUSE_IBREAK_SHIFT 1
121 #define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
122 #define DEBUGCAUSE_ICOUNT_SHIFT 0
123 #define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
125 /* MESR register fields: */
126 #define MESR_MEME 0x00000001 /* memory error */
127 #define MESR_MEME_SHIFT 0
128 #define MESR_DME 0x00000002 /* double memory error */
129 #define MESR_DME_SHIFT 1
130 #define MESR_RCE 0x00000010 /* recorded memory error */
131 #define MESR_RCE_SHIFT 4
133 #define MESR_LCE_SHIFT ?
135 #define MESR_ERRENAB 0x00000100
136 #define MESR_ERRENAB_SHIFT 8
137 #define MESR_ERRTEST 0x00000200
138 #define MESR_ERRTEST_SHIFT 9
139 #define MESR_DATEXC 0x00000400
140 #define MESR_DATEXC_SHIFT 10
141 #define MESR_INSEXC 0x00000800
142 #define MESR_INSEXC_SHIFT 11
143 #define MESR_WAYNUM_SHIFT 16
144 #define MESR_ACCTYPE_SHIFT 20
145 #define MESR_MEMTYPE_SHIFT 24
146 #define MESR_ERRTYPE_SHIFT 30
149 #endif /*XTENSA_COREBITS_H*/