1 #ifndef SHARED_MEMORY_H_
2 #define SHARED_MEMORY_H_
4 /* SHM (Shared Memory) offsets */
6 /* Host-side routing values for the SHM.
7 * This is only useful for the initvals */
8 #define HOST_SHM_UCODE 0
9 #define HOST_SHM_SHARED 1
10 #define HOST_SHM_SCRATCH 2
11 #define HOST_SHM_IHR 3
12 #define HOST_SHM_RCMTA 4
14 /* Macro to convert a host-SHM-address to a microcode-SHM-address.
15 * This also asserts that the address is word aligned. */
16 #define SHM(address) (((address) / 2) + \
17 (%assert((address & 1) == 0)))
19 /* Macro to convert a byte-offset into a microcode-SHM-word-offset.
20 * This does the same as SHM(), but is used to mark offsets that are not
21 * based on absolute zero, but relative. */
22 #define SHM_OFFSET(offset) SHM(offset)
24 /* BEGIN ABI: Start of the driver ABI definitions */
27 #define SHM_PREAMBLE_DURATION SHM(0x00C) /* duration of the preamble */
28 #define SHM_PCTLWDPOS SHM(0x008)
29 #define SHM_WLCOREREV SHM(0x016) /* 802.11 core revision */
30 #define SHM_MAXPDULEN SHM(0x020) /* MAX PDU LENGTH, initialized by initvals */
31 #define SHM_TXPWRCUR SHM(0x032) /* Current tx power */
32 #define SHM_RXPADOFF SHM(0x034) /* RX Padding data offset (PIO only) */
33 #define SHM_TBL_OFF2DUR SHM(0x038) /* Offset to duration in second level rate tables */
34 #define SHM_PHYVER SHM(0x050) /* PHY version */
35 #define SHM_PHYTYPE SHM(0x052) /* PHY type */
36 #define SHM_ANTSWAP SHM(0x05C) /* Antenna swap threshold */
37 #define SHM_HF_LO SHM(0x05E) /* Hostflags for ucode options (low) */
38 #define SHM_HF_LO_ANTDIVHELP 0 /* bit0: ucode antenna div helper */
39 #define SHM_HF_LO_SYMW 1 /* bit1: G-PHY SYM workaround */
40 #define SHM_HF_LO_RXPULLW 2 /* bit2: RX pullup workaround */
41 #define SHM_HF_LO_CCKBOOST 3 /* bit3: 4dB CCK power boost (exclusive with OFDM boost) */
42 #define SHM_HF_LO_BTCOEX 4 /* bit4: Bluetooth coexistence */
43 #define SHM_HF_LO_GDCW 5 /* bit5: G-PHY DC canceller filter bw workaround */
44 #define SHM_HF_LO_OFDMPABOOST 6 /* bit6: Enable PA gain boost for OFDM */
45 #define SHM_HF_LO_ACPR 7 /* bit7: Disable for Japan, channel 14 */
46 #define SHM_HF_LO_EDCF 8 /* bit8: on if WME and MAC suspended */
47 #define SHM_HF_LO_TSSIRPSMW 9 /* bit9: TSSI reset PSM ucode workaround */
48 #define SHM_HF_LO_20IN40IQW 9 /* bit9: 20 in 40 MHz I/Q workaround (rev >= 13 only) */
49 #define SHM_HF_LO_DSCRQ 10 /* bit10: Disable slow clock request in ucode */
50 #define SHM_HF_LO_ACIW 11 /* bit11: ACI workaround: shift bits by 2 on PHY CRS */
51 #define SHM_HF_LO_2060W 12 /* bit12: 2060 radio workaround */
52 #define SHM_HF_LO_RADARW 13 /* bit13: Radar workaround */
53 #define SHM_HF_LO_USEDEFKEYS 14 /* bit14: Enable use of default keys */
54 #define SHM_HF_LO_AFTERBURNER 15 /* bit15: Afterburner enabled */
55 #define SHM_HF_MI SHM(0x060) /* Hostflags for ucode options (middle) */
56 #define SHM_HF_MI_BT4PRIOCOEX 0 /* bit0: Bluetooth 4-priority coexistence */
57 #define SHM_HF_MI_FWKUP 1 /* bit1: Fast wake-up ucode */
58 #define SHM_HF_MI_VCORECALC 2 /* bit2: Force VCO recalculation when powering up synthpu */
59 #define SHM_HF_MI_PCISCW 3 /* bit3: PCI slow clock workaround */
60 #define SHM_HF_MI_4318TSSI 5 /* bit5: 4318 TSSI */
61 #define SHM_HF_MI_FBCMCFIFO 6 /* bit6: Flush bcast/mcast FIFO immediately */
62 #define SHM_HF_MI_HWPCTL 7 /* bit7: Enable hardware power control */
63 #define SHM_HF_MI_BTCOEXALT 8 /* bit8: Bluetooth coexistence in alternate pins */
64 #define SHM_HF_MI_TXBTCHECK 9 /* bit9: Bluetooth check during transmission */
65 #define SHM_HF_MI_SKCFPUP 10 /* bit10: Skip CFP update */
66 #define SHM_HF_MI_N40W 11 /* bit11: N PHY 40 MHz workaround (rev >= 13 only) */
67 #define SHM_HF_MI_ANTSEL 13 /* bit13: Antenna selection (for testing antenna div.) */
68 #define SHM_HF_MI_BT3COEXT 13 /* bit13: Bluetooth 3-wire coexistence (rev >= 13 only) */
69 #define SHM_HF_MI_BTCANT 14 /* bit14: Bluetooth coexistence (antenna mode) (rev >= 13 only) */
70 #define SHM_HF_HI SHM(0x062) /* Hostflags for ucode options (high) */
71 #define SHM_HF_HI_ANTSELEN 0 /* bit0: Antenna selection enabled (rev >= 13 only) */
72 #define SHM_HF_HI_ANTSELMODE 1 /* bit1: Antenna selection mode (rev >= 13 only) */
73 #define SHM_HF_HI_MLADVW 4 /* bit4: N PHY ML ADV workaround (rev >= 13 only) */
74 #define SHM_HF_HI_PR45960W 11 /* bit11: PR 45960 workaround (rev >= 13 only) */
75 #define SHM_RFATT SHM(0x064) /* Current radio attenuation value */
76 #define SHM_RADAR SHM(0x066) /* Radar register */
77 #define SHM_PHYTXNOI SHM(0x06E) /* PHY noise directly after TX (lower 8bit only) */
78 #define SHM_RFRXSP1 SHM(0x072) /* RF RX SP Register 1 */
79 #define SHM_RX_TIME_WORD3 SHM(0x078)
80 #define SHM_RX_TIME_WORD2 SHM(0x07A)
81 #define SHM_RX_TIME_WORD1 SHM(0x07C)
82 #define SHM_RX_TIME_WORD0 SHM(0x07E)
83 #define SHM_CHAN SHM(0x0A0) /* Current channel (low 8bit only) */
84 #define SHM_GCLASSCTL SHM(0x0A6) /* Value for the G-PHY classify control register */
85 #define SHM_BCMCFIFOID SHM(0x108) /* Last posted cookie to the bcast/mcast FIFO */
87 /* TSSI information */
88 #define SHM_TSSI_CCK_LO SHM(0x058) /* TSSI for the last 4 CCK frames (low) */
89 #define SHM_TSSI_CCK_HI SHM(0x05A) /* TSSI for the last 4 CCK frames (high) */
90 #define SHM_TSSI_OFDM_A_LO SHM(0x068) /* TSSI for the last 4 OFDM (A) frames (low) */
91 #define SHM_TSSI_OFDM_A_HI SHM(0x06A) /* TSSI for the last 4 OFDM (A) frames (high) */
92 #define SHM_TSSI_OFDM_G_LO SHM(0x070) /* TSSI for the last 4 OFDM (G) frames (low) */
93 #define SHM_TSSI_OFDM_G_HI SHM(0x072) /* TSSI for the last 4 OFDM (G) frames (high) */
95 /* TX FIFO variables */
96 #define SHM_TXFIFO_SIZE01 SHM(0x098) /* TX FIFO size for FIFO 0 (low) and 1 (high) */
97 #define SHM_TXFIFO_SIZE23 SHM(0x09A) /* TX FIFO size for FIFO 2 and 3 */
98 #define SHM_TXFIFO_SIZE45 SHM(0x09C) /* TX FIFO size for FIFO 4 and 5 */
99 #define SHM_TXFIFO_SIZE67 SHM(0x09E) /* TX FIFO size for FIFO 6 and 7 */
101 /* Background noise */
102 #define SHM_JSSI0 SHM(0x088) /* Measure JSSI 0 */
103 #define SHM_JSSI1 SHM(0x08A) /* Measure JSSI 1 */
104 #define SHM_JSSIAUX SHM(0x08C) /* Measure JSSI AUX */
107 #define SHM_DEFAULTIV SHM(0x03C) /* Default IV location */
108 #define SHM_NRRXTRANS SHM(0x03E) /* # of soft RX transmitter addresses (max 8) */
109 #define SHM_KTP SHM(0x056) /* Key table pointer */
110 #define SHM_TKIP_P1KEYS SHM(0x2E0) /* TKIP Phase 1 keys. */
111 #define SHM_KEYIDXBLOCK SHM(0x5D4) /* Key index/algorithm block. */
114 #define SHM_EDCFSTAT SHM(0x00E) /* EDCF status */
115 #define SHM_TXFCUR SHM(0x030) /* TXF current index */
116 #define SHM_EDCFQ SHM(0x240) /* EDCF Q info */
117 #define SHM_EDCFQCUR SHM(0x260) /* EDCF info for the current (the only one!) queue */
118 #define SHM_EDCFQ_TXOP SHM_OFFSET(0x00)
119 #define SHM_EDCFQ_CWMIN SHM_OFFSET(0x02)
120 #define SHM_EDCFQ_CWMAX SHM_OFFSET(0x04)
121 #define SHM_EDCFQ_CWCUR SHM_OFFSET(0x06)
122 #define SHM_EDCFQ_AIFS SHM_OFFSET(0x08)
123 #define SHM_EDCFQ_BSLOTS SHM_OFFSET(0x0A)
124 #define SHM_EDCFQ_REGGAP SHM_OFFSET(0x0C)
125 #define SHM_EDCFQ_STATUS SHM_OFFSET(0x0E) /* Informations about retries */
127 /* Powersave mode related variables */
128 #define SHM_SLOTT SHM(0x010) /* Slot time */
129 #define SHM_DTIMPER SHM(0x012) /* DTIM period */
130 #define SHM_NOSLPZNATDTIM SHM(0x04C) /* NOSLPZNAT DTIM */
132 /* Beacon/AP variables */
133 #define SHM_BTL0 SHM(0x018) /* Beacon template length 0 */
134 #define SHM_BTL1 SHM(0x01A) /* Beacon template length 1 */
135 #define SHM_BTSFOFF SHM(0x01C) /* Beacon TSF offset */
136 #define SHM_TIMBPOS SHM(0x01E) /* TIM B position in beacon */
137 #define SHM_MCASTCOOKIE SHM(0x0A8) /* Last bcast/mcast frame ID */
138 #define SHM_SFFBLIM SHM(0x044) /* Short frame fallback retry limit */
139 #define SHM_LFFBLIM SHM(0x046) /* Long frame fallback retry limit */
140 #define SHM_BEACPHYCTL SHM(0x054) /* Beacon PHY TX control word (see PHY TX control) */
141 #define SHM_EXTNPHYCTL SHM(0x0B0) /* Extended bytes for beacon PHY control (N) */
143 /* ACK/CTS control */
144 #define SHM_ACKCTSPHYCTL SHM(0x022) /* ACK/CTS PHY control word (see PHY TX control) */
146 /* Probe response variables */
147 #define SHM_PRSSID SHM(0x160) /* Probe Response SSID */
148 #define SHM_PRSSIDLEN SHM(0x048) /* Probe Response SSID length */
149 #define SHM_PRTLEN SHM(0x04A) /* Probe Response template length */
150 #define SHM_PRMAXTIME SHM(0x074) /* Probe Response max time */
151 #define SHM_PRPHYCTL SHM(0x188) /* Probe Response PHY TX control word */
154 #define SHM_OFDMDIRECT SHM(0x1C0) /* Pointer to OFDM direct map */
155 #define SHM_OFDMBASIC SHM(0x1E0) /* Pointer to OFDM basic rate map */
156 #define SHM_CCKDIRECT SHM(0x200) /* Pointer to CCK direct map */
157 #define SHM_CCKBASIC SHM(0x220) /* Pointer to CCK basic rate map */
159 /* Microcode soft registers */
160 #define SHM_UCODEREV SHM(0x000) /* Microcode revision */
161 #define SHM_UCODEPATCH SHM(0x002) /* Microcode patchlevel */
162 #define SHM_UCODEDATE SHM(0x004) /* Microcode date */
163 #define SHM_UCODETIME SHM(0x006) /* Microcode time */
164 #define SHM_UCODESTAT SHM(0x040) /* Microcode debug status code */
165 #define SHM_UCODESTAT_INVALID 0
166 #define SHM_UCODESTAT_INIT 1
167 #define SHM_UCODESTAT_ACTIVE 2
168 #define SHM_UCODESTAT_SUSP 3 /* suspended */
169 #define SHM_UCODESTAT_SLEEP 4 /* asleep (PS) */
170 #define SHM_MAXBFRAMES SHM(0x080) /* Maximum number of frames in a burst */
171 #define SHM_SPUWKUP SHM(0x094) /* pre-wakeup for synth PU in us */
172 #define SHM_PRETBTT SHM(0x096) /* pre-TBTT in us */
174 #define SHM_CURMOD SHM(0x7FC) /* modulation used by the current rx or tx frame */
175 #define SHM_TXHEADER SHM(0x83C) /* start of the tx header buffer in shm */
176 #define SHM_RXHEADER SHM(0xA08) /* start of the tx header buffer in shm */
178 #define SHM_BEACON_TIM_PTR SHM(0xAB0) /* temporary memory buffer for beacon analysis */
180 #define SHM_BCNVAL0 SHM(0x65C) /* Values within second level tables used for beacon */
181 #define SHM_BCNVAL1 SHM(0x6FC) /* Values within second level tables used for beacon */
183 /* Received frame header fields */
185 #define RX_FRAME_PLCP_0 SHM_OFFSET(0x00)
186 #define RX_FRAME_PLCP_1 SHM_OFFSET(0x02)
187 #define RX_FRAME_PLPC_2 SHM_OFFSET(0x04)
188 #define RX_FRAME_FC SHM_OFFSET(0x06)
189 #define RX_FRAME_DURATION SHM_OFFSET(0x08)
190 #define RX_FRAME_ADDR1_1 SHM_OFFSET(0x0A)
191 #define RX_FRAME_ADDR1_2 SHM_OFFSET(0x0C)
192 #define RX_FRAME_ADDR1_3 SHM_OFFSET(0x0E)
193 #define RX_FRAME_ADDR2_1 SHM_OFFSET(0x10)
194 #define RX_FRAME_ADDR2_2 SHM_OFFSET(0x12)
195 #define RX_FRAME_ADDR2_3 SHM_OFFSET(0x14)
196 #define RX_FRAME_ADDR3_1 SHM_OFFSET(0x16)
197 #define RX_FRAME_ADDR3_2 SHM_OFFSET(0x18)
198 #define RX_FRAME_ADDR3_3 SHM_OFFSET(0x1A)
200 #define RX_FRAME_BCN_TIMESTAMP_0 SHM_OFFSET(0x1E)
201 #define RX_FRAME_BCN_TIMESTAMP_1 SHM_OFFSET(0x20)
202 #define RX_FRAME_BCN_TIMESTAMP_2 SHM_OFFSET(0x22)
203 #define RX_FRAME_BCN_TIMESTAMP_3 SHM_OFFSET(0x24)
205 /* RX-header for the driver.
206 * The RXE will take it from here and put it into the DMA FIFO. */
207 #define SHM_RXHDR SHM(0xA88) /* start of the RX driver header */
208 #define SHM_RXHDR_LEN 0xA /* length of this header in 16bit words */
209 #define SHM_RXHDR_FLEN SHM(0xA88) /* frame length, not including the RX header length */
210 #define SHM_RXHDR_PAD SHM(0xA8A) /* unused padding */
211 #define SHM_RXHDR_PHYST0 SHM(0xA8C) /* PHY RX Status 0 */
212 #define SHM_RXHDR_PHYST1 SHM(0xA8E) /* PHY RX Status 1 */
213 #define SHM_RXHDR_PHYST2 SHM(0xA90) /* PHY RX Status 2 */
214 #define SHM_RXHDR_PHYST3 SHM(0xA92) /* PHY RX Status 3 */
215 #define SHM_RXHDR_MACST_LOW SHM(0xA94) /* MAC RX Status (low 16 bits) */
216 #define MACSTAT0_FCSERR 0 /* bit0: FCS error */
217 #define MACSTAT0_RESP 1 /* bit1: Response frame transmitted */
218 #define MACSTAT0_PADDING 2 /* bit2: Pad bytes present */
219 #define MACSTAT0_DEC 3 /* bit3: Decryption attempted */
220 #define MACSTAT0_DECERR 4 /* bit4: Decrypt error */
221 #define SHM_RXHDR_MACST_HIGH SHM(0xA96) /* MAX RX Status (high 16 bits) */
222 #define SHM_RXHDR_MACTIME SHM(0xA98) /* MAC time (time of first MAC symbol plus PHY delay */
223 #define SHM_RXHDR_RXCHAN SHM(0xA9A) /* RX Channel */
225 #define SHM_BGN_START_TSF1 SHM(0xAD8) /* TSF word1 when the measurement started */
226 #define SHM_WAIT10_CLOCK SHM(0xADA) /* Clock is stored here when waiting 10us after tx without bg noise sampling */
227 #define SHM_LAST_RX_ANTENNA SHM(0xAE6) /* Last antenna that received a frame */
230 /* TX header WORD(!) offsets. These are used as offsets into the TX header
231 * information fields in SHM for each FIFO via offset register pointer.
232 * This layout is v351 compliant */
233 #define TXHDR_MACLO SHM_OFFSET(0x00) /* MAC control lo */
234 #define TXHDR_MACLO_DFCS 6 /* bit6: Do not generate FCS */
235 #define TXHDR_MACHI SHM_OFFSET(0x02) /* MAC control hi */
236 #define TXHDR_FCTL SHM_OFFSET(0x04) /* Frame Control field copy */
237 #define TXHDR_FES SHM_OFFSET(0x06) /* TX FES Time Normal */
238 #define TXHDR_PHYCTL SHM_OFFSET(0x08) /* PHY control word */
239 #define TXHDR_PHYCTL1 SHM_OFFSET(0x0A) /* PHY control word 1 */
240 #define TXHDR_PHYCTL1FB SHM_OFFSET(0x0C) /* PHY control word 1 for fallback */
241 #define TXHDR_PHYCTL1RTS SHM_OFFSET(0x0E) /* PHY control word 1 RTS */
242 #define TXHDR_PHYCTL1RTSFB SHM_OFFSET(0x10) /* PHY control word 1 RTS for fallback */
243 #define TXHDR_PHYRATES SHM_OFFSET(0x12) /* PHY rates */
244 #define TXHDR_EFT SHM_OFFSET(0x14) /* Extra Frame Types */
245 #define TXHDR_IV SHM_OFFSET(0x16) /* IV / crypto field */
246 #define TXHDR_RA SHM_OFFSET(0x26) /* Tx Frame receiver address */
247 #define TXHDR_FESFB SHM_OFFSET(0x2C) /* TX FES Time fallback */
248 #define TXHDR_RTSPLCPFB SHM_OFFSET(0x2E) /* RTS PLCP fallback */
249 #define TXHDR_RTSDURFB SHM_OFFSET(0x34) /* RTS duration fallback */
250 #define TXHDR_PLCPFB0 SHM_OFFSET(0x36) /* PLCP fallback word 0 */
251 #define TXHDR_PLCPFB1 SHM_OFFSET(0x38) /* PLCP fallback word 1 */
252 #define TXHDR_DURFB SHM_OFFSET(0x3C) /* Duration fallback */
253 #define TXHDR_MIMOML SHM_OFFSET(0x3E) /* MIMO mode length */
254 #define TXHDR_MIMOFBRL SHM_OFFSET(0x40) /* MIMO fallback rate length */
255 #define TXHDR_TOLO SHM_OFFSET(0x42) /* Timeout low */
256 #define TXHDR_TOHI SHM_OFFSET(0x44) /* Timeout high */
257 #define TXHDR_UNUSED SHM_OFFSET(0x4A) /* Unused */
258 #define TXHDR_COOKIE SHM_OFFSET(0x4C) /* Frame ID */
259 #define TXHDR_STAT SHM_OFFSET(0x4E) /* Status */
260 #define TXHDR_RTSPLCP SHM_OFFSET(0x50) /* RTS PLCP header */
261 #define TXHDR_RTSSEQCTR SHM_OFFSET(0x52) /* RTS PLCP sequence counter */
262 #define TXHDR_RTSPHYSTAT SHM_OFFSET(0x54) /* RTS PLCP phy status */
263 #define TXHDR_RTS SHM_OFFSET(0x56) /* RTS frame */
264 #define TXHDR_HK4 SHM_OFFSET(0x58) /* Housekeeping field 4 */
265 #define TXHDR_HK5 SHM_OFFSET(0x5A) /* Housekeeping field 5 */
266 #define TXHDR_UNUSED2 SHM_OFFSET(0x66) /* Unused padding */
268 #define TXHDR_LEN 80 /* Length of this header in 16bit words */
270 /* END ABI: End of the driver ABI definitions */
272 #endif /* SHARED_MEMORY_H_ */
274 // vim: syntax=b43 ts=8