2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
84 return DWC3_DSTS_USBLNKST(reg);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc->revision >= DWC3_REVISION_194A) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc->revision >= DWC3_REVISION_194A)
131 /* wait for a change in DSTS */
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
136 if (DWC3_DSTS_USBLNKST(reg) == state)
142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
149 * dwc3_ep_inc_trb() - Increment a TRB index.
150 * @index - Pointer to the TRB index to increment.
152 * The index should never point to the link TRB. After incrementing,
153 * if it is point to the link TRB, wrap around to the beginning. The
154 * link TRB is always at the last TRB entry.
156 static void dwc3_ep_inc_trb(u8 *index)
159 if (*index == (DWC3_TRB_NUM - 1))
163 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
165 dwc3_ep_inc_trb(&dep->trb_enqueue);
168 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
170 dwc3_ep_inc_trb(&dep->trb_dequeue);
173 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
176 struct dwc3 *dwc = dep->dwc;
177 unsigned int unmap_after_complete = false;
179 req->started = false;
180 list_del(&req->list);
183 if (req->request.status == -EINPROGRESS)
184 req->request.status = status;
187 * NOTICE we don't want to unmap before calling ->complete() if we're
188 * dealing with a bounced ep0 request. If we unmap it here, we would end
189 * up overwritting the contents of req->buf and this could confuse the
192 if (dwc->ep0_bounced && dep->number <= 1) {
193 dwc->ep0_bounced = false;
194 unmap_after_complete = true;
196 usb_gadget_unmap_request(&dwc->gadget,
197 &req->request, req->direction);
200 trace_dwc3_gadget_giveback(req);
202 spin_unlock(&dwc->lock);
203 usb_gadget_giveback_request(&dep->endpoint, &req->request);
204 spin_lock(&dwc->lock);
206 if (unmap_after_complete)
207 usb_gadget_unmap_request(&dwc->gadget,
208 &req->request, req->direction);
211 pm_runtime_put(dwc->dev);
214 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
221 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
222 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
225 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
226 if (!(reg & DWC3_DGCMD_CMDACT)) {
227 status = DWC3_DGCMD_STATUS(reg);
239 trace_dwc3_gadget_generic_cmd(cmd, param, status);
244 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
246 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
247 struct dwc3_gadget_ep_cmd_params *params)
249 struct dwc3 *dwc = dep->dwc;
258 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
259 * we're issuing an endpoint command, we must check if
260 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
262 * We will also set SUSPHY bit to what it was before returning as stated
263 * by the same section on Synopsys databook.
265 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
266 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
267 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
269 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
270 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
274 if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
277 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
278 dwc->link_state == DWC3_LINK_STATE_U2 ||
279 dwc->link_state == DWC3_LINK_STATE_U3);
281 if (unlikely(needs_wakeup)) {
282 ret = __dwc3_gadget_wakeup(dwc);
283 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
288 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
289 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
290 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
292 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT);
294 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
295 if (!(reg & DWC3_DEPCMD_CMDACT)) {
296 cmd_status = DWC3_DEPCMD_STATUS(reg);
298 switch (cmd_status) {
302 case DEPEVT_TRANSFER_NO_RESOURCE:
305 case DEPEVT_TRANSFER_BUS_EXPIRY:
307 * SW issues START TRANSFER command to
308 * isochronous ep with future frame interval. If
309 * future interval time has already passed when
310 * core receives the command, it will respond
311 * with an error status of 'Bus Expiry'.
313 * Instead of always returning -EINVAL, let's
314 * give a hint to the gadget driver that this is
315 * the case by returning -EAGAIN.
320 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
329 cmd_status = -ETIMEDOUT;
332 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
334 if (unlikely(susphy)) {
335 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
336 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
337 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
343 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
345 struct dwc3 *dwc = dep->dwc;
346 struct dwc3_gadget_ep_cmd_params params;
347 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
350 * As of core revision 2.60a the recommended programming model
351 * is to set the ClearPendIN bit when issuing a Clear Stall EP
352 * command for IN endpoints. This is to prevent an issue where
353 * some (non-compliant) hosts may not send ACK TPs for pending
354 * IN transfers due to a mishandled error condition. Synopsys
357 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
358 (dwc->gadget.speed >= USB_SPEED_SUPER))
359 cmd |= DWC3_DEPCMD_CLEARPENDIN;
361 memset(¶ms, 0, sizeof(params));
363 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
366 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
367 struct dwc3_trb *trb)
369 u32 offset = (char *) trb - (char *) dep->trb_pool;
371 return dep->trb_pool_dma + offset;
374 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
376 struct dwc3 *dwc = dep->dwc;
381 dep->trb_pool = dma_alloc_coherent(dwc->dev,
382 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
383 &dep->trb_pool_dma, GFP_KERNEL);
384 if (!dep->trb_pool) {
385 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
393 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
395 struct dwc3 *dwc = dep->dwc;
397 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
398 dep->trb_pool, dep->trb_pool_dma);
400 dep->trb_pool = NULL;
401 dep->trb_pool_dma = 0;
404 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
407 * dwc3_gadget_start_config - Configure EP resources
408 * @dwc: pointer to our controller context structure
409 * @dep: endpoint that is being enabled
411 * The assignment of transfer resources cannot perfectly follow the
412 * data book due to the fact that the controller driver does not have
413 * all knowledge of the configuration in advance. It is given this
414 * information piecemeal by the composite gadget framework after every
415 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
416 * programming model in this scenario can cause errors. For two
419 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
420 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
421 * multiple interfaces.
423 * 2) The databook does not mention doing more DEPXFERCFG for new
424 * endpoint on alt setting (8.1.6).
426 * The following simplified method is used instead:
428 * All hardware endpoints can be assigned a transfer resource and this
429 * setting will stay persistent until either a core reset or
430 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
431 * do DEPXFERCFG for every hardware endpoint as well. We are
432 * guaranteed that there are as many transfer resources as endpoints.
434 * This function is called for each endpoint when it is being enabled
435 * but is triggered only when called for EP0-out, which always happens
436 * first, and which should only happen in one of the above conditions.
438 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
440 struct dwc3_gadget_ep_cmd_params params;
448 memset(¶ms, 0x00, sizeof(params));
449 cmd = DWC3_DEPCMD_DEPSTARTCFG;
451 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
455 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
456 struct dwc3_ep *dep = dwc->eps[i];
461 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
469 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
470 const struct usb_endpoint_descriptor *desc,
471 const struct usb_ss_ep_comp_descriptor *comp_desc,
472 bool modify, bool restore)
474 struct dwc3_gadget_ep_cmd_params params;
476 if (dev_WARN_ONCE(dwc->dev, modify && restore,
477 "Can't modify and restore\n"))
480 memset(¶ms, 0x00, sizeof(params));
482 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
483 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
485 /* Burst size is only needed in SuperSpeed mode */
486 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
487 u32 burst = dep->endpoint.maxburst;
488 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
492 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
493 } else if (restore) {
494 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
495 params.param2 |= dep->saved_state;
497 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
500 if (usb_endpoint_xfer_control(desc))
501 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
503 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
504 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
506 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
507 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
508 | DWC3_DEPCFG_STREAM_EVENT_EN;
509 dep->stream_capable = true;
512 if (!usb_endpoint_xfer_control(desc))
513 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
516 * We are doing 1:1 mapping for endpoints, meaning
517 * Physical Endpoints 2 maps to Logical Endpoint 2 and
518 * so on. We consider the direction bit as part of the physical
519 * endpoint number. So USB endpoint 0x81 is 0x03.
521 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
524 * We must use the lower 16 TX FIFOs even though
528 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
530 if (desc->bInterval) {
534 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13, and it
535 * must be set to 0 when the controller operates in full-speed.
537 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
538 if (dwc->gadget.speed == USB_SPEED_FULL)
541 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
542 dwc->gadget.speed == USB_SPEED_FULL)
543 dep->interval = desc->bInterval;
545 dep->interval = 1 << (desc->bInterval - 1);
547 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
550 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
553 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
555 struct dwc3_gadget_ep_cmd_params params;
557 memset(¶ms, 0x00, sizeof(params));
559 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
561 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
566 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
567 * @dep: endpoint to be initialized
568 * @desc: USB Endpoint Descriptor
570 * Caller should take care of locking
572 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
573 const struct usb_endpoint_descriptor *desc,
574 const struct usb_ss_ep_comp_descriptor *comp_desc,
575 bool modify, bool restore)
577 struct dwc3 *dwc = dep->dwc;
581 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
583 if (!(dep->flags & DWC3_EP_ENABLED)) {
584 ret = dwc3_gadget_start_config(dwc, dep);
589 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, modify,
594 if (!(dep->flags & DWC3_EP_ENABLED)) {
595 struct dwc3_trb *trb_st_hw;
596 struct dwc3_trb *trb_link;
598 dep->endpoint.desc = desc;
599 dep->comp_desc = comp_desc;
600 dep->type = usb_endpoint_type(desc);
601 dep->flags |= DWC3_EP_ENABLED;
603 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
604 reg |= DWC3_DALEPENA_EP(dep->number);
605 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
607 if (usb_endpoint_xfer_control(desc))
610 /* Initialize the TRB ring */
611 dep->trb_dequeue = 0;
612 dep->trb_enqueue = 0;
613 memset(dep->trb_pool, 0,
614 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
616 /* Link TRB. The HWO bit is never reset */
617 trb_st_hw = &dep->trb_pool[0];
619 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
620 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
621 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
622 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
623 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
629 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
630 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
632 struct dwc3_request *req;
634 dwc3_stop_active_transfer(dwc, dep->number, true);
636 /* - giveback all requests to gadget driver */
637 while (!list_empty(&dep->started_list)) {
638 req = next_request(&dep->started_list);
640 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
643 while (!list_empty(&dep->pending_list)) {
644 req = next_request(&dep->pending_list);
646 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
651 * __dwc3_gadget_ep_disable - Disables a HW endpoint
652 * @dep: the endpoint to disable
654 * This function also removes requests which are currently processed ny the
655 * hardware and those which are not yet scheduled.
656 * Caller should take care of locking.
658 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
660 struct dwc3 *dwc = dep->dwc;
663 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
665 dwc3_remove_requests(dwc, dep);
667 /* make sure HW endpoint isn't stalled */
668 if (dep->flags & DWC3_EP_STALL)
669 __dwc3_gadget_ep_set_halt(dep, 0, false);
671 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
672 reg &= ~DWC3_DALEPENA_EP(dep->number);
673 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
675 dep->stream_capable = false;
676 dep->endpoint.desc = NULL;
677 dep->comp_desc = NULL;
684 /* -------------------------------------------------------------------------- */
686 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
687 const struct usb_endpoint_descriptor *desc)
692 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
697 /* -------------------------------------------------------------------------- */
699 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
700 const struct usb_endpoint_descriptor *desc)
707 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
708 pr_debug("dwc3: invalid parameters\n");
712 if (!desc->wMaxPacketSize) {
713 pr_debug("dwc3: missing wMaxPacketSize\n");
717 dep = to_dwc3_ep(ep);
720 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
721 "%s is already enabled\n",
725 spin_lock_irqsave(&dwc->lock, flags);
726 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
727 spin_unlock_irqrestore(&dwc->lock, flags);
732 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
740 pr_debug("dwc3: invalid parameters\n");
744 dep = to_dwc3_ep(ep);
747 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
748 "%s is already disabled\n",
752 spin_lock_irqsave(&dwc->lock, flags);
753 ret = __dwc3_gadget_ep_disable(dep);
754 spin_unlock_irqrestore(&dwc->lock, flags);
759 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
762 struct dwc3_request *req;
763 struct dwc3_ep *dep = to_dwc3_ep(ep);
765 req = kzalloc(sizeof(*req), gfp_flags);
769 req->epnum = dep->number;
772 dep->allocated_requests++;
774 trace_dwc3_alloc_request(req);
776 return &req->request;
779 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
780 struct usb_request *request)
782 struct dwc3_request *req = to_dwc3_request(request);
783 struct dwc3_ep *dep = to_dwc3_ep(ep);
785 dep->allocated_requests--;
786 trace_dwc3_free_request(req);
790 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
793 * dwc3_prepare_one_trb - setup one TRB from one request
794 * @dep: endpoint for which this request is prepared
795 * @req: dwc3_request pointer
797 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
798 struct dwc3_request *req, dma_addr_t dma,
799 unsigned length, unsigned chain, unsigned node)
801 struct dwc3_trb *trb;
802 struct dwc3 *dwc = dep->dwc;
803 struct usb_gadget *gadget = &dwc->gadget;
804 enum usb_device_speed speed = gadget->speed;
806 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s",
807 dep->name, req, (unsigned long long) dma,
808 length, chain ? " chain" : "");
810 trb = &dep->trb_pool[dep->trb_enqueue];
813 dwc3_gadget_move_started_request(req);
815 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
816 req->first_trb_index = dep->trb_enqueue;
817 dep->queued_requests++;
820 dwc3_ep_inc_enq(dep);
822 trb->size = DWC3_TRB_SIZE_LENGTH(length);
823 trb->bpl = lower_32_bits(dma);
824 trb->bph = upper_32_bits(dma);
826 switch (usb_endpoint_type(dep->endpoint.desc)) {
827 case USB_ENDPOINT_XFER_CONTROL:
828 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
831 case USB_ENDPOINT_XFER_ISOC:
833 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
836 * USB Specification 2.0 Section 5.9.2 states that: "If
837 * there is only a single transaction in the microframe,
838 * only a DATA0 data packet PID is used. If there are
839 * two transactions per microframe, DATA1 is used for
840 * the first transaction data packet and DATA0 is used
841 * for the second transaction data packet. If there are
842 * three transactions per microframe, DATA2 is used for
843 * the first transaction data packet, DATA1 is used for
844 * the second, and DATA0 is used for the third."
846 * IOW, we should satisfy the following cases:
848 * 1) length <= maxpacket
851 * 2) maxpacket < length <= (2 * maxpacket)
854 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
855 * - DATA2, DATA1, DATA0
857 if (speed == USB_SPEED_HIGH) {
858 struct usb_ep *ep = &dep->endpoint;
859 unsigned int mult = ep->mult - 1;
862 maxp = usb_endpoint_maxp(ep->desc) & 0x07ff;
864 if (length <= (2 * maxp))
870 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
873 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
876 /* always enable Interrupt on Missed ISOC */
877 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
880 case USB_ENDPOINT_XFER_BULK:
881 case USB_ENDPOINT_XFER_INT:
882 trb->ctrl = DWC3_TRBCTL_NORMAL;
886 * This is only possible with faulty memory because we
887 * checked it already :)
892 /* always enable Continue on Short Packet */
893 trb->ctrl |= DWC3_TRB_CTRL_CSP;
895 if ((!req->request.no_interrupt && !chain) ||
896 (dwc3_calc_trbs_left(dep) == 0))
897 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
900 trb->ctrl |= DWC3_TRB_CTRL_CHN;
902 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
903 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
905 trb->ctrl |= DWC3_TRB_CTRL_HWO;
907 trace_dwc3_prepare_trb(dep, trb);
911 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
912 * @dep: The endpoint with the TRB ring
913 * @index: The index of the current TRB in the ring
915 * Returns the TRB prior to the one pointed to by the index. If the
916 * index is 0, we will wrap backwards, skip the link TRB, and return
917 * the one just before that.
919 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
924 tmp = DWC3_TRB_NUM - 1;
926 return &dep->trb_pool[tmp - 1];
929 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
934 * If the enqueue & dequeue are equal then the TRB ring is either full
935 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
936 * pending to be processed by the driver.
938 if (dep->trb_enqueue == dep->trb_dequeue) {
940 * If there is any request remained in the started_list at
941 * this point, that means there is no TRB available.
943 if (!list_empty(&dep->started_list))
946 return DWC3_TRB_NUM - 1;
949 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
950 trbs_left &= (DWC3_TRB_NUM - 1);
952 if (dep->trb_dequeue < dep->trb_enqueue)
958 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
959 struct dwc3_request *req)
961 struct scatterlist *sg = req->sg;
962 struct scatterlist *s;
967 for_each_sg(sg, s, req->num_pending_sgs, i) {
968 unsigned chain = true;
970 length = sg_dma_len(s);
971 dma = sg_dma_address(s);
976 dwc3_prepare_one_trb(dep, req, dma, length,
979 if (!dwc3_calc_trbs_left(dep))
984 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
985 struct dwc3_request *req)
990 dma = req->request.dma;
991 length = req->request.length;
993 dwc3_prepare_one_trb(dep, req, dma, length,
998 * dwc3_prepare_trbs - setup TRBs from requests
999 * @dep: endpoint for which requests are being prepared
1001 * The function goes through the requests list and sets up TRBs for the
1002 * transfers. The function returns once there are no more TRBs available or
1003 * it runs out of requests.
1005 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1007 struct dwc3_request *req, *n;
1009 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1011 if (!dwc3_calc_trbs_left(dep))
1014 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1015 if (req->num_pending_sgs > 0)
1016 dwc3_prepare_one_trb_sg(dep, req);
1018 dwc3_prepare_one_trb_linear(dep, req);
1020 if (!dwc3_calc_trbs_left(dep))
1025 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
1027 struct dwc3_gadget_ep_cmd_params params;
1028 struct dwc3_request *req;
1029 struct dwc3 *dwc = dep->dwc;
1034 starting = !(dep->flags & DWC3_EP_BUSY);
1036 dwc3_prepare_trbs(dep);
1037 req = next_request(&dep->started_list);
1039 dep->flags |= DWC3_EP_PENDING_REQUEST;
1043 memset(¶ms, 0, sizeof(params));
1046 params.param0 = upper_32_bits(req->trb_dma);
1047 params.param1 = lower_32_bits(req->trb_dma);
1048 cmd = DWC3_DEPCMD_STARTTRANSFER |
1049 DWC3_DEPCMD_PARAM(cmd_param);
1051 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1052 DWC3_DEPCMD_PARAM(dep->resource_index);
1055 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1058 * FIXME we need to iterate over the list of requests
1059 * here and stop, unmap, free and del each of the linked
1060 * requests instead of what we do now.
1062 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1064 list_del(&req->list);
1068 dep->flags |= DWC3_EP_BUSY;
1071 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1072 WARN_ON_ONCE(!dep->resource_index);
1078 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1079 struct dwc3_ep *dep, u32 cur_uf)
1083 if (list_empty(&dep->pending_list)) {
1084 dwc3_trace(trace_dwc3_gadget,
1085 "ISOC ep %s run out for requests",
1087 dep->flags |= DWC3_EP_PENDING_REQUEST;
1091 /* 4 micro frames in the future */
1092 uf = cur_uf + dep->interval * 4;
1094 __dwc3_gadget_kick_transfer(dep, uf);
1097 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1098 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1102 mask = ~(dep->interval - 1);
1103 cur_uf = event->parameters & mask;
1105 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1108 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1110 struct dwc3 *dwc = dep->dwc;
1113 if (!dep->endpoint.desc) {
1114 dwc3_trace(trace_dwc3_gadget,
1115 "trying to queue request %p to disabled %s",
1116 &req->request, dep->endpoint.name);
1120 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1121 &req->request, req->dep->name)) {
1122 dwc3_trace(trace_dwc3_gadget, "request %pK belongs to '%s'",
1123 &req->request, req->dep->name);
1127 pm_runtime_get(dwc->dev);
1129 req->request.actual = 0;
1130 req->request.status = -EINPROGRESS;
1131 req->direction = dep->direction;
1132 req->epnum = dep->number;
1134 trace_dwc3_ep_queue(req);
1136 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1141 req->sg = req->request.sg;
1142 req->num_pending_sgs = req->request.num_mapped_sgs;
1144 list_add_tail(&req->list, &dep->pending_list);
1147 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1148 * wait for a XferNotReady event so we will know what's the current
1149 * (micro-)frame number.
1151 * Without this trick, we are very, very likely gonna get Bus Expiry
1152 * errors which will force us issue EndTransfer command.
1154 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1155 if ((dep->flags & DWC3_EP_PENDING_REQUEST) &&
1156 list_empty(&dep->started_list)) {
1157 dwc3_stop_active_transfer(dwc, dep->number, true);
1158 dep->flags = DWC3_EP_ENABLED;
1163 if (!dwc3_calc_trbs_left(dep))
1166 ret = __dwc3_gadget_kick_transfer(dep, 0);
1167 if (ret && ret != -EBUSY)
1168 dwc3_trace(trace_dwc3_gadget,
1169 "%s: failed to kick transfers",
1177 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1178 struct usb_request *request)
1180 dwc3_gadget_ep_free_request(ep, request);
1183 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1185 struct dwc3_request *req;
1186 struct usb_request *request;
1187 struct usb_ep *ep = &dep->endpoint;
1189 dwc3_trace(trace_dwc3_gadget, "queueing ZLP");
1190 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1194 request->length = 0;
1195 request->buf = dwc->zlp_buf;
1196 request->complete = __dwc3_gadget_ep_zlp_complete;
1198 req = to_dwc3_request(request);
1200 return __dwc3_gadget_ep_queue(dep, req);
1203 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1206 struct dwc3_request *req = to_dwc3_request(request);
1207 struct dwc3_ep *dep = to_dwc3_ep(ep);
1208 struct dwc3 *dwc = dep->dwc;
1210 unsigned long flags;
1214 spin_lock_irqsave(&dwc->lock, flags);
1215 ret = __dwc3_gadget_ep_queue(dep, req);
1218 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1219 * setting request->zero, instead of doing magic, we will just queue an
1220 * extra usb_request ourselves so that it gets handled the same way as
1221 * any other request.
1223 if (ret == 0 && request->zero && request->length &&
1224 (request->length % ep->maxpacket == 0))
1225 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1227 spin_unlock_irqrestore(&dwc->lock, flags);
1232 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1233 struct usb_request *request)
1235 struct dwc3_request *req = to_dwc3_request(request);
1236 struct dwc3_request *r = NULL;
1238 struct dwc3_ep *dep = to_dwc3_ep(ep);
1239 struct dwc3 *dwc = dep->dwc;
1241 unsigned long flags;
1244 trace_dwc3_ep_dequeue(req);
1246 spin_lock_irqsave(&dwc->lock, flags);
1248 list_for_each_entry(r, &dep->pending_list, list) {
1254 list_for_each_entry(r, &dep->started_list, list) {
1259 /* wait until it is processed */
1260 dwc3_stop_active_transfer(dwc, dep->number, true);
1263 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1270 /* giveback the request */
1271 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1274 spin_unlock_irqrestore(&dwc->lock, flags);
1279 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1281 struct dwc3_gadget_ep_cmd_params params;
1282 struct dwc3 *dwc = dep->dwc;
1285 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1286 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1290 memset(¶ms, 0x00, sizeof(params));
1293 struct dwc3_trb *trb;
1295 unsigned transfer_in_flight;
1298 if (dep->number > 1)
1299 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1301 trb = &dwc->ep0_trb[dep->trb_enqueue];
1303 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1304 started = !list_empty(&dep->started_list);
1306 if (!protocol && ((dep->direction && transfer_in_flight) ||
1307 (!dep->direction && started))) {
1308 dwc3_trace(trace_dwc3_gadget,
1309 "%s: pending request, cannot halt",
1314 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1317 dev_err(dwc->dev, "failed to set STALL on %s\n",
1320 dep->flags |= DWC3_EP_STALL;
1323 ret = dwc3_send_clear_stall_ep_cmd(dep);
1325 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1328 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1334 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1336 struct dwc3_ep *dep = to_dwc3_ep(ep);
1337 struct dwc3 *dwc = dep->dwc;
1339 unsigned long flags;
1343 spin_lock_irqsave(&dwc->lock, flags);
1344 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1345 spin_unlock_irqrestore(&dwc->lock, flags);
1350 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1352 struct dwc3_ep *dep = to_dwc3_ep(ep);
1353 struct dwc3 *dwc = dep->dwc;
1354 unsigned long flags;
1357 spin_lock_irqsave(&dwc->lock, flags);
1358 dep->flags |= DWC3_EP_WEDGE;
1360 if (dep->number == 0 || dep->number == 1)
1361 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1363 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1364 spin_unlock_irqrestore(&dwc->lock, flags);
1369 /* -------------------------------------------------------------------------- */
1371 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1372 .bLength = USB_DT_ENDPOINT_SIZE,
1373 .bDescriptorType = USB_DT_ENDPOINT,
1374 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1377 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1378 .enable = dwc3_gadget_ep0_enable,
1379 .disable = dwc3_gadget_ep0_disable,
1380 .alloc_request = dwc3_gadget_ep_alloc_request,
1381 .free_request = dwc3_gadget_ep_free_request,
1382 .queue = dwc3_gadget_ep0_queue,
1383 .dequeue = dwc3_gadget_ep_dequeue,
1384 .set_halt = dwc3_gadget_ep0_set_halt,
1385 .set_wedge = dwc3_gadget_ep_set_wedge,
1388 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1389 .enable = dwc3_gadget_ep_enable,
1390 .disable = dwc3_gadget_ep_disable,
1391 .alloc_request = dwc3_gadget_ep_alloc_request,
1392 .free_request = dwc3_gadget_ep_free_request,
1393 .queue = dwc3_gadget_ep_queue,
1394 .dequeue = dwc3_gadget_ep_dequeue,
1395 .set_halt = dwc3_gadget_ep_set_halt,
1396 .set_wedge = dwc3_gadget_ep_set_wedge,
1399 /* -------------------------------------------------------------------------- */
1401 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1403 struct dwc3 *dwc = gadget_to_dwc(g);
1406 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1407 return DWC3_DSTS_SOFFN(reg);
1410 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1421 * According to the Databook Remote wakeup request should
1422 * be issued only when the device is in early suspend state.
1424 * We can check that via USB Link State bits in DSTS register.
1426 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1428 speed = reg & DWC3_DSTS_CONNECTSPD;
1429 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1430 (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
1431 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed");
1435 link_state = DWC3_DSTS_USBLNKST(reg);
1437 switch (link_state) {
1438 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1439 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1442 dwc3_trace(trace_dwc3_gadget,
1443 "can't wakeup from '%s'",
1444 dwc3_gadget_link_string(link_state));
1448 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1450 dev_err(dwc->dev, "failed to put link in Recovery\n");
1454 /* Recent versions do this automatically */
1455 if (dwc->revision < DWC3_REVISION_194A) {
1456 /* write zeroes to Link Change Request */
1457 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1458 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1459 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1462 /* poll until Link State changes to ON */
1466 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1468 /* in HS, means ON */
1469 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1473 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1474 dev_err(dwc->dev, "failed to send remote wakeup\n");
1481 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1483 struct dwc3 *dwc = gadget_to_dwc(g);
1484 unsigned long flags;
1487 spin_lock_irqsave(&dwc->lock, flags);
1488 ret = __dwc3_gadget_wakeup(dwc);
1489 spin_unlock_irqrestore(&dwc->lock, flags);
1494 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1497 struct dwc3 *dwc = gadget_to_dwc(g);
1498 unsigned long flags;
1500 spin_lock_irqsave(&dwc->lock, flags);
1501 g->is_selfpowered = !!is_selfpowered;
1502 spin_unlock_irqrestore(&dwc->lock, flags);
1507 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1512 if (pm_runtime_suspended(dwc->dev))
1515 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1517 if (dwc->revision <= DWC3_REVISION_187A) {
1518 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1519 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1522 if (dwc->revision >= DWC3_REVISION_194A)
1523 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1524 reg |= DWC3_DCTL_RUN_STOP;
1526 if (dwc->has_hibernation)
1527 reg |= DWC3_DCTL_KEEP_CONNECT;
1529 dwc->pullups_connected = true;
1531 reg &= ~DWC3_DCTL_RUN_STOP;
1533 if (dwc->has_hibernation && !suspend)
1534 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1536 dwc->pullups_connected = false;
1539 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1542 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1543 reg &= DWC3_DSTS_DEVCTRLHLT;
1544 } while (--timeout && !(!is_on ^ !reg));
1549 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1551 ? dwc->gadget_driver->function : "no-function",
1552 is_on ? "connect" : "disconnect");
1557 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1559 struct dwc3 *dwc = gadget_to_dwc(g);
1560 unsigned long flags;
1565 spin_lock_irqsave(&dwc->lock, flags);
1566 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1567 spin_unlock_irqrestore(&dwc->lock, flags);
1572 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1576 /* Enable all but Start and End of Frame IRQs */
1577 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1578 DWC3_DEVTEN_EVNTOVERFLOWEN |
1579 DWC3_DEVTEN_CMDCMPLTEN |
1580 DWC3_DEVTEN_ERRTICERREN |
1581 DWC3_DEVTEN_WKUPEVTEN |
1582 DWC3_DEVTEN_ULSTCNGEN |
1583 DWC3_DEVTEN_CONNECTDONEEN |
1584 DWC3_DEVTEN_USBRSTEN |
1585 DWC3_DEVTEN_DISCONNEVTEN);
1587 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1590 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1592 /* mask all interrupts */
1593 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1596 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1597 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1600 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1601 * dwc: pointer to our context structure
1603 * The following looks like complex but it's actually very simple. In order to
1604 * calculate the number of packets we can burst at once on OUT transfers, we're
1605 * gonna use RxFIFO size.
1607 * To calculate RxFIFO size we need two numbers:
1608 * MDWIDTH = size, in bits, of the internal memory bus
1609 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1611 * Given these two numbers, the formula is simple:
1613 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1615 * 24 bytes is for 3x SETUP packets
1616 * 16 bytes is a clock domain crossing tolerance
1618 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1620 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1627 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1628 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1630 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1631 nump = min_t(u32, nump, 16);
1634 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1635 reg &= ~DWC3_DCFG_NUMP_MASK;
1636 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1637 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1640 static int __dwc3_gadget_start(struct dwc3 *dwc)
1642 struct dwc3_ep *dep;
1646 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1647 reg &= ~(DWC3_DCFG_SPEED_MASK);
1650 * WORKAROUND: DWC3 revision < 2.20a have an issue
1651 * which would cause metastability state on Run/Stop
1652 * bit if we try to force the IP to USB2-only mode.
1654 * Because of that, we cannot configure the IP to any
1655 * speed other than the SuperSpeed
1659 * STAR#9000525659: Clock Domain Crossing on DCTL in
1662 if (dwc->revision < DWC3_REVISION_220A) {
1663 reg |= DWC3_DCFG_SUPERSPEED;
1665 switch (dwc->maximum_speed) {
1667 reg |= DWC3_DCFG_LOWSPEED;
1669 case USB_SPEED_FULL:
1670 reg |= DWC3_DCFG_FULLSPEED;
1672 case USB_SPEED_HIGH:
1673 reg |= DWC3_DCFG_HIGHSPEED;
1675 case USB_SPEED_SUPER_PLUS:
1676 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
1679 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1680 dwc->maximum_speed);
1682 case USB_SPEED_SUPER:
1683 reg |= DWC3_DCFG_SUPERSPEED;
1687 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1690 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1691 * field instead of letting dwc3 itself calculate that automatically.
1693 * This way, we maximize the chances that we'll be able to get several
1694 * bursts of data without going through any sort of endpoint throttling.
1696 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1697 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1698 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1700 dwc3_gadget_setup_nump(dwc);
1702 /* Start with SuperSpeed Default */
1703 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1706 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1709 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1714 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1717 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1721 /* begin to receive SETUP packets */
1722 dwc->ep0state = EP0_SETUP_PHASE;
1723 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
1724 dwc3_ep0_out_start(dwc);
1726 dwc3_gadget_enable_irq(dwc);
1731 __dwc3_gadget_ep_disable(dwc->eps[0]);
1737 static int dwc3_gadget_start(struct usb_gadget *g,
1738 struct usb_gadget_driver *driver)
1740 struct dwc3 *dwc = gadget_to_dwc(g);
1741 unsigned long flags;
1745 irq = dwc->irq_gadget;
1746 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1747 IRQF_SHARED, "dwc3", dwc->ev_buf);
1749 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1754 spin_lock_irqsave(&dwc->lock, flags);
1755 if (dwc->gadget_driver) {
1756 dev_err(dwc->dev, "%s is already bound to %s\n",
1758 dwc->gadget_driver->driver.name);
1763 dwc->gadget_driver = driver;
1765 if (pm_runtime_active(dwc->dev))
1766 __dwc3_gadget_start(dwc);
1768 spin_unlock_irqrestore(&dwc->lock, flags);
1773 spin_unlock_irqrestore(&dwc->lock, flags);
1780 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1782 if (pm_runtime_suspended(dwc->dev))
1785 dwc3_gadget_disable_irq(dwc);
1786 __dwc3_gadget_ep_disable(dwc->eps[0]);
1787 __dwc3_gadget_ep_disable(dwc->eps[1]);
1790 static int dwc3_gadget_stop(struct usb_gadget *g)
1792 struct dwc3 *dwc = gadget_to_dwc(g);
1793 unsigned long flags;
1795 spin_lock_irqsave(&dwc->lock, flags);
1796 __dwc3_gadget_stop(dwc);
1797 dwc->gadget_driver = NULL;
1798 spin_unlock_irqrestore(&dwc->lock, flags);
1800 free_irq(dwc->irq_gadget, dwc->ev_buf);
1805 static const struct usb_gadget_ops dwc3_gadget_ops = {
1806 .get_frame = dwc3_gadget_get_frame,
1807 .wakeup = dwc3_gadget_wakeup,
1808 .set_selfpowered = dwc3_gadget_set_selfpowered,
1809 .pullup = dwc3_gadget_pullup,
1810 .udc_start = dwc3_gadget_start,
1811 .udc_stop = dwc3_gadget_stop,
1814 /* -------------------------------------------------------------------------- */
1816 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1817 u8 num, u32 direction)
1819 struct dwc3_ep *dep;
1822 for (i = 0; i < num; i++) {
1823 u8 epnum = (i << 1) | (direction ? 1 : 0);
1825 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1830 dep->number = epnum;
1831 dep->direction = !!direction;
1832 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
1833 dwc->eps[epnum] = dep;
1835 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1836 (epnum & 1) ? "in" : "out");
1838 dep->endpoint.name = dep->name;
1839 spin_lock_init(&dep->lock);
1841 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1843 if (epnum == 0 || epnum == 1) {
1844 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1845 dep->endpoint.maxburst = 1;
1846 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1848 dwc->gadget.ep0 = &dep->endpoint;
1852 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1853 dep->endpoint.max_streams = 15;
1854 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1855 list_add_tail(&dep->endpoint.ep_list,
1856 &dwc->gadget.ep_list);
1858 ret = dwc3_alloc_trb_pool(dep);
1863 if (epnum == 0 || epnum == 1) {
1864 dep->endpoint.caps.type_control = true;
1866 dep->endpoint.caps.type_iso = true;
1867 dep->endpoint.caps.type_bulk = true;
1868 dep->endpoint.caps.type_int = true;
1871 dep->endpoint.caps.dir_in = !!direction;
1872 dep->endpoint.caps.dir_out = !direction;
1874 INIT_LIST_HEAD(&dep->pending_list);
1875 INIT_LIST_HEAD(&dep->started_list);
1881 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1885 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1887 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1889 dwc3_trace(trace_dwc3_gadget,
1890 "failed to allocate OUT endpoints");
1894 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1896 dwc3_trace(trace_dwc3_gadget,
1897 "failed to allocate IN endpoints");
1904 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1906 struct dwc3_ep *dep;
1909 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1910 dep = dwc->eps[epnum];
1914 * Physical endpoints 0 and 1 are special; they form the
1915 * bi-directional USB endpoint 0.
1917 * For those two physical endpoints, we don't allocate a TRB
1918 * pool nor do we add them the endpoints list. Due to that, we
1919 * shouldn't do these two operations otherwise we would end up
1920 * with all sorts of bugs when removing dwc3.ko.
1922 if (epnum != 0 && epnum != 1) {
1923 dwc3_free_trb_pool(dep);
1924 list_del(&dep->endpoint.ep_list);
1931 /* -------------------------------------------------------------------------- */
1933 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1934 struct dwc3_request *req, struct dwc3_trb *trb,
1935 const struct dwc3_event_depevt *event, int status,
1939 unsigned int s_pkt = 0;
1940 unsigned int trb_status;
1942 dwc3_ep_inc_deq(dep);
1944 if (req->trb == trb)
1945 dep->queued_requests--;
1947 trace_dwc3_complete_trb(dep, trb);
1950 * If we're in the middle of series of chained TRBs and we
1951 * receive a short transfer along the way, DWC3 will skip
1952 * through all TRBs including the last TRB in the chain (the
1953 * where CHN bit is zero. DWC3 will also avoid clearing HWO
1954 * bit and SW has to do it manually.
1956 * We're going to do that here to avoid problems of HW trying
1957 * to use bogus TRBs for transfers.
1959 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
1960 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1962 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1965 count = trb->size & DWC3_TRB_SIZE_MASK;
1966 req->request.actual += count;
1968 if (dep->direction) {
1970 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1971 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1972 dwc3_trace(trace_dwc3_gadget,
1973 "%s: incomplete IN transfer",
1976 * If missed isoc occurred and there is
1977 * no request queued then issue END
1978 * TRANSFER, so that core generates
1979 * next xfernotready and we will issue
1980 * a fresh START TRANSFER.
1981 * If there are still queued request
1982 * then wait, do not issue either END
1983 * or UPDATE TRANSFER, just attach next
1984 * request in pending_list during
1985 * giveback.If any future queued request
1986 * is successfully transferred then we
1987 * will issue UPDATE TRANSFER for all
1988 * request in the pending_list.
1990 dep->flags |= DWC3_EP_MISSED_ISOC;
1992 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1994 status = -ECONNRESET;
1997 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2000 if (count && (event->status & DEPEVT_STATUS_SHORT))
2004 if (s_pkt && !chain)
2007 if ((event->status & DEPEVT_STATUS_IOC) &&
2008 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2014 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2015 const struct dwc3_event_depevt *event, int status)
2017 struct dwc3_request *req, *n;
2018 struct dwc3_trb *trb;
2022 list_for_each_entry_safe(req, n, &dep->started_list, list) {
2027 length = req->request.length;
2028 chain = req->num_pending_sgs > 0;
2030 struct scatterlist *sg = req->sg;
2031 struct scatterlist *s;
2032 unsigned int pending = req->num_pending_sgs;
2035 for_each_sg(sg, s, pending, i) {
2036 trb = &dep->trb_pool[dep->trb_dequeue];
2038 req->sg = sg_next(s);
2039 req->num_pending_sgs--;
2041 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2042 event, status, chain);
2047 trb = &dep->trb_pool[dep->trb_dequeue];
2048 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2049 event, status, chain);
2053 * We assume here we will always receive the entire data block
2054 * which we should receive. Meaning, if we program RX to
2055 * receive 4K but we receive only 2K, we assume that's all we
2056 * should receive and we simply bounce the request back to the
2057 * gadget driver for further processing.
2059 actual = length - req->request.actual;
2060 req->request.actual = actual;
2062 if (ret && chain && (actual < length) && req->num_pending_sgs)
2063 return __dwc3_gadget_kick_transfer(dep, 0);
2065 dwc3_gadget_giveback(dep, req, status);
2068 if ((event->status & DEPEVT_STATUS_IOC) &&
2069 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2076 * Our endpoint might get disabled by another thread during
2077 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2078 * early on so DWC3_EP_BUSY flag gets cleared
2080 if (!dep->endpoint.desc)
2083 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2084 list_empty(&dep->started_list)) {
2085 if (list_empty(&dep->pending_list)) {
2087 * If there is no entry in request list then do
2088 * not issue END TRANSFER now. Just set PENDING
2089 * flag, so that END TRANSFER is issued when an
2090 * entry is added into request list.
2092 dep->flags = DWC3_EP_PENDING_REQUEST;
2094 dwc3_stop_active_transfer(dwc, dep->number, true);
2095 dep->flags = DWC3_EP_ENABLED;
2100 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2106 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2107 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2109 unsigned status = 0;
2111 u32 is_xfer_complete;
2113 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2115 if (event->status & DEPEVT_STATUS_BUSERR)
2116 status = -ECONNRESET;
2118 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2119 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2120 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2121 dep->flags &= ~DWC3_EP_BUSY;
2124 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2125 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2127 if (dwc->revision < DWC3_REVISION_183A) {
2131 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2134 if (!(dep->flags & DWC3_EP_ENABLED))
2137 if (!list_empty(&dep->started_list))
2141 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2143 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2149 * Our endpoint might get disabled by another thread during
2150 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2151 * early on so DWC3_EP_BUSY flag gets cleared
2153 if (!dep->endpoint.desc)
2156 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2159 ret = __dwc3_gadget_kick_transfer(dep, 0);
2160 if (!ret || ret == -EBUSY)
2165 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2166 const struct dwc3_event_depevt *event)
2168 struct dwc3_ep *dep;
2169 u8 epnum = event->endpoint_number;
2171 dep = dwc->eps[epnum];
2173 if (!(dep->flags & DWC3_EP_ENABLED))
2176 if (epnum == 0 || epnum == 1) {
2177 dwc3_ep0_interrupt(dwc, event);
2181 switch (event->endpoint_event) {
2182 case DWC3_DEPEVT_XFERCOMPLETE:
2183 dep->resource_index = 0;
2185 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2186 dwc3_trace(trace_dwc3_gadget,
2187 "%s is an Isochronous endpoint",
2192 dwc3_endpoint_transfer_complete(dwc, dep, event);
2194 case DWC3_DEPEVT_XFERINPROGRESS:
2195 dwc3_endpoint_transfer_complete(dwc, dep, event);
2197 case DWC3_DEPEVT_XFERNOTREADY:
2198 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2199 dwc3_gadget_start_isoc(dwc, dep, event);
2204 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2206 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2207 dep->name, active ? "Transfer Active"
2208 : "Transfer Not Active");
2210 ret = __dwc3_gadget_kick_transfer(dep, 0);
2211 if (!ret || ret == -EBUSY)
2214 dwc3_trace(trace_dwc3_gadget,
2215 "%s: failed to kick transfers",
2220 case DWC3_DEPEVT_STREAMEVT:
2221 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2222 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2227 switch (event->status) {
2228 case DEPEVT_STREAMEVT_FOUND:
2229 dwc3_trace(trace_dwc3_gadget,
2230 "Stream %d found and started",
2234 case DEPEVT_STREAMEVT_NOTFOUND:
2237 dwc3_trace(trace_dwc3_gadget,
2238 "unable to find suitable stream");
2241 case DWC3_DEPEVT_RXTXFIFOEVT:
2242 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun", dep->name);
2244 case DWC3_DEPEVT_EPCMDCMPLT:
2245 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2250 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2252 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2253 spin_unlock(&dwc->lock);
2254 dwc->gadget_driver->disconnect(&dwc->gadget);
2255 spin_lock(&dwc->lock);
2259 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2261 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2262 spin_unlock(&dwc->lock);
2263 dwc->gadget_driver->suspend(&dwc->gadget);
2264 spin_lock(&dwc->lock);
2268 static void dwc3_resume_gadget(struct dwc3 *dwc)
2270 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2271 spin_unlock(&dwc->lock);
2272 dwc->gadget_driver->resume(&dwc->gadget);
2273 spin_lock(&dwc->lock);
2277 static void dwc3_reset_gadget(struct dwc3 *dwc)
2279 if (!dwc->gadget_driver)
2282 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2283 spin_unlock(&dwc->lock);
2284 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2285 spin_lock(&dwc->lock);
2289 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2291 struct dwc3_ep *dep;
2292 struct dwc3_gadget_ep_cmd_params params;
2296 dep = dwc->eps[epnum];
2298 if (!dep->resource_index)
2302 * NOTICE: We are violating what the Databook says about the
2303 * EndTransfer command. Ideally we would _always_ wait for the
2304 * EndTransfer Command Completion IRQ, but that's causing too
2305 * much trouble synchronizing between us and gadget driver.
2307 * We have discussed this with the IP Provider and it was
2308 * suggested to giveback all requests here, but give HW some
2309 * extra time to synchronize with the interconnect. We're using
2310 * an arbitrary 100us delay for that.
2312 * Note also that a similar handling was tested by Synopsys
2313 * (thanks a lot Paul) and nothing bad has come out of it.
2314 * In short, what we're doing is:
2316 * - Issue EndTransfer WITH CMDIOC bit set
2319 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2320 * supports a mode to work around the above limitation. The
2321 * software can poll the CMDACT bit in the DEPCMD register
2322 * after issuing a EndTransfer command. This mode is enabled
2323 * by writing GUCTL2[14]. This polling is already done in the
2324 * dwc3_send_gadget_ep_cmd() function so if the mode is
2325 * enabled, the EndTransfer command will have completed upon
2326 * returning from this function and we don't need to delay for
2329 * This mode is NOT available on the DWC_usb31 IP.
2332 cmd = DWC3_DEPCMD_ENDTRANSFER;
2333 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2334 cmd |= DWC3_DEPCMD_CMDIOC;
2335 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2336 memset(¶ms, 0, sizeof(params));
2337 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2339 dep->resource_index = 0;
2340 dep->flags &= ~DWC3_EP_BUSY;
2342 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A)
2346 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2350 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2351 struct dwc3_ep *dep;
2353 dep = dwc->eps[epnum];
2357 if (!(dep->flags & DWC3_EP_ENABLED))
2360 dwc3_remove_requests(dwc, dep);
2364 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2368 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2369 struct dwc3_ep *dep;
2372 dep = dwc->eps[epnum];
2376 if (!(dep->flags & DWC3_EP_STALL))
2379 dep->flags &= ~DWC3_EP_STALL;
2381 ret = dwc3_send_clear_stall_ep_cmd(dep);
2386 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2390 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2391 reg &= ~DWC3_DCTL_INITU1ENA;
2392 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2394 reg &= ~DWC3_DCTL_INITU2ENA;
2395 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2397 dwc3_disconnect_gadget(dwc);
2399 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2400 dwc->setup_packet_pending = false;
2401 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2403 dwc->connected = false;
2406 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2410 dwc->connected = true;
2413 * Ideally, dwc3_reset_gadget() would trigger the function
2414 * drivers to stop any active transfers through ep disable.
2415 * However, for functions which defer ep disable, such as mass
2416 * storage, we will need to rely on the call to stop active
2417 * transfers here, and avoid allowing of request queuing.
2419 dwc->connected = false;
2422 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2423 * would cause a missing Disconnect Event if there's a
2424 * pending Setup Packet in the FIFO.
2426 * There's no suggested workaround on the official Bug
2427 * report, which states that "unless the driver/application
2428 * is doing any special handling of a disconnect event,
2429 * there is no functional issue".
2431 * Unfortunately, it turns out that we _do_ some special
2432 * handling of a disconnect event, namely complete all
2433 * pending transfers, notify gadget driver of the
2434 * disconnection, and so on.
2436 * Our suggested workaround is to follow the Disconnect
2437 * Event steps here, instead, based on a setup_packet_pending
2438 * flag. Such flag gets set whenever we have a SETUP_PENDING
2439 * status for EP0 TRBs and gets cleared on XferComplete for the
2444 * STAR#9000466709: RTL: Device : Disconnect event not
2445 * generated if setup packet pending in FIFO
2447 if (dwc->revision < DWC3_REVISION_188A) {
2448 if (dwc->setup_packet_pending)
2449 dwc3_gadget_disconnect_interrupt(dwc);
2452 dwc3_reset_gadget(dwc);
2454 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2455 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2456 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2457 dwc->test_mode = false;
2459 dwc3_stop_active_transfers(dwc);
2460 dwc3_clear_stall_all_ep(dwc);
2462 /* Reset device address to zero */
2463 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2464 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2465 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2468 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2471 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2474 * We change the clock only at SS but I dunno why I would want to do
2475 * this. Maybe it becomes part of the power saving plan.
2478 if ((speed != DWC3_DSTS_SUPERSPEED) &&
2479 (speed != DWC3_DSTS_SUPERSPEED_PLUS))
2483 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2484 * each time on Connect Done.
2489 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2490 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2491 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2494 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2496 struct dwc3_ep *dep;
2501 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2502 speed = reg & DWC3_DSTS_CONNECTSPD;
2505 dwc3_update_ram_clk_sel(dwc, speed);
2508 case DWC3_DSTS_SUPERSPEED_PLUS:
2509 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2510 dwc->gadget.ep0->maxpacket = 512;
2511 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2513 case DWC3_DSTS_SUPERSPEED:
2515 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2516 * would cause a missing USB3 Reset event.
2518 * In such situations, we should force a USB3 Reset
2519 * event by calling our dwc3_gadget_reset_interrupt()
2524 * STAR#9000483510: RTL: SS : USB3 reset event may
2525 * not be generated always when the link enters poll
2527 if (dwc->revision < DWC3_REVISION_190A)
2528 dwc3_gadget_reset_interrupt(dwc);
2530 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2531 dwc->gadget.ep0->maxpacket = 512;
2532 dwc->gadget.speed = USB_SPEED_SUPER;
2534 case DWC3_DSTS_HIGHSPEED:
2535 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2536 dwc->gadget.ep0->maxpacket = 64;
2537 dwc->gadget.speed = USB_SPEED_HIGH;
2539 case DWC3_DSTS_FULLSPEED:
2540 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2541 dwc->gadget.ep0->maxpacket = 64;
2542 dwc->gadget.speed = USB_SPEED_FULL;
2544 case DWC3_DSTS_LOWSPEED:
2545 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2546 dwc->gadget.ep0->maxpacket = 8;
2547 dwc->gadget.speed = USB_SPEED_LOW;
2551 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2553 /* Enable USB2 LPM Capability */
2555 if ((dwc->revision > DWC3_REVISION_194A) &&
2556 (speed != DWC3_DSTS_SUPERSPEED) &&
2557 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2558 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2559 reg |= DWC3_DCFG_LPM_CAP;
2560 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2562 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2563 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2565 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2568 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2569 * DCFG.LPMCap is set, core responses with an ACK and the
2570 * BESL value in the LPM token is less than or equal to LPM
2573 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2574 && dwc->has_lpm_erratum,
2575 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2577 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2578 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2580 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2582 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2583 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2584 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2588 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2591 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2596 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2599 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2604 * Configure PHY via GUSB3PIPECTLn if required.
2606 * Update GTXFIFOSIZn
2608 * In both cases reset values should be sufficient.
2612 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2615 * TODO take core out of low power mode when that's
2619 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2620 spin_unlock(&dwc->lock);
2621 dwc->gadget_driver->resume(&dwc->gadget);
2622 spin_lock(&dwc->lock);
2626 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2627 unsigned int evtinfo)
2629 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2630 unsigned int pwropt;
2633 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2634 * Hibernation mode enabled which would show up when device detects
2635 * host-initiated U3 exit.
2637 * In that case, device will generate a Link State Change Interrupt
2638 * from U3 to RESUME which is only necessary if Hibernation is
2641 * There are no functional changes due to such spurious event and we
2642 * just need to ignore it.
2646 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2649 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2650 if ((dwc->revision < DWC3_REVISION_250A) &&
2651 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2652 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2653 (next == DWC3_LINK_STATE_RESUME)) {
2654 dwc3_trace(trace_dwc3_gadget,
2655 "ignoring transition U3 -> Resume");
2661 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2662 * on the link partner, the USB session might do multiple entry/exit
2663 * of low power states before a transfer takes place.
2665 * Due to this problem, we might experience lower throughput. The
2666 * suggested workaround is to disable DCTL[12:9] bits if we're
2667 * transitioning from U1/U2 to U0 and enable those bits again
2668 * after a transfer completes and there are no pending transfers
2669 * on any of the enabled endpoints.
2671 * This is the first half of that workaround.
2675 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2676 * core send LGO_Ux entering U0
2678 if (dwc->revision < DWC3_REVISION_183A) {
2679 if (next == DWC3_LINK_STATE_U0) {
2683 switch (dwc->link_state) {
2684 case DWC3_LINK_STATE_U1:
2685 case DWC3_LINK_STATE_U2:
2686 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2687 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2688 | DWC3_DCTL_ACCEPTU2ENA
2689 | DWC3_DCTL_INITU1ENA
2690 | DWC3_DCTL_ACCEPTU1ENA);
2693 dwc->u1u2 = reg & u1u2;
2697 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2707 case DWC3_LINK_STATE_U1:
2708 if (dwc->speed == USB_SPEED_SUPER)
2709 dwc3_suspend_gadget(dwc);
2711 case DWC3_LINK_STATE_U2:
2712 case DWC3_LINK_STATE_U3:
2713 dwc3_suspend_gadget(dwc);
2715 case DWC3_LINK_STATE_RESUME:
2716 dwc3_resume_gadget(dwc);
2723 dwc->link_state = next;
2726 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2727 unsigned int evtinfo)
2729 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2731 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2732 dwc3_suspend_gadget(dwc);
2734 dwc->link_state = next;
2737 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2738 unsigned int evtinfo)
2740 unsigned int is_ss = evtinfo & BIT(4);
2743 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2744 * have a known issue which can cause USB CV TD.9.23 to fail
2747 * Because of this issue, core could generate bogus hibernation
2748 * events which SW needs to ignore.
2752 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2753 * Device Fallback from SuperSpeed
2755 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2758 /* enter hibernation here */
2761 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2762 const struct dwc3_event_devt *event)
2764 switch (event->type) {
2765 case DWC3_DEVICE_EVENT_DISCONNECT:
2766 dwc3_gadget_disconnect_interrupt(dwc);
2768 case DWC3_DEVICE_EVENT_RESET:
2769 dwc3_gadget_reset_interrupt(dwc);
2771 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2772 dwc3_gadget_conndone_interrupt(dwc);
2774 case DWC3_DEVICE_EVENT_WAKEUP:
2775 dwc3_gadget_wakeup_interrupt(dwc);
2777 case DWC3_DEVICE_EVENT_HIBER_REQ:
2778 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2779 "unexpected hibernation event\n"))
2782 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2784 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2785 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2787 case DWC3_DEVICE_EVENT_EOPF:
2788 /* It changed to be suspend event for version 2.30a and above */
2789 if (dwc->revision < DWC3_REVISION_230A) {
2790 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2792 dwc3_trace(trace_dwc3_gadget, "U3/L1-L2 Suspend Event");
2795 * Ignore suspend event until the gadget enters into
2796 * USB_STATE_CONFIGURED state.
2798 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2799 dwc3_gadget_suspend_interrupt(dwc,
2803 case DWC3_DEVICE_EVENT_SOF:
2804 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2806 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2807 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2809 case DWC3_DEVICE_EVENT_CMD_CMPL:
2810 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2812 case DWC3_DEVICE_EVENT_OVERFLOW:
2813 dwc3_trace(trace_dwc3_gadget, "Overflow");
2816 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2820 static void dwc3_process_event_entry(struct dwc3 *dwc,
2821 const union dwc3_event *event)
2823 trace_dwc3_event(event->raw);
2825 /* Endpoint IRQ, handle it and return early */
2826 if (event->type.is_devspec == 0) {
2828 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2831 switch (event->type.type) {
2832 case DWC3_EVENT_TYPE_DEV:
2833 dwc3_gadget_interrupt(dwc, &event->devt);
2835 /* REVISIT what to do with Carkit and I2C events ? */
2837 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2841 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2843 struct dwc3 *dwc = evt->dwc;
2844 irqreturn_t ret = IRQ_NONE;
2850 if (!(evt->flags & DWC3_EVENT_PENDING))
2854 union dwc3_event event;
2856 event.raw = *(u32 *) (evt->buf + evt->lpos);
2858 dwc3_process_event_entry(dwc, &event);
2861 * FIXME we wrap around correctly to the next entry as
2862 * almost all entries are 4 bytes in size. There is one
2863 * entry which has 12 bytes which is a regular entry
2864 * followed by 8 bytes data. ATM I don't know how
2865 * things are organized if we get next to the a
2866 * boundary so I worry about that once we try to handle
2869 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2872 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2876 evt->flags &= ~DWC3_EVENT_PENDING;
2879 /* Unmask interrupt */
2880 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2881 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2882 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2887 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2889 struct dwc3_event_buffer *evt = _evt;
2890 struct dwc3 *dwc = evt->dwc;
2891 unsigned long flags;
2892 irqreturn_t ret = IRQ_NONE;
2894 spin_lock_irqsave(&dwc->lock, flags);
2895 ret = dwc3_process_event_buf(evt);
2896 spin_unlock_irqrestore(&dwc->lock, flags);
2901 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2903 struct dwc3 *dwc = evt->dwc;
2907 if (pm_runtime_suspended(dwc->dev)) {
2908 pm_runtime_get(dwc->dev);
2909 disable_irq_nosync(dwc->irq_gadget);
2910 dwc->pending_events = true;
2915 * With PCIe legacy interrupt, test shows that top-half irq handler can
2916 * be called again after HW interrupt deassertion. Check if bottom-half
2917 * irq event handler completes before caching new event to prevent
2920 if (evt->flags & DWC3_EVENT_PENDING)
2923 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2924 count &= DWC3_GEVNTCOUNT_MASK;
2929 evt->flags |= DWC3_EVENT_PENDING;
2931 /* Mask interrupt */
2932 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2933 reg |= DWC3_GEVNTSIZ_INTMASK;
2934 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2936 return IRQ_WAKE_THREAD;
2939 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2941 struct dwc3_event_buffer *evt = _evt;
2943 return dwc3_check_event_buf(evt);
2947 * dwc3_gadget_init - Initializes gadget related registers
2948 * @dwc: pointer to our controller context structure
2950 * Returns 0 on success otherwise negative errno.
2952 int dwc3_gadget_init(struct dwc3 *dwc)
2955 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
2957 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
2958 if (irq == -EPROBE_DEFER)
2962 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
2963 if (irq == -EPROBE_DEFER)
2967 irq = platform_get_irq(dwc3_pdev, 0);
2969 if (irq != -EPROBE_DEFER) {
2971 "missing peripheral IRQ\n");
2980 dwc->irq_gadget = irq;
2982 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2983 &dwc->ctrl_req_addr, GFP_KERNEL);
2984 if (!dwc->ctrl_req) {
2985 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2990 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2991 &dwc->ep0_trb_addr, GFP_KERNEL);
2992 if (!dwc->ep0_trb) {
2993 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2998 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2999 if (!dwc->setup_buf) {
3004 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
3005 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
3007 if (!dwc->ep0_bounce) {
3008 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
3013 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
3014 if (!dwc->zlp_buf) {
3019 dwc->gadget.ops = &dwc3_gadget_ops;
3020 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3021 dwc->gadget.sg_supported = true;
3022 dwc->gadget.name = "dwc3-gadget";
3025 * FIXME We might be setting max_speed to <SUPER, however versions
3026 * <2.20a of dwc3 have an issue with metastability (documented
3027 * elsewhere in this driver) which tells us we can't set max speed to
3028 * anything lower than SUPER.
3030 * Because gadget.max_speed is only used by composite.c and function
3031 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3032 * to happen so we avoid sending SuperSpeed Capability descriptor
3033 * together with our BOS descriptor as that could confuse host into
3034 * thinking we can handle super speed.
3036 * Note that, in fact, we won't even support GetBOS requests when speed
3037 * is less than super speed because we don't have means, yet, to tell
3038 * composite.c that we are USB 2.0 + LPM ECN.
3040 if (dwc->revision < DWC3_REVISION_220A)
3041 dwc3_trace(trace_dwc3_gadget,
3042 "Changing max_speed on rev %08x",
3045 dwc->gadget.max_speed = dwc->maximum_speed;
3048 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
3051 dwc->gadget.quirk_ep_out_aligned_size = true;
3054 * REVISIT: Here we should clear all pending IRQs to be
3055 * sure we're starting from a well known location.
3058 ret = dwc3_gadget_init_endpoints(dwc);
3062 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3064 dev_err(dwc->dev, "failed to register udc\n");
3071 kfree(dwc->zlp_buf);
3074 dwc3_gadget_free_endpoints(dwc);
3075 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3076 dwc->ep0_bounce, dwc->ep0_bounce_addr);
3079 kfree(dwc->setup_buf);
3082 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
3083 dwc->ep0_trb, dwc->ep0_trb_addr);
3086 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3087 dwc->ctrl_req, dwc->ctrl_req_addr);
3093 /* -------------------------------------------------------------------------- */
3095 void dwc3_gadget_exit(struct dwc3 *dwc)
3097 usb_del_gadget_udc(&dwc->gadget);
3099 dwc3_gadget_free_endpoints(dwc);
3101 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3102 dwc->ep0_bounce, dwc->ep0_bounce_addr);
3104 kfree(dwc->setup_buf);
3105 kfree(dwc->zlp_buf);
3107 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
3108 dwc->ep0_trb, dwc->ep0_trb_addr);
3110 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3111 dwc->ctrl_req, dwc->ctrl_req_addr);
3114 int dwc3_gadget_suspend(struct dwc3 *dwc)
3116 if (!dwc->gadget_driver)
3119 dwc3_gadget_run_stop(dwc, false, false);
3120 dwc3_disconnect_gadget(dwc);
3121 __dwc3_gadget_stop(dwc);
3123 synchronize_irq(dwc->irq_gadget);
3128 int dwc3_gadget_resume(struct dwc3 *dwc)
3132 if (!dwc->gadget_driver)
3135 ret = __dwc3_gadget_start(dwc);
3139 ret = dwc3_gadget_run_stop(dwc, true, false);
3146 __dwc3_gadget_stop(dwc);
3152 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3154 if (dwc->pending_events) {
3155 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3156 dwc->pending_events = false;
3157 enable_irq(dwc->irq_gadget);