2 * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
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19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * This file contains the interrupt handlers for Host mode
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/spinlock.h>
43 #include <linux/interrupt.h>
44 #include <linux/dma-mapping.h>
46 #include <linux/slab.h>
47 #include <linux/usb.h>
49 #include <linux/usb/hcd.h>
50 #include <linux/usb/ch11.h>
55 /* This function is for debug only */
56 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
58 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
59 u16 curr_frame_number = hsotg->frame_number;
61 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
62 if (((hsotg->last_frame_num + 1) & HFNUM_MAX_FRNUM) !=
64 hsotg->frame_num_array[hsotg->frame_num_idx] =
66 hsotg->last_frame_num_array[hsotg->frame_num_idx] =
67 hsotg->last_frame_num;
68 hsotg->frame_num_idx++;
70 } else if (!hsotg->dumped_frame_num_array) {
73 dev_info(hsotg->dev, "Frame Last Frame\n");
74 dev_info(hsotg->dev, "----- ----------\n");
75 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
76 dev_info(hsotg->dev, "0x%04x 0x%04x\n",
77 hsotg->frame_num_array[i],
78 hsotg->last_frame_num_array[i]);
80 hsotg->dumped_frame_num_array = 1;
82 hsotg->last_frame_num = curr_frame_number;
86 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
87 struct dwc2_host_chan *chan,
95 if (chan->qh->dev_speed == USB_SPEED_HIGH)
101 usb_urb = qtd->urb->priv;
102 if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
105 if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
106 chan->qh->tt_buffer_dirty = 1;
107 if (usb_hub_clear_tt_buffer(usb_urb))
108 /* Clear failed; let's hope things work anyway */
109 chan->qh->tt_buffer_dirty = 0;
114 * Handles the start-of-frame interrupt in host mode. Non-periodic
115 * transactions may be queued to the DWC_otg controller for the current
116 * (micro)frame. Periodic transactions may be queued to the controller
117 * for the next (micro)frame.
119 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
121 struct list_head *qh_entry;
123 enum dwc2_transaction_type tr_type;
126 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
129 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
131 dwc2_track_missed_sofs(hsotg);
133 /* Determine whether any periodic QHs should be executed */
134 qh_entry = hsotg->periodic_sched_inactive.next;
135 while (qh_entry != &hsotg->periodic_sched_inactive) {
136 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
137 qh_entry = qh_entry->next;
138 if (dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number))
140 * Move QH to the ready list to be executed next
143 list_move(&qh->qh_list_entry,
144 &hsotg->periodic_sched_ready);
146 tr_type = dwc2_hcd_select_transactions(hsotg);
147 if (tr_type != DWC2_TRANSACTION_NONE)
148 dwc2_hcd_queue_transactions(hsotg, tr_type);
150 /* Clear interrupt */
151 dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
155 * Handles the Rx FIFO Level Interrupt, which indicates that there is
156 * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
157 * memory if the DWC_otg controller is operating in Slave mode.
159 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
161 u32 grxsts, chnum, bcnt, dpid, pktsts;
162 struct dwc2_host_chan *chan;
165 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
167 grxsts = dwc2_readl(hsotg->regs + GRXSTSP);
168 chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
169 chan = hsotg->hc_ptr_array[chnum];
171 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
175 bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
176 dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
177 pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
181 dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum);
182 dev_vdbg(hsotg->dev, " Count = %d\n", bcnt);
183 dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid,
184 chan->data_pid_start);
185 dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts);
189 case GRXSTS_PKTSTS_HCHIN:
190 /* Read the data into the host buffer */
192 dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
194 /* Update the HC fields for the next packet received */
195 chan->xfer_count += bcnt;
196 chan->xfer_buf += bcnt;
199 case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
200 case GRXSTS_PKTSTS_DATATOGGLEERR:
201 case GRXSTS_PKTSTS_HCHHALTED:
202 /* Handled in interrupt, just ignore data */
206 "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
212 * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
213 * data packets may be written to the FIFO for OUT transfers. More requests
214 * may be written to the non-periodic request queue for IN transfers. This
215 * interrupt is enabled only in Slave mode.
217 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
219 dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
220 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
224 * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
225 * packets may be written to the FIFO for OUT transfers. More requests may be
226 * written to the periodic request queue for IN transfers. This interrupt is
227 * enabled only in Slave mode.
229 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
232 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
233 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
236 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
239 struct dwc2_core_params *params = hsotg->core_params;
247 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
249 /* Every time when port enables calculate HFIR.FrInterval */
250 hfir = dwc2_readl(hsotg->regs + HFIR);
251 hfir &= ~HFIR_FRINT_MASK;
252 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
254 dwc2_writel(hfir, hsotg->regs + HFIR);
256 /* Check if we need to adjust the PHY clock speed for low power */
257 if (!params->host_support_fs_ls_low_power) {
258 /* Port has been enabled, set the reset change flag */
259 hsotg->flags.b.port_reset_change = 1;
263 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
264 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
266 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
268 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
269 /* Set PHY low power clock select for FS/LS devices */
270 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
271 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
275 hcfg = dwc2_readl(hsotg->regs + HCFG);
276 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
277 HCFG_FSLSPCLKSEL_SHIFT;
279 if (prtspd == HPRT0_SPD_LOW_SPEED &&
280 params->host_ls_low_power_phy_clk ==
281 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
284 "FS_PHY programming HCFG to 6 MHz\n");
285 if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
286 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
287 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
288 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
289 dwc2_writel(hcfg, hsotg->regs + HCFG);
295 "FS_PHY programming HCFG to 48 MHz\n");
296 if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
297 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
298 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
299 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
300 dwc2_writel(hcfg, hsotg->regs + HCFG);
306 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
307 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
308 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
314 *hprt0_modify |= HPRT0_RST;
315 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
316 msecs_to_jiffies(60));
318 /* Port has been enabled, set the reset change flag */
319 hsotg->flags.b.port_reset_change = 1;
324 * There are multiple conditions that can cause a port interrupt. This function
325 * determines which interrupt conditions have occurred and handles them
328 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
333 dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
335 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
336 hprt0_modify = hprt0;
339 * Clear appropriate bits in HPRT0 to clear the interrupt bit in
342 hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
346 * Port Connect Detected
347 * Set flag and clear if detected
349 if (hprt0 & HPRT0_CONNDET) {
351 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
353 if (hsotg->lx_state != DWC2_L0)
354 usb_hcd_resume_root_hub(hsotg->priv);
356 hsotg->flags.b.port_connect_status_change = 1;
357 hsotg->flags.b.port_connect_status = 1;
358 hprt0_modify |= HPRT0_CONNDET;
361 * The Hub driver asserts a reset when it sees port connect
367 * Port Enable Changed
368 * Clear if detected - Set internal flag if disabled
370 if (hprt0 & HPRT0_ENACHG) {
372 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
373 hprt0, !!(hprt0 & HPRT0_ENA));
374 hprt0_modify |= HPRT0_ENACHG;
375 if (hprt0 & HPRT0_ENA)
376 dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
378 hsotg->flags.b.port_enable_change = 1;
381 /* Overcurrent Change Interrupt */
382 if (hprt0 & HPRT0_OVRCURRCHG) {
384 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
386 hsotg->flags.b.port_over_current_change = 1;
387 hprt0_modify |= HPRT0_OVRCURRCHG;
390 /* Clear Port Interrupts */
391 dwc2_writel(hprt0_modify, hsotg->regs + HPRT0);
395 * Gets the actual length of a transfer after the transfer halts. halt_status
396 * holds the reason for the halt.
398 * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
399 * is set to 1 upon return if less than the requested number of bytes were
400 * transferred. short_read may also be NULL on entry, in which case it remains
403 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
404 struct dwc2_host_chan *chan, int chnum,
405 struct dwc2_qtd *qtd,
406 enum dwc2_halt_status halt_status,
409 u32 hctsiz, count, length;
411 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
413 if (halt_status == DWC2_HC_XFER_COMPLETE) {
414 if (chan->ep_is_in) {
415 count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
417 length = chan->xfer_len - count;
418 if (short_read != NULL)
419 *short_read = (count != 0);
420 } else if (chan->qh->do_split) {
421 length = qtd->ssplit_out_xfer_count;
423 length = chan->xfer_len;
427 * Must use the hctsiz.pktcnt field to determine how much data
428 * has been transferred. This field reflects the number of
429 * packets that have been transferred via the USB. This is
430 * always an integral number of packets if the transfer was
431 * halted before its normal completion. (Can't use the
432 * hctsiz.xfersize field because that reflects the number of
433 * bytes transferred via the AHB, not the USB).
435 count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
436 length = (chan->start_pkt_count - count) * chan->max_packet;
443 * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
444 * Complete interrupt on the host channel. Updates the actual_length field
445 * of the URB based on the number of bytes transferred via the host channel.
446 * Sets the URB status if the data transfer is finished.
448 * Return: 1 if the data transfer specified by the URB is completely finished,
451 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
452 struct dwc2_host_chan *chan, int chnum,
453 struct dwc2_hcd_urb *urb,
454 struct dwc2_qtd *qtd)
459 int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
460 DWC2_HC_XFER_COMPLETE,
463 if (urb->actual_length + xfer_length > urb->length) {
464 dev_dbg(hsotg->dev, "%s(): trimming xfer length\n", __func__);
465 xfer_length = urb->length - urb->actual_length;
468 /* Non DWORD-aligned buffer case handling */
469 if (chan->align_buf && xfer_length) {
470 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
471 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
472 chan->qh->dw_align_buf_size,
474 DMA_FROM_DEVICE : DMA_TO_DEVICE);
476 memcpy(urb->buf + urb->actual_length,
477 chan->qh->dw_align_buf, xfer_length);
480 dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
481 urb->actual_length, xfer_length);
482 urb->actual_length += xfer_length;
484 if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
485 (urb->flags & URB_SEND_ZERO_PACKET) &&
486 urb->actual_length >= urb->length &&
487 !(urb->length % chan->max_packet)) {
489 } else if (short_read || urb->actual_length >= urb->length) {
494 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
495 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
496 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
497 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
498 dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n",
499 (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
500 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length);
501 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length);
502 dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read,
509 * Save the starting data toggle for the next transfer. The data toggle is
510 * saved in the QH for non-control transfers and it's saved in the QTD for
513 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
514 struct dwc2_host_chan *chan, int chnum,
515 struct dwc2_qtd *qtd)
517 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
518 u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
520 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
521 if (pid == TSIZ_SC_MC_PID_DATA0)
522 chan->qh->data_toggle = DWC2_HC_PID_DATA0;
524 chan->qh->data_toggle = DWC2_HC_PID_DATA1;
526 if (pid == TSIZ_SC_MC_PID_DATA0)
527 qtd->data_toggle = DWC2_HC_PID_DATA0;
529 qtd->data_toggle = DWC2_HC_PID_DATA1;
534 * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
535 * the transfer is stopped for any reason. The fields of the current entry in
536 * the frame descriptor array are set based on the transfer state and the input
537 * halt_status. Completes the Isochronous URB if all the URB frames have been
540 * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
541 * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
543 static enum dwc2_halt_status dwc2_update_isoc_urb_state(
544 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
545 int chnum, struct dwc2_qtd *qtd,
546 enum dwc2_halt_status halt_status)
548 struct dwc2_hcd_iso_packet_desc *frame_desc;
549 struct dwc2_hcd_urb *urb = qtd->urb;
552 return DWC2_HC_XFER_NO_HALT_STATUS;
554 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
556 switch (halt_status) {
557 case DWC2_HC_XFER_COMPLETE:
558 frame_desc->status = 0;
559 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
560 chan, chnum, qtd, halt_status, NULL);
562 /* Non DWORD-aligned buffer case handling */
563 if (chan->align_buf && frame_desc->actual_length) {
564 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n",
566 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
567 chan->qh->dw_align_buf_size,
569 DMA_FROM_DEVICE : DMA_TO_DEVICE);
571 memcpy(urb->buf + frame_desc->offset +
572 qtd->isoc_split_offset,
573 chan->qh->dw_align_buf,
574 frame_desc->actual_length);
577 case DWC2_HC_XFER_FRAME_OVERRUN:
580 frame_desc->status = -ENOSR;
582 frame_desc->status = -ECOMM;
583 frame_desc->actual_length = 0;
585 case DWC2_HC_XFER_BABBLE_ERR:
587 frame_desc->status = -EOVERFLOW;
588 /* Don't need to update actual_length in this case */
590 case DWC2_HC_XFER_XACT_ERR:
592 frame_desc->status = -EPROTO;
593 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
594 chan, chnum, qtd, halt_status, NULL);
596 /* Non DWORD-aligned buffer case handling */
597 if (chan->align_buf && frame_desc->actual_length) {
598 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n",
600 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
601 chan->qh->dw_align_buf_size,
603 DMA_FROM_DEVICE : DMA_TO_DEVICE);
605 memcpy(urb->buf + frame_desc->offset +
606 qtd->isoc_split_offset,
607 chan->qh->dw_align_buf,
608 frame_desc->actual_length);
611 /* Skip whole frame */
612 if (chan->qh->do_split &&
613 chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
614 hsotg->core_params->dma_enable > 0) {
615 qtd->complete_split = 0;
616 qtd->isoc_split_offset = 0;
621 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
626 if (++qtd->isoc_frame_index == urb->packet_count) {
628 * urb->status is not used for isoc transfers. The individual
629 * frame_desc statuses are used instead.
631 dwc2_host_complete(hsotg, qtd, 0);
632 halt_status = DWC2_HC_XFER_URB_COMPLETE;
634 halt_status = DWC2_HC_XFER_COMPLETE;
641 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
642 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
643 * still linked to the QH, the QH is added to the end of the inactive
644 * non-periodic schedule. For periodic QHs, removes the QH from the periodic
645 * schedule if no more QTDs are linked to the QH.
647 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
650 int continue_split = 0;
651 struct dwc2_qtd *qtd;
654 dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__,
655 hsotg, qh, free_qtd);
657 if (list_empty(&qh->qtd_list)) {
658 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
662 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
664 if (qtd->complete_split)
666 else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
667 qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
671 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
677 qh->channel->align_buf = 0;
679 dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
683 * dwc2_release_channel() - Releases a host channel for use by other transfers
685 * @hsotg: The HCD state structure
686 * @chan: The host channel to release
687 * @qtd: The QTD associated with the host channel. This QTD may be
688 * freed if the transfer is complete or an error has occurred.
689 * @halt_status: Reason the channel is being released. This status
690 * determines the actions taken by this function.
692 * Also attempts to select and queue more transactions since at least one host
693 * channel is available.
695 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
696 struct dwc2_host_chan *chan,
697 struct dwc2_qtd *qtd,
698 enum dwc2_halt_status halt_status)
700 enum dwc2_transaction_type tr_type;
705 dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n",
706 __func__, chan->hc_num, halt_status);
708 switch (halt_status) {
709 case DWC2_HC_XFER_URB_COMPLETE:
712 case DWC2_HC_XFER_AHB_ERR:
713 case DWC2_HC_XFER_STALL:
714 case DWC2_HC_XFER_BABBLE_ERR:
717 case DWC2_HC_XFER_XACT_ERR:
718 if (qtd && qtd->error_count >= 3) {
720 " Complete URB with transaction error\n");
722 dwc2_host_complete(hsotg, qtd, -EPROTO);
725 case DWC2_HC_XFER_URB_DEQUEUE:
727 * The QTD has already been removed and the QH has been
728 * deactivated. Don't want to do anything except release the
729 * host channel and try to queue more transfers.
732 case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
733 dev_vdbg(hsotg->dev, " Complete URB with I/O error\n");
735 dwc2_host_complete(hsotg, qtd, -EIO);
737 case DWC2_HC_XFER_NO_HALT_STATUS:
742 dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
746 * Release the host channel for use by other transfers. The cleanup
747 * function clears the channel interrupt enables and conditions, so
748 * there's no need to clear the Channel Halted interrupt separately.
750 if (!list_empty(&chan->hc_list_entry))
751 list_del(&chan->hc_list_entry);
752 dwc2_hc_cleanup(hsotg, chan);
753 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
755 if (hsotg->core_params->uframe_sched > 0) {
756 hsotg->available_host_channels++;
758 switch (chan->ep_type) {
759 case USB_ENDPOINT_XFER_CONTROL:
760 case USB_ENDPOINT_XFER_BULK:
761 hsotg->non_periodic_channels--;
765 * Don't release reservations for periodic channels
766 * here. That's done when a periodic transfer is
767 * descheduled (i.e. when the QH is removed from the
768 * periodic schedule).
774 haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
775 haintmsk &= ~(1 << chan->hc_num);
776 dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
778 /* Try to queue more transfers now that there's a free channel */
779 tr_type = dwc2_hcd_select_transactions(hsotg);
780 if (tr_type != DWC2_TRANSACTION_NONE)
781 dwc2_hcd_queue_transactions(hsotg, tr_type);
785 * Halts a host channel. If the channel cannot be halted immediately because
786 * the request queue is full, this function ensures that the FIFO empty
787 * interrupt for the appropriate queue is enabled so that the halt request can
788 * be queued when there is space in the request queue.
790 * This function may also be called in DMA mode. In that case, the channel is
791 * simply released since the core always halts the channel automatically in
794 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
795 struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
796 enum dwc2_halt_status halt_status)
799 dev_vdbg(hsotg->dev, "%s()\n", __func__);
801 if (hsotg->core_params->dma_enable > 0) {
803 dev_vdbg(hsotg->dev, "DMA enabled\n");
804 dwc2_release_channel(hsotg, chan, qtd, halt_status);
808 /* Slave mode processing */
809 dwc2_hc_halt(hsotg, chan, halt_status);
811 if (chan->halt_on_queue) {
814 dev_vdbg(hsotg->dev, "Halt on queue\n");
815 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
816 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
817 dev_vdbg(hsotg->dev, "control/bulk\n");
819 * Make sure the Non-periodic Tx FIFO empty interrupt
820 * is enabled so that the non-periodic schedule will
823 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
824 gintmsk |= GINTSTS_NPTXFEMP;
825 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
827 dev_vdbg(hsotg->dev, "isoc/intr\n");
829 * Move the QH from the periodic queued schedule to
830 * the periodic assigned schedule. This allows the
831 * halt to be queued when the periodic schedule is
834 list_move(&chan->qh->qh_list_entry,
835 &hsotg->periodic_sched_assigned);
838 * Make sure the Periodic Tx FIFO Empty interrupt is
839 * enabled so that the periodic schedule will be
842 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
843 gintmsk |= GINTSTS_PTXFEMP;
844 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
850 * Performs common cleanup for non-periodic transfers after a Transfer
851 * Complete interrupt. This function should be called after any endpoint type
852 * specific handling is finished to release the host channel.
854 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
855 struct dwc2_host_chan *chan,
856 int chnum, struct dwc2_qtd *qtd,
857 enum dwc2_halt_status halt_status)
859 dev_vdbg(hsotg->dev, "%s()\n", __func__);
861 qtd->error_count = 0;
863 if (chan->hcint & HCINTMSK_NYET) {
865 * Got a NYET on the last transaction of the transfer. This
866 * means that the endpoint should be in the PING state at the
867 * beginning of the next transfer.
869 dev_vdbg(hsotg->dev, "got NYET\n");
870 chan->qh->ping_state = 1;
874 * Always halt and release the host channel to make it available for
875 * more transfers. There may still be more phases for a control
876 * transfer or more data packets for a bulk transfer at this point,
877 * but the host channel is still halted. A channel will be reassigned
878 * to the transfer when the non-periodic schedule is processed after
879 * the channel is released. This allows transactions to be queued
880 * properly via dwc2_hcd_queue_transactions, which also enables the
881 * Tx FIFO Empty interrupt if necessary.
883 if (chan->ep_is_in) {
885 * IN transfers in Slave mode require an explicit disable to
886 * halt the channel. (In DMA mode, this call simply releases
889 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
892 * The channel is automatically disabled by the core for OUT
893 * transfers in Slave mode
895 dwc2_release_channel(hsotg, chan, qtd, halt_status);
900 * Performs common cleanup for periodic transfers after a Transfer Complete
901 * interrupt. This function should be called after any endpoint type specific
902 * handling is finished to release the host channel.
904 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
905 struct dwc2_host_chan *chan, int chnum,
906 struct dwc2_qtd *qtd,
907 enum dwc2_halt_status halt_status)
909 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
911 qtd->error_count = 0;
913 if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
914 /* Core halts channel in these cases */
915 dwc2_release_channel(hsotg, chan, qtd, halt_status);
917 /* Flush any outstanding requests from the Tx queue */
918 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
921 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
922 struct dwc2_host_chan *chan, int chnum,
923 struct dwc2_qtd *qtd)
925 struct dwc2_hcd_iso_packet_desc *frame_desc;
931 frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
932 len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
933 DWC2_HC_XFER_COMPLETE, NULL);
934 if (!len && !qtd->isoc_split_offset) {
935 qtd->complete_split = 0;
939 frame_desc->actual_length += len;
941 if (chan->align_buf) {
942 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
943 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
944 chan->qh->dw_align_buf_size, DMA_FROM_DEVICE);
945 memcpy(qtd->urb->buf + frame_desc->offset +
946 qtd->isoc_split_offset, chan->qh->dw_align_buf, len);
949 qtd->isoc_split_offset += len;
951 if (frame_desc->actual_length >= frame_desc->length) {
952 frame_desc->status = 0;
953 qtd->isoc_frame_index++;
954 qtd->complete_split = 0;
955 qtd->isoc_split_offset = 0;
958 if (qtd->isoc_frame_index == qtd->urb->packet_count) {
959 dwc2_host_complete(hsotg, qtd, 0);
960 dwc2_release_channel(hsotg, chan, qtd,
961 DWC2_HC_XFER_URB_COMPLETE);
963 dwc2_release_channel(hsotg, chan, qtd,
964 DWC2_HC_XFER_NO_HALT_STATUS);
967 return 1; /* Indicates that channel released */
971 * Handles a host channel Transfer Complete interrupt. This handler may be
972 * called in either DMA mode or Slave mode.
974 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
975 struct dwc2_host_chan *chan, int chnum,
976 struct dwc2_qtd *qtd)
978 struct dwc2_hcd_urb *urb = qtd->urb;
979 enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
985 "--Host Channel %d Interrupt: Transfer Complete--\n",
989 goto handle_xfercomp_done;
991 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
993 if (hsotg->core_params->dma_desc_enable > 0) {
994 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
995 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
996 /* Do not disable the interrupt, just clear it */
998 goto handle_xfercomp_done;
1001 /* Handle xfer complete on CSPLIT */
1002 if (chan->qh->do_split) {
1003 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
1004 hsotg->core_params->dma_enable > 0) {
1005 if (qtd->complete_split &&
1006 dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
1008 goto handle_xfercomp_done;
1010 qtd->complete_split = 0;
1014 /* Update the QTD and URB states */
1015 switch (pipe_type) {
1016 case USB_ENDPOINT_XFER_CONTROL:
1017 switch (qtd->control_phase) {
1018 case DWC2_CONTROL_SETUP:
1019 if (urb->length > 0)
1020 qtd->control_phase = DWC2_CONTROL_DATA;
1022 qtd->control_phase = DWC2_CONTROL_STATUS;
1023 dev_vdbg(hsotg->dev,
1024 " Control setup transaction done\n");
1025 halt_status = DWC2_HC_XFER_COMPLETE;
1027 case DWC2_CONTROL_DATA:
1028 urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1030 if (urb_xfer_done) {
1031 qtd->control_phase = DWC2_CONTROL_STATUS;
1032 dev_vdbg(hsotg->dev,
1033 " Control data transfer done\n");
1035 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1038 halt_status = DWC2_HC_XFER_COMPLETE;
1040 case DWC2_CONTROL_STATUS:
1041 dev_vdbg(hsotg->dev, " Control transfer complete\n");
1042 if (urb->status == -EINPROGRESS)
1044 dwc2_host_complete(hsotg, qtd, urb->status);
1045 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1049 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1052 case USB_ENDPOINT_XFER_BULK:
1053 dev_vdbg(hsotg->dev, " Bulk transfer complete\n");
1054 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1056 if (urb_xfer_done) {
1057 dwc2_host_complete(hsotg, qtd, urb->status);
1058 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1060 halt_status = DWC2_HC_XFER_COMPLETE;
1063 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1064 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1067 case USB_ENDPOINT_XFER_INT:
1068 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n");
1069 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1073 * Interrupt URB is done on the first transfer complete
1076 if (urb_xfer_done) {
1077 dwc2_host_complete(hsotg, qtd, urb->status);
1078 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1080 halt_status = DWC2_HC_XFER_COMPLETE;
1083 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1084 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1087 case USB_ENDPOINT_XFER_ISOC:
1089 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n");
1090 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1091 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1092 chnum, qtd, DWC2_HC_XFER_COMPLETE);
1093 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1098 handle_xfercomp_done:
1099 disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1103 * Handles a host channel STALL interrupt. This handler may be called in
1104 * either DMA mode or Slave mode.
1106 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1107 struct dwc2_host_chan *chan, int chnum,
1108 struct dwc2_qtd *qtd)
1110 struct dwc2_hcd_urb *urb = qtd->urb;
1113 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1116 if (hsotg->core_params->dma_desc_enable > 0) {
1117 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1118 DWC2_HC_XFER_STALL);
1119 goto handle_stall_done;
1123 goto handle_stall_halt;
1125 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1127 if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1128 dwc2_host_complete(hsotg, qtd, -EPIPE);
1130 if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1131 pipe_type == USB_ENDPOINT_XFER_INT) {
1132 dwc2_host_complete(hsotg, qtd, -EPIPE);
1134 * USB protocol requires resetting the data toggle for bulk
1135 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1136 * setup command is issued to the endpoint. Anticipate the
1137 * CLEAR_FEATURE command since a STALL has occurred and reset
1138 * the data toggle now.
1140 chan->qh->data_toggle = 0;
1144 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1147 disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1151 * Updates the state of the URB when a transfer has been stopped due to an
1152 * abnormal condition before the transfer completes. Modifies the
1153 * actual_length field of the URB to reflect the number of bytes that have
1154 * actually been transferred via the host channel.
1156 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1157 struct dwc2_host_chan *chan, int chnum,
1158 struct dwc2_hcd_urb *urb,
1159 struct dwc2_qtd *qtd,
1160 enum dwc2_halt_status halt_status)
1162 u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1163 qtd, halt_status, NULL);
1166 if (urb->actual_length + xfer_length > urb->length) {
1167 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1168 xfer_length = urb->length - urb->actual_length;
1171 /* Non DWORD-aligned buffer case handling */
1172 if (chan->align_buf && xfer_length && chan->ep_is_in) {
1173 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
1174 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
1175 chan->qh->dw_align_buf_size,
1177 DMA_FROM_DEVICE : DMA_TO_DEVICE);
1179 memcpy(urb->buf + urb->actual_length,
1180 chan->qh->dw_align_buf,
1184 urb->actual_length += xfer_length;
1186 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1187 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1188 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1189 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
1190 chan->start_pkt_count);
1191 dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n",
1192 (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
1193 dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet);
1194 dev_vdbg(hsotg->dev, " bytes_transferred %d\n",
1196 dev_vdbg(hsotg->dev, " urb->actual_length %d\n",
1197 urb->actual_length);
1198 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n",
1203 * Handles a host channel NAK interrupt. This handler may be called in either
1204 * DMA mode or Slave mode.
1206 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1207 struct dwc2_host_chan *chan, int chnum,
1208 struct dwc2_qtd *qtd)
1211 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1216 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1221 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1225 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1226 * interrupt. Re-start the SSPLIT transfer.
1228 if (chan->do_split) {
1229 if (chan->complete_split)
1230 qtd->error_count = 0;
1231 qtd->complete_split = 0;
1232 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1233 goto handle_nak_done;
1236 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1237 case USB_ENDPOINT_XFER_CONTROL:
1238 case USB_ENDPOINT_XFER_BULK:
1239 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) {
1241 * NAK interrupts are enabled on bulk/control IN
1242 * transfers in DMA mode for the sole purpose of
1243 * resetting the error count after a transaction error
1244 * occurs. The core will continue transferring data.
1246 qtd->error_count = 0;
1251 * NAK interrupts normally occur during OUT transfers in DMA
1252 * or Slave mode. For IN transfers, more requests will be
1253 * queued as request queue space is available.
1255 qtd->error_count = 0;
1257 if (!chan->qh->ping_state) {
1258 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1259 qtd, DWC2_HC_XFER_NAK);
1260 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1262 if (chan->speed == USB_SPEED_HIGH)
1263 chan->qh->ping_state = 1;
1267 * Halt the channel so the transfer can be re-started from
1268 * the appropriate point or the PING protocol will
1271 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1273 case USB_ENDPOINT_XFER_INT:
1274 qtd->error_count = 0;
1275 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1277 case USB_ENDPOINT_XFER_ISOC:
1278 /* Should never get called for isochronous transfers */
1279 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1284 disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1288 * Handles a host channel ACK interrupt. This interrupt is enabled when
1289 * performing the PING protocol in Slave mode, when errors occur during
1290 * either Slave mode or DMA mode, and during Start Split transactions.
1292 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1293 struct dwc2_host_chan *chan, int chnum,
1294 struct dwc2_qtd *qtd)
1296 struct dwc2_hcd_iso_packet_desc *frame_desc;
1299 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1302 if (chan->do_split) {
1303 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1304 if (!chan->ep_is_in &&
1305 chan->data_pid_start != DWC2_HC_PID_SETUP)
1306 qtd->ssplit_out_xfer_count = chan->xfer_len;
1308 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1309 qtd->complete_split = 1;
1310 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1313 switch (chan->xact_pos) {
1314 case DWC2_HCSPLT_XACTPOS_ALL:
1316 case DWC2_HCSPLT_XACTPOS_END:
1317 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1318 qtd->isoc_split_offset = 0;
1320 case DWC2_HCSPLT_XACTPOS_BEGIN:
1321 case DWC2_HCSPLT_XACTPOS_MID:
1323 * For BEGIN or MID, calculate the length for
1324 * the next microframe to determine the correct
1325 * SSPLIT token, either MID or END
1327 frame_desc = &qtd->urb->iso_descs[
1328 qtd->isoc_frame_index];
1329 qtd->isoc_split_offset += 188;
1331 if (frame_desc->length - qtd->isoc_split_offset
1333 qtd->isoc_split_pos =
1334 DWC2_HCSPLT_XACTPOS_END;
1336 qtd->isoc_split_pos =
1337 DWC2_HCSPLT_XACTPOS_MID;
1342 qtd->error_count = 0;
1344 if (chan->qh->ping_state) {
1345 chan->qh->ping_state = 0;
1347 * Halt the channel so the transfer can be re-started
1348 * from the appropriate point. This only happens in
1349 * Slave mode. In DMA mode, the ping_state is cleared
1350 * when the transfer is started because the core
1351 * automatically executes the PING, then the transfer.
1353 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1358 * If the ACK occurred when _not_ in the PING state, let the channel
1359 * continue transferring data after clearing the error count
1361 disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1365 * Handles a host channel NYET interrupt. This interrupt should only occur on
1366 * Bulk and Control OUT endpoints and for complete split transactions. If a
1367 * NYET occurs at the same time as a Transfer Complete interrupt, it is
1368 * handled in the xfercomp interrupt handler, not here. This handler may be
1369 * called in either DMA mode or Slave mode.
1371 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1372 struct dwc2_host_chan *chan, int chnum,
1373 struct dwc2_qtd *qtd)
1376 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1381 * re-do the CSPLIT immediately on non-periodic
1383 if (chan->do_split && chan->complete_split) {
1384 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1385 hsotg->core_params->dma_enable > 0) {
1386 qtd->complete_split = 0;
1387 qtd->isoc_split_offset = 0;
1388 qtd->isoc_frame_index++;
1390 qtd->isoc_frame_index == qtd->urb->packet_count) {
1391 dwc2_host_complete(hsotg, qtd, 0);
1392 dwc2_release_channel(hsotg, chan, qtd,
1393 DWC2_HC_XFER_URB_COMPLETE);
1395 dwc2_release_channel(hsotg, chan, qtd,
1396 DWC2_HC_XFER_NO_HALT_STATUS);
1398 goto handle_nyet_done;
1401 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1402 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1403 int frnum = dwc2_hcd_get_frame_number(hsotg);
1405 if (dwc2_full_frame_num(frnum) !=
1406 dwc2_full_frame_num(chan->qh->sched_frame)) {
1408 * No longer in the same full speed frame.
1409 * Treat this as a transaction error.
1413 * Todo: Fix system performance so this can
1414 * be treated as an error. Right now complete
1415 * splits cannot be scheduled precisely enough
1416 * due to other system activity, so this error
1417 * occurs regularly in Slave mode.
1421 qtd->complete_split = 0;
1422 dwc2_halt_channel(hsotg, chan, qtd,
1423 DWC2_HC_XFER_XACT_ERR);
1424 /* Todo: add support for isoc release */
1425 goto handle_nyet_done;
1429 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1430 goto handle_nyet_done;
1433 chan->qh->ping_state = 1;
1434 qtd->error_count = 0;
1436 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1438 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1441 * Halt the channel and re-start the transfer so the PING protocol
1444 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1447 disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1451 * Handles a host channel babble interrupt. This handler may be called in
1452 * either DMA mode or Slave mode.
1454 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1455 struct dwc2_host_chan *chan, int chnum,
1456 struct dwc2_qtd *qtd)
1458 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1461 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1463 if (hsotg->core_params->dma_desc_enable > 0) {
1464 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1465 DWC2_HC_XFER_BABBLE_ERR);
1469 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1470 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1471 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1473 enum dwc2_halt_status halt_status;
1475 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1476 qtd, DWC2_HC_XFER_BABBLE_ERR);
1477 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1481 disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1485 * Handles a host channel AHB error interrupt. This handler is only called in
1488 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1489 struct dwc2_host_chan *chan, int chnum,
1490 struct dwc2_qtd *qtd)
1492 struct dwc2_hcd_urb *urb = qtd->urb;
1493 char *pipetype, *speed;
1499 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1503 goto handle_ahberr_halt;
1505 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1507 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1508 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1509 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1510 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum));
1512 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1513 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1514 dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1515 dev_err(hsotg->dev, " Device address: %d\n",
1516 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1517 dev_err(hsotg->dev, " Endpoint: %d, %s\n",
1518 dwc2_hcd_get_ep_num(&urb->pipe_info),
1519 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1521 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1522 case USB_ENDPOINT_XFER_CONTROL:
1523 pipetype = "CONTROL";
1525 case USB_ENDPOINT_XFER_BULK:
1528 case USB_ENDPOINT_XFER_INT:
1529 pipetype = "INTERRUPT";
1531 case USB_ENDPOINT_XFER_ISOC:
1532 pipetype = "ISOCHRONOUS";
1535 pipetype = "UNKNOWN";
1539 dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype);
1541 switch (chan->speed) {
1542 case USB_SPEED_HIGH:
1545 case USB_SPEED_FULL:
1556 dev_err(hsotg->dev, " Speed: %s\n", speed);
1558 dev_err(hsotg->dev, " Max packet size: %d\n",
1559 dwc2_hcd_get_mps(&urb->pipe_info));
1560 dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length);
1561 dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
1562 urb->buf, (unsigned long)urb->dma);
1563 dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
1564 urb->setup_packet, (unsigned long)urb->setup_dma);
1565 dev_err(hsotg->dev, " Interval: %d\n", urb->interval);
1567 /* Core halts the channel for Descriptor DMA mode */
1568 if (hsotg->core_params->dma_desc_enable > 0) {
1569 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1570 DWC2_HC_XFER_AHB_ERR);
1571 goto handle_ahberr_done;
1574 dwc2_host_complete(hsotg, qtd, -EIO);
1578 * Force a channel halt. Don't call dwc2_halt_channel because that won't
1579 * write to the HCCHARn register in DMA mode to force the halt.
1581 dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1584 disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1588 * Handles a host channel transaction error interrupt. This handler may be
1589 * called in either DMA mode or Slave mode.
1591 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1592 struct dwc2_host_chan *chan, int chnum,
1593 struct dwc2_qtd *qtd)
1596 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1598 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1600 if (hsotg->core_params->dma_desc_enable > 0) {
1601 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1602 DWC2_HC_XFER_XACT_ERR);
1603 goto handle_xacterr_done;
1606 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1607 case USB_ENDPOINT_XFER_CONTROL:
1608 case USB_ENDPOINT_XFER_BULK:
1610 if (!chan->qh->ping_state) {
1612 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1613 qtd, DWC2_HC_XFER_XACT_ERR);
1614 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1615 if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1616 chan->qh->ping_state = 1;
1620 * Halt the channel so the transfer can be re-started from
1621 * the appropriate point or the PING protocol will start
1623 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1625 case USB_ENDPOINT_XFER_INT:
1627 if (chan->do_split && chan->complete_split)
1628 qtd->complete_split = 0;
1629 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1631 case USB_ENDPOINT_XFER_ISOC:
1633 enum dwc2_halt_status halt_status;
1635 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1636 chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1637 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1642 handle_xacterr_done:
1643 disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1647 * Handles a host channel frame overrun interrupt. This handler may be called
1648 * in either DMA mode or Slave mode.
1650 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1651 struct dwc2_host_chan *chan, int chnum,
1652 struct dwc2_qtd *qtd)
1654 enum dwc2_halt_status halt_status;
1657 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1660 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1662 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1663 case USB_ENDPOINT_XFER_CONTROL:
1664 case USB_ENDPOINT_XFER_BULK:
1666 case USB_ENDPOINT_XFER_INT:
1667 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1669 case USB_ENDPOINT_XFER_ISOC:
1670 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1671 qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1672 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1676 disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1680 * Handles a host channel data toggle error interrupt. This handler may be
1681 * called in either DMA mode or Slave mode.
1683 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1684 struct dwc2_host_chan *chan, int chnum,
1685 struct dwc2_qtd *qtd)
1688 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1691 qtd->error_count = 0;
1694 "Data Toggle Error on OUT transfer, channel %d\n",
1697 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1698 disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1702 * For debug only. It checks that a valid halt status is set and that
1703 * HCCHARn.chdis is clear. If there's a problem, corrective action is
1704 * taken and a warning is issued.
1706 * Return: true if halt status is ok, false otherwise
1708 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1709 struct dwc2_host_chan *chan, int chnum,
1710 struct dwc2_qtd *qtd)
1718 if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1720 * This code is here only as a check. This condition should
1721 * never happen. Ignore the halt if it does occur.
1723 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1724 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1725 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1726 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1728 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1731 "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1732 chnum, hcchar, hctsiz);
1734 "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1735 chan->hcint, hcintmsk, hcsplt);
1737 dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1738 qtd->complete_split);
1739 dev_warn(hsotg->dev,
1740 "%s: no halt status, channel %d, ignoring interrupt\n",
1746 * This code is here only as a check. hcchar.chdis should never be set
1747 * when the halt interrupt occurs. Halt the channel again if it does
1750 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1751 if (hcchar & HCCHAR_CHDIS) {
1752 dev_warn(hsotg->dev,
1753 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1755 chan->halt_pending = 0;
1756 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1765 * Handles a host Channel Halted interrupt in DMA mode. This handler
1766 * determines the reason the channel halted and proceeds accordingly.
1768 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1769 struct dwc2_host_chan *chan, int chnum,
1770 struct dwc2_qtd *qtd)
1773 int out_nak_enh = 0;
1776 dev_vdbg(hsotg->dev,
1777 "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1781 * For core with OUT NAK enhancement, the flow for high-speed
1782 * CONTROL/BULK OUT is handled a little differently
1784 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1785 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1786 (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1787 chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1792 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1793 (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1794 hsotg->core_params->dma_desc_enable <= 0)) {
1795 if (hsotg->core_params->dma_desc_enable > 0)
1796 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1800 * Just release the channel. A dequeue can happen on a
1801 * transfer timeout. In the case of an AHB Error, the
1802 * channel was forced to halt because there's no way to
1803 * gracefully recover.
1805 dwc2_release_channel(hsotg, chan, qtd,
1810 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1812 if (chan->hcint & HCINTMSK_XFERCOMPL) {
1814 * Todo: This is here because of a possible hardware bug. Spec
1815 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1816 * interrupt w/ACK bit set should occur, but I only see the
1817 * XFERCOMP bit, even with it masked out. This is a workaround
1818 * for that behavior. Should fix this when hardware is fixed.
1820 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1821 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1822 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1823 } else if (chan->hcint & HCINTMSK_STALL) {
1824 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1825 } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1826 hsotg->core_params->dma_desc_enable <= 0) {
1829 (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1830 dev_vdbg(hsotg->dev,
1831 "XactErr with NYET/NAK/ACK\n");
1832 qtd->error_count = 0;
1834 dev_vdbg(hsotg->dev,
1835 "XactErr without NYET/NAK/ACK\n");
1840 * Must handle xacterr before nak or ack. Could get a xacterr
1841 * at the same time as either of these on a BULK/CONTROL OUT
1842 * that started with a PING. The xacterr takes precedence.
1844 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1845 } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1846 hsotg->core_params->dma_desc_enable > 0) {
1847 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1848 } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1849 hsotg->core_params->dma_desc_enable > 0) {
1850 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1851 } else if (chan->hcint & HCINTMSK_BBLERR) {
1852 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1853 } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1854 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1855 } else if (!out_nak_enh) {
1856 if (chan->hcint & HCINTMSK_NYET) {
1858 * Must handle nyet before nak or ack. Could get a nyet
1859 * at the same time as either of those on a BULK/CONTROL
1860 * OUT that started with a PING. The nyet takes
1863 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1864 } else if ((chan->hcint & HCINTMSK_NAK) &&
1865 !(hcintmsk & HCINTMSK_NAK)) {
1867 * If nak is not masked, it's because a non-split IN
1868 * transfer is in an error state. In that case, the nak
1869 * is handled by the nak interrupt handler, not here.
1870 * Handle nak here for BULK/CONTROL OUT transfers, which
1871 * halt on a NAK to allow rewinding the buffer pointer.
1873 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1874 } else if ((chan->hcint & HCINTMSK_ACK) &&
1875 !(hcintmsk & HCINTMSK_ACK)) {
1877 * If ack is not masked, it's because a non-split IN
1878 * transfer is in an error state. In that case, the ack
1879 * is handled by the ack interrupt handler, not here.
1880 * Handle ack here for split transfers. Start splits
1883 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1885 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1886 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1888 * A periodic transfer halted with no other
1889 * channel interrupts set. Assume it was halted
1890 * by the core because it could not be completed
1891 * in its scheduled (micro)frame.
1894 "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1896 dwc2_halt_channel(hsotg, chan, qtd,
1897 DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1900 "%s: Channel %d - ChHltd set, but reason is unknown\n",
1903 "hcint 0x%08x, intsts 0x%08x\n",
1905 dwc2_readl(hsotg->regs + GINTSTS));
1910 dev_info(hsotg->dev,
1911 "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1914 /* Failthrough: use 3-strikes rule */
1916 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1917 qtd, DWC2_HC_XFER_XACT_ERR);
1919 * We can get here after a completed transaction
1920 * (urb->actual_length >= urb->length) which was not reported
1921 * as completed. If that is the case, and we do not abort
1922 * the transfer, a transfer of size 0 will be enqueued
1923 * subsequently. If urb->actual_length is not DMA-aligned,
1924 * the buffer will then point to an unaligned address, and
1925 * the resulting behavior is undefined. Bail out in that
1928 if (qtd->urb->actual_length >= qtd->urb->length)
1929 qtd->error_count = 3;
1930 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1931 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1936 * Handles a host channel Channel Halted interrupt
1938 * In slave mode, this handler is called only when the driver specifically
1939 * requests a halt. This occurs during handling other host channel interrupts
1940 * (e.g. nak, xacterr, stall, nyet, etc.).
1942 * In DMA mode, this is the interrupt that occurs when the core has finished
1943 * processing a transfer on a channel. Other host channel interrupts (except
1944 * ahberr) are disabled in DMA mode.
1946 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1947 struct dwc2_host_chan *chan, int chnum,
1948 struct dwc2_qtd *qtd)
1951 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1954 if (hsotg->core_params->dma_enable > 0) {
1955 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1957 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1959 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1964 * Check if the given qtd is still the top of the list (and thus valid).
1966 * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed
1967 * the qtd from the top of the list, this will return false (otherwise true).
1969 static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
1971 struct dwc2_qtd *cur_head;
1976 cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
1978 return (cur_head == qtd);
1981 /* Handles interrupt for a specific Host Channel */
1982 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1984 struct dwc2_qtd *qtd;
1985 struct dwc2_host_chan *chan;
1986 u32 hcint, hcintmsk;
1988 chan = hsotg->hc_ptr_array[chnum];
1990 hcint = dwc2_readl(hsotg->regs + HCINT(chnum));
1991 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1993 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
1994 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
1999 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
2001 dev_vdbg(hsotg->dev,
2002 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2003 hcint, hcintmsk, hcint & hcintmsk);
2006 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
2007 chan->hcint = hcint;
2011 * If the channel was halted due to a dequeue, the qtd list might
2012 * be empty or at least the first entry will not be the active qtd.
2013 * In this case, take a shortcut and just release the channel.
2015 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
2017 * If the channel was halted, this should be the only
2018 * interrupt unmasked
2020 WARN_ON(hcint != HCINTMSK_CHHLTD);
2021 if (hsotg->core_params->dma_desc_enable > 0)
2022 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2025 dwc2_release_channel(hsotg, chan, NULL,
2030 if (list_empty(&chan->qh->qtd_list)) {
2032 * TODO: Will this ever happen with the
2033 * DWC2_HC_XFER_URB_DEQUEUE handling above?
2035 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2038 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2039 chan->hcint, hcintmsk, hcint);
2040 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2041 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2046 qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
2049 if (hsotg->core_params->dma_enable <= 0) {
2050 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
2051 hcint &= ~HCINTMSK_CHHLTD;
2054 if (hcint & HCINTMSK_XFERCOMPL) {
2055 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2057 * If NYET occurred at same time as Xfer Complete, the NYET is
2058 * handled by the Xfer Complete interrupt handler. Don't want
2059 * to call the NYET interrupt handler in this case.
2061 hcint &= ~HCINTMSK_NYET;
2064 if (hcint & HCINTMSK_CHHLTD) {
2065 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2066 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2069 if (hcint & HCINTMSK_AHBERR) {
2070 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2071 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2074 if (hcint & HCINTMSK_STALL) {
2075 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2076 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2079 if (hcint & HCINTMSK_NAK) {
2080 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2081 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2084 if (hcint & HCINTMSK_ACK) {
2085 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2086 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2089 if (hcint & HCINTMSK_NYET) {
2090 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2091 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2094 if (hcint & HCINTMSK_XACTERR) {
2095 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2096 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2099 if (hcint & HCINTMSK_BBLERR) {
2100 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2101 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2104 if (hcint & HCINTMSK_FRMOVRUN) {
2105 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2106 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2109 if (hcint & HCINTMSK_DATATGLERR) {
2110 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2111 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2120 * This interrupt indicates that one or more host channels has a pending
2121 * interrupt. There are multiple conditions that can cause each host channel
2122 * interrupt. This function determines which conditions have occurred for each
2123 * host channel interrupt and handles them appropriately.
2125 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2130 haint = dwc2_readl(hsotg->regs + HAINT);
2132 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2134 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2137 for (i = 0; i < hsotg->core_params->host_channels; i++) {
2138 if (haint & (1 << i))
2139 dwc2_hc_n_intr(hsotg, i);
2143 /* This function handles interrupts for the HCD */
2144 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2146 u32 gintsts, dbg_gintsts;
2147 irqreturn_t retval = IRQ_NONE;
2149 if (!dwc2_is_controller_alive(hsotg)) {
2150 dev_warn(hsotg->dev, "Controller is dead\n");
2154 spin_lock(&hsotg->lock);
2156 /* Check if HOST Mode */
2157 if (dwc2_is_host_mode(hsotg)) {
2158 gintsts = dwc2_read_core_intr(hsotg);
2160 spin_unlock(&hsotg->lock);
2164 retval = IRQ_HANDLED;
2166 dbg_gintsts = gintsts;
2168 dbg_gintsts &= ~GINTSTS_SOF;
2171 dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2174 /* Only print if there are any non-suppressed interrupts left */
2176 dev_vdbg(hsotg->dev,
2177 "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2180 if (gintsts & GINTSTS_SOF)
2181 dwc2_sof_intr(hsotg);
2182 if (gintsts & GINTSTS_RXFLVL)
2183 dwc2_rx_fifo_level_intr(hsotg);
2184 if (gintsts & GINTSTS_NPTXFEMP)
2185 dwc2_np_tx_fifo_empty_intr(hsotg);
2186 if (gintsts & GINTSTS_PRTINT)
2187 dwc2_port_intr(hsotg);
2188 if (gintsts & GINTSTS_HCHINT)
2189 dwc2_hc_intr(hsotg);
2190 if (gintsts & GINTSTS_PTXFEMP)
2191 dwc2_perio_tx_fifo_empty_intr(hsotg);
2194 dev_vdbg(hsotg->dev,
2195 "DWC OTG HCD Finished Servicing Interrupts\n");
2196 dev_vdbg(hsotg->dev,
2197 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2198 dwc2_readl(hsotg->regs + GINTSTS),
2199 dwc2_readl(hsotg->regs + GINTMSK));
2203 spin_unlock(&hsotg->lock);