2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * DMA support added by Chip Coldwell.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/tty.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/serial.h>
30 #include <linux/clk.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/tty_flip.h>
34 #include <linux/platform_device.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
40 #include <linux/atmel_pdc.h>
41 #include <linux/atmel_serial.h>
42 #include <linux/uaccess.h>
43 #include <linux/platform_data/atmel.h>
44 #include <linux/timer.h>
45 #include <linux/gpio.h>
46 #include <linux/gpio/consumer.h>
47 #include <linux/err.h>
48 #include <linux/irq.h>
49 #include <linux/suspend.h>
52 #include <asm/ioctls.h>
54 #define PDC_BUFFER_SIZE 512
55 /* Revisit: We should calculate this based on the actual port settings */
56 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
58 /* The minium number of data FIFOs should be able to contain */
59 #define ATMEL_MIN_FIFO_SIZE 8
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
64 #define ATMEL_RTS_HIGH_OFFSET 16
65 #define ATMEL_RTS_LOW_OFFSET 20
67 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
71 #include <linux/serial_core.h>
73 #include "serial_mctrl_gpio.h"
75 static void atmel_start_rx(struct uart_port *port);
76 static void atmel_stop_rx(struct uart_port *port);
78 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
80 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
81 * should coexist with the 8250 driver, such as if we have an external 16C550
83 #define SERIAL_ATMEL_MAJOR 204
84 #define MINOR_START 154
85 #define ATMEL_DEVICENAME "ttyAT"
89 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
90 * name, but it is legally reserved for the 8250 driver. */
91 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
92 #define MINOR_START 64
93 #define ATMEL_DEVICENAME "ttyS"
97 #define ATMEL_ISR_PASS_LIMIT 256
99 struct atmel_dma_buffer {
102 unsigned int dma_size;
106 struct atmel_uart_char {
112 * Be careful, the real size of the ring buffer is
113 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
114 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
117 #define ATMEL_SERIAL_RINGSIZE 1024
120 * at91: 6 USARTs and one DBGU port (SAM9260)
123 #define ATMEL_MAX_UART 7
126 * We wrap our port structure around the generic uart_port.
128 struct atmel_uart_port {
129 struct uart_port uart; /* uart */
130 struct clk *clk; /* uart clock */
131 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
132 u32 backup_imr; /* IMR saved during suspend */
133 int break_active; /* break being received */
135 bool use_dma_rx; /* enable DMA receiver */
136 bool use_pdc_rx; /* enable PDC receiver */
137 short pdc_rx_idx; /* current PDC RX buffer */
138 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
140 bool use_dma_tx; /* enable DMA transmitter */
141 bool use_pdc_tx; /* enable PDC transmitter */
142 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
144 spinlock_t lock_tx; /* port lock */
145 spinlock_t lock_rx; /* port lock */
146 struct dma_chan *chan_tx;
147 struct dma_chan *chan_rx;
148 struct dma_async_tx_descriptor *desc_tx;
149 struct dma_async_tx_descriptor *desc_rx;
150 dma_cookie_t cookie_tx;
151 dma_cookie_t cookie_rx;
152 struct scatterlist sg_tx;
153 struct scatterlist sg_rx;
154 struct tasklet_struct tasklet_rx;
155 struct tasklet_struct tasklet_tx;
156 atomic_t tasklet_shutdown;
157 unsigned int irq_status_prev;
160 struct circ_buf rx_ring;
162 struct mctrl_gpios *gpios;
163 unsigned int tx_done_mask;
168 u32 rtor; /* address of receiver timeout register if it exists */
169 bool has_frac_baudrate;
171 struct timer_list uart_timer;
174 unsigned int pending;
175 unsigned int pending_status;
176 spinlock_t lock_suspended;
178 bool hd_start_rx; /* can start RX during half-duplex operation */
180 int (*prepare_rx)(struct uart_port *port);
181 int (*prepare_tx)(struct uart_port *port);
182 void (*schedule_rx)(struct uart_port *port);
183 void (*schedule_tx)(struct uart_port *port);
184 void (*release_rx)(struct uart_port *port);
185 void (*release_tx)(struct uart_port *port);
188 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
189 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
192 static struct console atmel_console;
195 #if defined(CONFIG_OF)
196 static const struct of_device_id atmel_serial_dt_ids[] = {
197 { .compatible = "atmel,at91rm9200-usart" },
198 { .compatible = "atmel,at91sam9260-usart" },
203 static inline struct atmel_uart_port *
204 to_atmel_uart_port(struct uart_port *uart)
206 return container_of(uart, struct atmel_uart_port, uart);
209 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
211 return __raw_readl(port->membase + reg);
214 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
216 __raw_writel(value, port->membase + reg);
221 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
222 static inline u8 atmel_uart_read_char(struct uart_port *port)
224 return __raw_readl(port->membase + ATMEL_US_RHR);
227 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
229 __raw_writel(value, port->membase + ATMEL_US_THR);
234 static inline u8 atmel_uart_read_char(struct uart_port *port)
236 return __raw_readb(port->membase + ATMEL_US_RHR);
239 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
241 __raw_writeb(value, port->membase + ATMEL_US_THR);
246 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
248 return (port->rs485.flags & SER_RS485_ENABLED) &&
249 !(port->rs485.flags & SER_RS485_RX_DURING_TX);
252 #ifdef CONFIG_SERIAL_ATMEL_PDC
253 static bool atmel_use_pdc_rx(struct uart_port *port)
255 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
257 return atmel_port->use_pdc_rx;
260 static bool atmel_use_pdc_tx(struct uart_port *port)
262 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
264 return atmel_port->use_pdc_tx;
267 static bool atmel_use_pdc_rx(struct uart_port *port)
272 static bool atmel_use_pdc_tx(struct uart_port *port)
278 static bool atmel_use_dma_tx(struct uart_port *port)
280 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
282 return atmel_port->use_dma_tx;
285 static bool atmel_use_dma_rx(struct uart_port *port)
287 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
289 return atmel_port->use_dma_rx;
292 static bool atmel_use_fifo(struct uart_port *port)
294 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
296 return atmel_port->fifo_size;
299 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
300 struct tasklet_struct *t)
302 if (!atomic_read(&atmel_port->tasklet_shutdown))
306 static unsigned int atmel_get_lines_status(struct uart_port *port)
308 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
309 unsigned int status, ret = 0;
311 status = atmel_uart_readl(port, ATMEL_US_CSR);
313 mctrl_gpio_get(atmel_port->gpios, &ret);
315 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
318 status &= ~ATMEL_US_CTS;
320 status |= ATMEL_US_CTS;
323 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
326 status &= ~ATMEL_US_DSR;
328 status |= ATMEL_US_DSR;
331 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
334 status &= ~ATMEL_US_RI;
336 status |= ATMEL_US_RI;
339 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
342 status &= ~ATMEL_US_DCD;
344 status |= ATMEL_US_DCD;
350 /* Enable or disable the rs485 support */
351 static int atmel_config_rs485(struct uart_port *port,
352 struct serial_rs485 *rs485conf)
354 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
357 /* Disable interrupts */
358 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
360 mode = atmel_uart_readl(port, ATMEL_US_MR);
362 /* Resetting serial mode to RS232 (0x0) */
363 mode &= ~ATMEL_US_USMODE;
365 port->rs485 = *rs485conf;
367 if (rs485conf->flags & SER_RS485_ENABLED) {
368 dev_dbg(port->dev, "Setting UART to RS485\n");
369 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
370 atmel_uart_writel(port, ATMEL_US_TTGR,
371 rs485conf->delay_rts_after_send);
372 mode |= ATMEL_US_USMODE_RS485;
374 dev_dbg(port->dev, "Setting UART to RS232\n");
375 if (atmel_use_pdc_tx(port))
376 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
379 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
381 atmel_uart_writel(port, ATMEL_US_MR, mode);
383 /* Enable interrupts */
384 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
390 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
392 static u_int atmel_tx_empty(struct uart_port *port)
394 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
400 * Set state of the modem control output lines
402 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
404 unsigned int control = 0;
405 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
406 unsigned int rts_paused, rts_ready;
407 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
409 /* override mode to RS485 if needed, otherwise keep the current mode */
410 if (port->rs485.flags & SER_RS485_ENABLED) {
411 atmel_uart_writel(port, ATMEL_US_TTGR,
412 port->rs485.delay_rts_after_send);
413 mode &= ~ATMEL_US_USMODE;
414 mode |= ATMEL_US_USMODE_RS485;
417 /* set the RTS line state according to the mode */
418 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
419 /* force RTS line to high level */
420 rts_paused = ATMEL_US_RTSEN;
422 /* give the control of the RTS line back to the hardware */
423 rts_ready = ATMEL_US_RTSDIS;
425 /* force RTS line to high level */
426 rts_paused = ATMEL_US_RTSDIS;
428 /* force RTS line to low level */
429 rts_ready = ATMEL_US_RTSEN;
432 if (mctrl & TIOCM_RTS)
433 control |= rts_ready;
435 control |= rts_paused;
437 if (mctrl & TIOCM_DTR)
438 control |= ATMEL_US_DTREN;
440 control |= ATMEL_US_DTRDIS;
442 atmel_uart_writel(port, ATMEL_US_CR, control);
444 mctrl_gpio_set(atmel_port->gpios, mctrl);
446 /* Local loopback mode? */
447 mode &= ~ATMEL_US_CHMODE;
448 if (mctrl & TIOCM_LOOP)
449 mode |= ATMEL_US_CHMODE_LOC_LOOP;
451 mode |= ATMEL_US_CHMODE_NORMAL;
453 atmel_uart_writel(port, ATMEL_US_MR, mode);
457 * Get state of the modem control input lines
459 static u_int atmel_get_mctrl(struct uart_port *port)
461 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
462 unsigned int ret = 0, status;
464 status = atmel_uart_readl(port, ATMEL_US_CSR);
467 * The control signals are active low.
469 if (!(status & ATMEL_US_DCD))
471 if (!(status & ATMEL_US_CTS))
473 if (!(status & ATMEL_US_DSR))
475 if (!(status & ATMEL_US_RI))
478 return mctrl_gpio_get(atmel_port->gpios, &ret);
484 static void atmel_stop_tx(struct uart_port *port)
486 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
488 if (atmel_use_pdc_tx(port)) {
489 /* disable PDC transmit */
490 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
494 * Disable the transmitter.
495 * This is mandatory when DMA is used, otherwise the DMA buffer
496 * is fully transmitted.
498 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
500 /* Disable interrupts */
501 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
503 if (atmel_uart_is_half_duplex(port))
504 if (!atomic_read(&atmel_port->tasklet_shutdown))
505 atmel_start_rx(port);
510 * Start transmitting.
512 static void atmel_start_tx(struct uart_port *port)
514 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
516 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
518 /* The transmitter is already running. Yes, we
522 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
523 if (atmel_uart_is_half_duplex(port))
526 if (atmel_use_pdc_tx(port))
527 /* re-enable PDC transmit */
528 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
530 /* Enable interrupts */
531 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
533 /* re-enable the transmitter */
534 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
538 * start receiving - port is in process of being opened.
540 static void atmel_start_rx(struct uart_port *port)
542 /* reset status and receiver */
543 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
545 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
547 if (atmel_use_pdc_rx(port)) {
548 /* enable PDC controller */
549 atmel_uart_writel(port, ATMEL_US_IER,
550 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
551 port->read_status_mask);
552 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
554 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
559 * Stop receiving - port is in process of being closed.
561 static void atmel_stop_rx(struct uart_port *port)
563 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
565 if (atmel_use_pdc_rx(port)) {
566 /* disable PDC receive */
567 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
568 atmel_uart_writel(port, ATMEL_US_IDR,
569 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
570 port->read_status_mask);
572 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
577 * Enable modem status interrupts
579 static void atmel_enable_ms(struct uart_port *port)
581 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
585 * Interrupt should not be enabled twice
587 if (atmel_port->ms_irq_enabled)
590 atmel_port->ms_irq_enabled = true;
592 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
593 ier |= ATMEL_US_CTSIC;
595 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
596 ier |= ATMEL_US_DSRIC;
598 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
599 ier |= ATMEL_US_RIIC;
601 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
602 ier |= ATMEL_US_DCDIC;
604 atmel_uart_writel(port, ATMEL_US_IER, ier);
606 mctrl_gpio_enable_ms(atmel_port->gpios);
610 * Disable modem status interrupts
612 static void atmel_disable_ms(struct uart_port *port)
614 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
618 * Interrupt should not be disabled twice
620 if (!atmel_port->ms_irq_enabled)
623 atmel_port->ms_irq_enabled = false;
625 mctrl_gpio_disable_ms(atmel_port->gpios);
627 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
628 idr |= ATMEL_US_CTSIC;
630 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
631 idr |= ATMEL_US_DSRIC;
633 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
634 idr |= ATMEL_US_RIIC;
636 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
637 idr |= ATMEL_US_DCDIC;
639 atmel_uart_writel(port, ATMEL_US_IDR, idr);
643 * Control the transmission of a break signal
645 static void atmel_break_ctl(struct uart_port *port, int break_state)
647 if (break_state != 0)
649 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
652 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
656 * Stores the incoming character in the ring buffer
659 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
662 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
663 struct circ_buf *ring = &atmel_port->rx_ring;
664 struct atmel_uart_char *c;
666 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
667 /* Buffer overflow, ignore char */
670 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
674 /* Make sure the character is stored before we update head. */
677 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
681 * Deal with parity, framing and overrun errors.
683 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
686 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
688 if (status & ATMEL_US_RXBRK) {
689 /* ignore side-effect */
690 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
693 if (status & ATMEL_US_PARE)
694 port->icount.parity++;
695 if (status & ATMEL_US_FRAME)
696 port->icount.frame++;
697 if (status & ATMEL_US_OVRE)
698 port->icount.overrun++;
702 * Characters received (called from interrupt handler)
704 static void atmel_rx_chars(struct uart_port *port)
706 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
707 unsigned int status, ch;
709 status = atmel_uart_readl(port, ATMEL_US_CSR);
710 while (status & ATMEL_US_RXRDY) {
711 ch = atmel_uart_read_char(port);
714 * note that the error handling code is
715 * out of the main execution path
717 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
718 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
719 || atmel_port->break_active)) {
722 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
724 if (status & ATMEL_US_RXBRK
725 && !atmel_port->break_active) {
726 atmel_port->break_active = 1;
727 atmel_uart_writel(port, ATMEL_US_IER,
731 * This is either the end-of-break
732 * condition or we've received at
733 * least one character without RXBRK
734 * being set. In both cases, the next
735 * RXBRK will indicate start-of-break.
737 atmel_uart_writel(port, ATMEL_US_IDR,
739 status &= ~ATMEL_US_RXBRK;
740 atmel_port->break_active = 0;
744 atmel_buffer_rx_char(port, status, ch);
745 status = atmel_uart_readl(port, ATMEL_US_CSR);
748 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
752 * Transmit characters (called from tasklet with TXRDY interrupt
755 static void atmel_tx_chars(struct uart_port *port)
757 struct circ_buf *xmit = &port->state->xmit;
758 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
761 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
762 atmel_uart_write_char(port, port->x_char);
766 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
769 while (atmel_uart_readl(port, ATMEL_US_CSR) &
770 atmel_port->tx_done_mask) {
771 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
772 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
774 if (uart_circ_empty(xmit))
778 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
779 uart_write_wakeup(port);
781 if (!uart_circ_empty(xmit))
782 /* Enable interrupts */
783 atmel_uart_writel(port, ATMEL_US_IER,
784 atmel_port->tx_done_mask);
787 static void atmel_complete_tx_dma(void *arg)
789 struct atmel_uart_port *atmel_port = arg;
790 struct uart_port *port = &atmel_port->uart;
791 struct circ_buf *xmit = &port->state->xmit;
792 struct dma_chan *chan = atmel_port->chan_tx;
795 spin_lock_irqsave(&port->lock, flags);
798 dmaengine_terminate_all(chan);
799 xmit->tail += atmel_port->tx_len;
800 xmit->tail &= UART_XMIT_SIZE - 1;
802 port->icount.tx += atmel_port->tx_len;
804 spin_lock_irq(&atmel_port->lock_tx);
805 async_tx_ack(atmel_port->desc_tx);
806 atmel_port->cookie_tx = -EINVAL;
807 atmel_port->desc_tx = NULL;
808 spin_unlock_irq(&atmel_port->lock_tx);
810 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
811 uart_write_wakeup(port);
814 * xmit is a circular buffer so, if we have just send data from
815 * xmit->tail to the end of xmit->buf, now we have to transmit the
816 * remaining data from the beginning of xmit->buf to xmit->head.
818 if (!uart_circ_empty(xmit))
819 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
820 else if (atmel_uart_is_half_duplex(port)) {
822 * DMA done, re-enable TXEMPTY and signal that we can stop
823 * TX and start RX for RS485
825 atmel_port->hd_start_rx = true;
826 atmel_uart_writel(port, ATMEL_US_IER,
827 atmel_port->tx_done_mask);
830 spin_unlock_irqrestore(&port->lock, flags);
833 static void atmel_release_tx_dma(struct uart_port *port)
835 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
836 struct dma_chan *chan = atmel_port->chan_tx;
839 dmaengine_terminate_all(chan);
840 dma_release_channel(chan);
841 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
845 atmel_port->desc_tx = NULL;
846 atmel_port->chan_tx = NULL;
847 atmel_port->cookie_tx = -EINVAL;
851 * Called from tasklet with TXRDY interrupt is disabled.
853 static void atmel_tx_dma(struct uart_port *port)
855 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
856 struct circ_buf *xmit = &port->state->xmit;
857 struct dma_chan *chan = atmel_port->chan_tx;
858 struct dma_async_tx_descriptor *desc;
859 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
860 unsigned int tx_len, part1_len, part2_len, sg_len;
861 dma_addr_t phys_addr;
863 /* Make sure we have an idle channel */
864 if (atmel_port->desc_tx != NULL)
867 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
870 * Port xmit buffer is already mapped,
871 * and it is one page... Just adjust
872 * offsets and lengths. Since it is a circular buffer,
873 * we have to transmit till the end, and then the rest.
874 * Take the port lock to get a
875 * consistent xmit buffer state.
877 tx_len = CIRC_CNT_TO_END(xmit->head,
881 if (atmel_port->fifo_size) {
882 /* multi data mode */
883 part1_len = (tx_len & ~0x3); /* DWORD access */
884 part2_len = (tx_len & 0x3); /* BYTE access */
886 /* single data (legacy) mode */
888 part2_len = tx_len; /* BYTE access only */
891 sg_init_table(sgl, 2);
893 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
896 sg_dma_address(sg) = phys_addr;
897 sg_dma_len(sg) = part1_len;
899 phys_addr += part1_len;
904 sg_dma_address(sg) = phys_addr;
905 sg_dma_len(sg) = part2_len;
909 * save tx_len so atmel_complete_tx_dma() will increase
910 * xmit->tail correctly
912 atmel_port->tx_len = tx_len;
914 desc = dmaengine_prep_slave_sg(chan,
921 dev_err(port->dev, "Failed to send via dma!\n");
925 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
927 atmel_port->desc_tx = desc;
928 desc->callback = atmel_complete_tx_dma;
929 desc->callback_param = atmel_port;
930 atmel_port->cookie_tx = dmaengine_submit(desc);
931 if (dma_submit_error(atmel_port->cookie_tx)) {
932 dev_err(port->dev, "dma_submit_error %d\n",
933 atmel_port->cookie_tx);
937 dma_async_issue_pending(chan);
940 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
941 uart_write_wakeup(port);
944 static int atmel_prepare_tx_dma(struct uart_port *port)
946 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
948 struct dma_slave_config config;
952 dma_cap_set(DMA_SLAVE, mask);
954 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
955 if (atmel_port->chan_tx == NULL)
957 dev_info(port->dev, "using %s for tx DMA transfers\n",
958 dma_chan_name(atmel_port->chan_tx));
960 spin_lock_init(&atmel_port->lock_tx);
961 sg_init_table(&atmel_port->sg_tx, 1);
962 /* UART circular tx buffer is an aligned page. */
963 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
964 sg_set_page(&atmel_port->sg_tx,
965 virt_to_page(port->state->xmit.buf),
967 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
968 nent = dma_map_sg(port->dev,
974 dev_dbg(port->dev, "need to release resource of dma\n");
977 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
978 sg_dma_len(&atmel_port->sg_tx),
979 port->state->xmit.buf,
980 &sg_dma_address(&atmel_port->sg_tx));
983 /* Configure the slave DMA */
984 memset(&config, 0, sizeof(config));
985 config.direction = DMA_MEM_TO_DEV;
986 config.dst_addr_width = (atmel_port->fifo_size) ?
987 DMA_SLAVE_BUSWIDTH_4_BYTES :
988 DMA_SLAVE_BUSWIDTH_1_BYTE;
989 config.dst_addr = port->mapbase + ATMEL_US_THR;
990 config.dst_maxburst = 1;
992 ret = dmaengine_slave_config(atmel_port->chan_tx,
995 dev_err(port->dev, "DMA tx slave configuration failed\n");
1002 dev_err(port->dev, "TX channel not available, switch to pio\n");
1003 atmel_port->use_dma_tx = 0;
1004 if (atmel_port->chan_tx)
1005 atmel_release_tx_dma(port);
1009 static void atmel_complete_rx_dma(void *arg)
1011 struct uart_port *port = arg;
1012 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1014 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1017 static void atmel_release_rx_dma(struct uart_port *port)
1019 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1020 struct dma_chan *chan = atmel_port->chan_rx;
1023 dmaengine_terminate_all(chan);
1024 dma_release_channel(chan);
1025 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1029 atmel_port->desc_rx = NULL;
1030 atmel_port->chan_rx = NULL;
1031 atmel_port->cookie_rx = -EINVAL;
1034 static void atmel_rx_from_dma(struct uart_port *port)
1036 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1037 struct tty_port *tport = &port->state->port;
1038 struct circ_buf *ring = &atmel_port->rx_ring;
1039 struct dma_chan *chan = atmel_port->chan_rx;
1040 struct dma_tx_state state;
1041 enum dma_status dmastat;
1045 /* Reset the UART timeout early so that we don't miss one */
1046 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1047 dmastat = dmaengine_tx_status(chan,
1048 atmel_port->cookie_rx,
1050 /* Restart a new tasklet if DMA status is error */
1051 if (dmastat == DMA_ERROR) {
1052 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1053 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1054 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1058 /* CPU claims ownership of RX DMA buffer */
1059 dma_sync_sg_for_cpu(port->dev,
1065 * ring->head points to the end of data already written by the DMA.
1066 * ring->tail points to the beginning of data to be read by the
1068 * The current transfer size should not be larger than the dma buffer
1071 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1072 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1074 * At this point ring->head may point to the first byte right after the
1075 * last byte of the dma buffer:
1076 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1078 * However ring->tail must always points inside the dma buffer:
1079 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1081 * Since we use a ring buffer, we have to handle the case
1082 * where head is lower than tail. In such a case, we first read from
1083 * tail to the end of the buffer then reset tail.
1085 if (ring->head < ring->tail) {
1086 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1088 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1090 port->icount.rx += count;
1093 /* Finally we read data from tail to head */
1094 if (ring->tail < ring->head) {
1095 count = ring->head - ring->tail;
1097 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1098 /* Wrap ring->head if needed */
1099 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1101 ring->tail = ring->head;
1102 port->icount.rx += count;
1105 /* USART retreives ownership of RX DMA buffer */
1106 dma_sync_sg_for_device(port->dev,
1112 * Drop the lock here since it might end up calling
1113 * uart_start(), which takes the lock.
1115 spin_unlock(&port->lock);
1116 tty_flip_buffer_push(tport);
1117 spin_lock(&port->lock);
1119 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1122 static int atmel_prepare_rx_dma(struct uart_port *port)
1124 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1125 struct dma_async_tx_descriptor *desc;
1126 dma_cap_mask_t mask;
1127 struct dma_slave_config config;
1128 struct circ_buf *ring;
1131 ring = &atmel_port->rx_ring;
1134 dma_cap_set(DMA_CYCLIC, mask);
1136 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1137 if (atmel_port->chan_rx == NULL)
1139 dev_info(port->dev, "using %s for rx DMA transfers\n",
1140 dma_chan_name(atmel_port->chan_rx));
1142 spin_lock_init(&atmel_port->lock_rx);
1143 sg_init_table(&atmel_port->sg_rx, 1);
1144 /* UART circular rx buffer is an aligned page. */
1145 BUG_ON(!PAGE_ALIGNED(ring->buf));
1146 sg_set_page(&atmel_port->sg_rx,
1147 virt_to_page(ring->buf),
1148 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1149 (unsigned long)ring->buf & ~PAGE_MASK);
1150 nent = dma_map_sg(port->dev,
1156 dev_dbg(port->dev, "need to release resource of dma\n");
1159 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1160 sg_dma_len(&atmel_port->sg_rx),
1162 &sg_dma_address(&atmel_port->sg_rx));
1165 /* Configure the slave DMA */
1166 memset(&config, 0, sizeof(config));
1167 config.direction = DMA_DEV_TO_MEM;
1168 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1169 config.src_addr = port->mapbase + ATMEL_US_RHR;
1170 config.src_maxburst = 1;
1172 ret = dmaengine_slave_config(atmel_port->chan_rx,
1175 dev_err(port->dev, "DMA rx slave configuration failed\n");
1179 * Prepare a cyclic dma transfer, assign 2 descriptors,
1180 * each one is half ring buffer size
1182 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1183 sg_dma_address(&atmel_port->sg_rx),
1184 sg_dma_len(&atmel_port->sg_rx),
1185 sg_dma_len(&atmel_port->sg_rx)/2,
1187 DMA_PREP_INTERRUPT);
1189 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1192 desc->callback = atmel_complete_rx_dma;
1193 desc->callback_param = port;
1194 atmel_port->desc_rx = desc;
1195 atmel_port->cookie_rx = dmaengine_submit(desc);
1196 if (dma_submit_error(atmel_port->cookie_rx)) {
1197 dev_err(port->dev, "dma_submit_error %d\n",
1198 atmel_port->cookie_rx);
1202 dma_async_issue_pending(atmel_port->chan_rx);
1207 dev_err(port->dev, "RX channel not available, switch to pio\n");
1208 atmel_port->use_dma_rx = 0;
1209 if (atmel_port->chan_rx)
1210 atmel_release_rx_dma(port);
1214 static void atmel_uart_timer_callback(unsigned long data)
1216 struct uart_port *port = (void *)data;
1217 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1219 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1220 tasklet_schedule(&atmel_port->tasklet_rx);
1221 mod_timer(&atmel_port->uart_timer,
1222 jiffies + uart_poll_timeout(port));
1227 * receive interrupt handler.
1230 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1232 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1234 if (atmel_use_pdc_rx(port)) {
1236 * PDC receive. Just schedule the tasklet and let it
1237 * figure out the details.
1239 * TODO: We're not handling error flags correctly at
1242 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1243 atmel_uart_writel(port, ATMEL_US_IDR,
1244 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1245 atmel_tasklet_schedule(atmel_port,
1246 &atmel_port->tasklet_rx);
1249 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1250 ATMEL_US_FRAME | ATMEL_US_PARE))
1251 atmel_pdc_rxerr(port, pending);
1254 if (atmel_use_dma_rx(port)) {
1255 if (pending & ATMEL_US_TIMEOUT) {
1256 atmel_uart_writel(port, ATMEL_US_IDR,
1258 atmel_tasklet_schedule(atmel_port,
1259 &atmel_port->tasklet_rx);
1263 /* Interrupt receive */
1264 if (pending & ATMEL_US_RXRDY)
1265 atmel_rx_chars(port);
1266 else if (pending & ATMEL_US_RXBRK) {
1268 * End of break detected. If it came along with a
1269 * character, atmel_rx_chars will handle it.
1271 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1272 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1273 atmel_port->break_active = 0;
1278 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1281 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1283 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1285 if (pending & atmel_port->tx_done_mask) {
1286 atmel_uart_writel(port, ATMEL_US_IDR,
1287 atmel_port->tx_done_mask);
1289 /* Start RX if flag was set and FIFO is empty */
1290 if (atmel_port->hd_start_rx) {
1291 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1292 & ATMEL_US_TXEMPTY))
1293 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1295 atmel_port->hd_start_rx = false;
1296 atmel_start_rx(port);
1299 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1304 * status flags interrupt handler.
1307 atmel_handle_status(struct uart_port *port, unsigned int pending,
1308 unsigned int status)
1310 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1311 unsigned int status_change;
1313 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1314 | ATMEL_US_CTSIC)) {
1315 status_change = status ^ atmel_port->irq_status_prev;
1316 atmel_port->irq_status_prev = status;
1318 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1319 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1320 /* TODO: All reads to CSR will clear these interrupts! */
1321 if (status_change & ATMEL_US_RI)
1323 if (status_change & ATMEL_US_DSR)
1325 if (status_change & ATMEL_US_DCD)
1326 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1327 if (status_change & ATMEL_US_CTS)
1328 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1330 wake_up_interruptible(&port->state->port.delta_msr_wait);
1338 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1340 struct uart_port *port = dev_id;
1341 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1342 unsigned int status, pending, mask, pass_counter = 0;
1344 spin_lock(&atmel_port->lock_suspended);
1347 status = atmel_get_lines_status(port);
1348 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1349 pending = status & mask;
1353 if (atmel_port->suspended) {
1354 atmel_port->pending |= pending;
1355 atmel_port->pending_status = status;
1356 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1361 atmel_handle_receive(port, pending);
1362 atmel_handle_status(port, pending, status);
1363 atmel_handle_transmit(port, pending);
1364 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1366 spin_unlock(&atmel_port->lock_suspended);
1368 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1371 static void atmel_release_tx_pdc(struct uart_port *port)
1373 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1374 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1376 dma_unmap_single(port->dev,
1383 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1385 static void atmel_tx_pdc(struct uart_port *port)
1387 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1388 struct circ_buf *xmit = &port->state->xmit;
1389 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1392 /* nothing left to transmit? */
1393 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1396 xmit->tail += pdc->ofs;
1397 xmit->tail &= UART_XMIT_SIZE - 1;
1399 port->icount.tx += pdc->ofs;
1402 /* more to transmit - setup next transfer */
1404 /* disable PDC transmit */
1405 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1407 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1408 dma_sync_single_for_device(port->dev,
1413 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1416 atmel_uart_writel(port, ATMEL_PDC_TPR,
1417 pdc->dma_addr + xmit->tail);
1418 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1419 /* re-enable PDC transmit */
1420 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1421 /* Enable interrupts */
1422 atmel_uart_writel(port, ATMEL_US_IER,
1423 atmel_port->tx_done_mask);
1425 if (atmel_uart_is_half_duplex(port)) {
1426 /* DMA done, stop TX, start RX for RS485 */
1427 atmel_start_rx(port);
1431 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1432 uart_write_wakeup(port);
1435 static int atmel_prepare_tx_pdc(struct uart_port *port)
1437 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1438 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1439 struct circ_buf *xmit = &port->state->xmit;
1441 pdc->buf = xmit->buf;
1442 pdc->dma_addr = dma_map_single(port->dev,
1446 pdc->dma_size = UART_XMIT_SIZE;
1452 static void atmel_rx_from_ring(struct uart_port *port)
1454 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1455 struct circ_buf *ring = &atmel_port->rx_ring;
1457 unsigned int status;
1459 while (ring->head != ring->tail) {
1460 struct atmel_uart_char c;
1462 /* Make sure c is loaded after head. */
1465 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1467 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1474 * note that the error handling code is
1475 * out of the main execution path
1477 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1478 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1479 if (status & ATMEL_US_RXBRK) {
1480 /* ignore side-effect */
1481 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1484 if (uart_handle_break(port))
1487 if (status & ATMEL_US_PARE)
1488 port->icount.parity++;
1489 if (status & ATMEL_US_FRAME)
1490 port->icount.frame++;
1491 if (status & ATMEL_US_OVRE)
1492 port->icount.overrun++;
1494 status &= port->read_status_mask;
1496 if (status & ATMEL_US_RXBRK)
1498 else if (status & ATMEL_US_PARE)
1500 else if (status & ATMEL_US_FRAME)
1505 if (uart_handle_sysrq_char(port, c.ch))
1508 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1512 * Drop the lock here since it might end up calling
1513 * uart_start(), which takes the lock.
1515 spin_unlock(&port->lock);
1516 tty_flip_buffer_push(&port->state->port);
1517 spin_lock(&port->lock);
1520 static void atmel_release_rx_pdc(struct uart_port *port)
1522 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1525 for (i = 0; i < 2; i++) {
1526 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1528 dma_unmap_single(port->dev,
1536 static void atmel_rx_from_pdc(struct uart_port *port)
1538 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1539 struct tty_port *tport = &port->state->port;
1540 struct atmel_dma_buffer *pdc;
1541 int rx_idx = atmel_port->pdc_rx_idx;
1547 /* Reset the UART timeout early so that we don't miss one */
1548 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1550 pdc = &atmel_port->pdc_rx[rx_idx];
1551 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1554 /* If the PDC has switched buffers, RPR won't contain
1555 * any address within the current buffer. Since head
1556 * is unsigned, we just need a one-way comparison to
1559 * In this case, we just need to consume the entire
1560 * buffer and resubmit it for DMA. This will clear the
1561 * ENDRX bit as well, so that we can safely re-enable
1562 * all interrupts below.
1564 head = min(head, pdc->dma_size);
1566 if (likely(head != tail)) {
1567 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1568 pdc->dma_size, DMA_FROM_DEVICE);
1571 * head will only wrap around when we recycle
1572 * the DMA buffer, and when that happens, we
1573 * explicitly set tail to 0. So head will
1574 * always be greater than tail.
1576 count = head - tail;
1578 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1581 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1582 pdc->dma_size, DMA_FROM_DEVICE);
1584 port->icount.rx += count;
1589 * If the current buffer is full, we need to check if
1590 * the next one contains any additional data.
1592 if (head >= pdc->dma_size) {
1594 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1595 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1598 atmel_port->pdc_rx_idx = rx_idx;
1600 } while (head >= pdc->dma_size);
1603 * Drop the lock here since it might end up calling
1604 * uart_start(), which takes the lock.
1606 spin_unlock(&port->lock);
1607 tty_flip_buffer_push(tport);
1608 spin_lock(&port->lock);
1610 atmel_uart_writel(port, ATMEL_US_IER,
1611 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1614 static int atmel_prepare_rx_pdc(struct uart_port *port)
1616 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1619 for (i = 0; i < 2; i++) {
1620 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1622 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1623 if (pdc->buf == NULL) {
1625 dma_unmap_single(port->dev,
1626 atmel_port->pdc_rx[0].dma_addr,
1629 kfree(atmel_port->pdc_rx[0].buf);
1631 atmel_port->use_pdc_rx = 0;
1634 pdc->dma_addr = dma_map_single(port->dev,
1638 pdc->dma_size = PDC_BUFFER_SIZE;
1642 atmel_port->pdc_rx_idx = 0;
1644 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1645 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1647 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1648 atmel_port->pdc_rx[1].dma_addr);
1649 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1655 * tasklet handling tty stuff outside the interrupt handler.
1657 static void atmel_tasklet_rx_func(unsigned long data)
1659 struct uart_port *port = (struct uart_port *)data;
1660 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1662 /* The interrupt handler does not take the lock */
1663 spin_lock(&port->lock);
1664 atmel_port->schedule_rx(port);
1665 spin_unlock(&port->lock);
1668 static void atmel_tasklet_tx_func(unsigned long data)
1670 struct uart_port *port = (struct uart_port *)data;
1671 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1673 /* The interrupt handler does not take the lock */
1674 spin_lock(&port->lock);
1675 atmel_port->schedule_tx(port);
1676 spin_unlock(&port->lock);
1679 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1680 struct platform_device *pdev)
1682 struct device_node *np = pdev->dev.of_node;
1683 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1686 /* DMA/PDC usage specification */
1687 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1688 if (of_property_read_bool(np, "dmas")) {
1689 atmel_port->use_dma_rx = true;
1690 atmel_port->use_pdc_rx = false;
1692 atmel_port->use_dma_rx = false;
1693 atmel_port->use_pdc_rx = true;
1696 atmel_port->use_dma_rx = false;
1697 atmel_port->use_pdc_rx = false;
1700 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1701 if (of_property_read_bool(np, "dmas")) {
1702 atmel_port->use_dma_tx = true;
1703 atmel_port->use_pdc_tx = false;
1705 atmel_port->use_dma_tx = false;
1706 atmel_port->use_pdc_tx = true;
1709 atmel_port->use_dma_tx = false;
1710 atmel_port->use_pdc_tx = false;
1714 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1715 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1716 atmel_port->use_dma_rx = false;
1717 atmel_port->use_dma_tx = false;
1722 static void atmel_init_rs485(struct uart_port *port,
1723 struct platform_device *pdev)
1725 struct device_node *np = pdev->dev.of_node;
1726 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1729 struct serial_rs485 *rs485conf = &port->rs485;
1731 /* rs485 properties */
1732 if (of_property_read_u32_array(np, "rs485-rts-delay",
1733 rs485_delay, 2) == 0) {
1734 rs485conf->delay_rts_before_send = rs485_delay[0];
1735 rs485conf->delay_rts_after_send = rs485_delay[1];
1736 rs485conf->flags = 0;
1739 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1740 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1742 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1744 rs485conf->flags |= SER_RS485_ENABLED;
1746 port->rs485 = pdata->rs485;
1751 static void atmel_set_ops(struct uart_port *port)
1753 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1755 if (atmel_use_dma_rx(port)) {
1756 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1757 atmel_port->schedule_rx = &atmel_rx_from_dma;
1758 atmel_port->release_rx = &atmel_release_rx_dma;
1759 } else if (atmel_use_pdc_rx(port)) {
1760 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1761 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1762 atmel_port->release_rx = &atmel_release_rx_pdc;
1764 atmel_port->prepare_rx = NULL;
1765 atmel_port->schedule_rx = &atmel_rx_from_ring;
1766 atmel_port->release_rx = NULL;
1769 if (atmel_use_dma_tx(port)) {
1770 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1771 atmel_port->schedule_tx = &atmel_tx_dma;
1772 atmel_port->release_tx = &atmel_release_tx_dma;
1773 } else if (atmel_use_pdc_tx(port)) {
1774 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1775 atmel_port->schedule_tx = &atmel_tx_pdc;
1776 atmel_port->release_tx = &atmel_release_tx_pdc;
1778 atmel_port->prepare_tx = NULL;
1779 atmel_port->schedule_tx = &atmel_tx_chars;
1780 atmel_port->release_tx = NULL;
1785 * Get ip name usart or uart
1787 static void atmel_get_ip_name(struct uart_port *port)
1789 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1790 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1792 u32 usart, dbgu_uart, new_uart;
1793 /* ASCII decoding for IP version */
1794 usart = 0x55534152; /* USAR(T) */
1795 dbgu_uart = 0x44424755; /* DBGU */
1796 new_uart = 0x55415254; /* UART */
1799 * Only USART devices from at91sam9260 SOC implement fractional
1802 atmel_port->has_frac_baudrate = false;
1803 atmel_port->has_hw_timer = false;
1805 if (name == new_uart) {
1806 dev_dbg(port->dev, "Uart with hw timer");
1807 atmel_port->has_hw_timer = true;
1808 atmel_port->rtor = ATMEL_UA_RTOR;
1809 } else if (name == usart) {
1810 dev_dbg(port->dev, "Usart\n");
1811 atmel_port->has_frac_baudrate = true;
1812 atmel_port->has_hw_timer = true;
1813 atmel_port->rtor = ATMEL_US_RTOR;
1814 } else if (name == dbgu_uart) {
1815 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1817 /* fallback for older SoCs: use version field */
1818 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1823 dev_dbg(port->dev, "This version is usart\n");
1824 atmel_port->has_frac_baudrate = true;
1825 atmel_port->has_hw_timer = true;
1826 atmel_port->rtor = ATMEL_US_RTOR;
1830 dev_dbg(port->dev, "This version is uart\n");
1833 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1839 * Perform initialization and enable port for reception
1841 static int atmel_startup(struct uart_port *port)
1843 struct platform_device *pdev = to_platform_device(port->dev);
1844 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1848 * Ensure that no interrupts are enabled otherwise when
1849 * request_irq() is called we could get stuck trying to
1850 * handle an unexpected interrupt
1852 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1853 atmel_port->ms_irq_enabled = false;
1858 retval = request_irq(port->irq, atmel_interrupt,
1859 IRQF_SHARED | IRQF_COND_SUSPEND,
1860 dev_name(&pdev->dev), port);
1862 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1866 atomic_set(&atmel_port->tasklet_shutdown, 0);
1867 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1868 (unsigned long)port);
1869 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1870 (unsigned long)port);
1873 * Initialize DMA (if necessary)
1875 atmel_init_property(atmel_port, pdev);
1876 atmel_set_ops(port);
1878 if (atmel_port->prepare_rx) {
1879 retval = atmel_port->prepare_rx(port);
1881 atmel_set_ops(port);
1884 if (atmel_port->prepare_tx) {
1885 retval = atmel_port->prepare_tx(port);
1887 atmel_set_ops(port);
1891 * Enable FIFO when available
1893 if (atmel_port->fifo_size) {
1894 unsigned int txrdym = ATMEL_US_ONE_DATA;
1895 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1898 atmel_uart_writel(port, ATMEL_US_CR,
1903 if (atmel_use_dma_tx(port))
1904 txrdym = ATMEL_US_FOUR_DATA;
1906 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1907 if (atmel_port->rts_high &&
1908 atmel_port->rts_low)
1909 fmr |= ATMEL_US_FRTSC |
1910 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1911 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1913 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1916 /* Save current CSR for comparison in atmel_tasklet_func() */
1917 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1920 * Finally, enable the serial port
1922 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1923 /* enable xmit & rcvr */
1924 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1926 setup_timer(&atmel_port->uart_timer,
1927 atmel_uart_timer_callback,
1928 (unsigned long)port);
1930 if (atmel_use_pdc_rx(port)) {
1931 /* set UART timeout */
1932 if (!atmel_port->has_hw_timer) {
1933 mod_timer(&atmel_port->uart_timer,
1934 jiffies + uart_poll_timeout(port));
1935 /* set USART timeout */
1937 atmel_uart_writel(port, atmel_port->rtor,
1939 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1941 atmel_uart_writel(port, ATMEL_US_IER,
1942 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1944 /* enable PDC controller */
1945 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1946 } else if (atmel_use_dma_rx(port)) {
1947 /* set UART timeout */
1948 if (!atmel_port->has_hw_timer) {
1949 mod_timer(&atmel_port->uart_timer,
1950 jiffies + uart_poll_timeout(port));
1951 /* set USART timeout */
1953 atmel_uart_writel(port, atmel_port->rtor,
1955 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1957 atmel_uart_writel(port, ATMEL_US_IER,
1961 /* enable receive only */
1962 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1969 * Flush any TX data submitted for DMA. Called when the TX circular
1972 static void atmel_flush_buffer(struct uart_port *port)
1974 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1976 if (atmel_use_pdc_tx(port)) {
1977 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1978 atmel_port->pdc_tx.ofs = 0;
1981 * in uart_flush_buffer(), the xmit circular buffer has just
1982 * been cleared, so we have to reset tx_len accordingly.
1984 atmel_port->tx_len = 0;
1990 static void atmel_shutdown(struct uart_port *port)
1992 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1994 /* Disable modem control lines interrupts */
1995 atmel_disable_ms(port);
1997 /* Disable interrupts at device level */
1998 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2000 /* Prevent spurious interrupts from scheduling the tasklet */
2001 atomic_inc(&atmel_port->tasklet_shutdown);
2004 * Prevent any tasklets being scheduled during
2007 del_timer_sync(&atmel_port->uart_timer);
2009 /* Make sure that no interrupt is on the fly */
2010 synchronize_irq(port->irq);
2013 * Clear out any scheduled tasklets before
2014 * we destroy the buffers
2016 tasklet_kill(&atmel_port->tasklet_rx);
2017 tasklet_kill(&atmel_port->tasklet_tx);
2020 * Ensure everything is stopped and
2021 * disable port and break condition.
2023 atmel_stop_rx(port);
2024 atmel_stop_tx(port);
2026 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2029 * Shut-down the DMA.
2031 if (atmel_port->release_rx)
2032 atmel_port->release_rx(port);
2033 if (atmel_port->release_tx)
2034 atmel_port->release_tx(port);
2037 * Reset ring buffer pointers
2039 atmel_port->rx_ring.head = 0;
2040 atmel_port->rx_ring.tail = 0;
2043 * Free the interrupts
2045 free_irq(port->irq, port);
2047 atmel_flush_buffer(port);
2051 * Power / Clock management.
2053 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2054 unsigned int oldstate)
2056 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2061 * Enable the peripheral clock for this serial port.
2062 * This is called on uart_open() or a resume event.
2064 clk_prepare_enable(atmel_port->clk);
2066 /* re-enable interrupts if we disabled some on suspend */
2067 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2070 /* Back up the interrupt mask and disable all interrupts */
2071 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2072 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2075 * Disable the peripheral clock for this serial port.
2076 * This is called on uart_close() or a suspend event.
2078 clk_disable_unprepare(atmel_port->clk);
2081 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2086 * Change the port parameters
2088 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2089 struct ktermios *old)
2091 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2092 unsigned long flags;
2093 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2095 /* save the current mode register */
2096 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2098 /* reset the mode, clock divisor, parity, stop bits and data size */
2099 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2100 ATMEL_US_PAR | ATMEL_US_USMODE);
2102 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2105 switch (termios->c_cflag & CSIZE) {
2107 mode |= ATMEL_US_CHRL_5;
2110 mode |= ATMEL_US_CHRL_6;
2113 mode |= ATMEL_US_CHRL_7;
2116 mode |= ATMEL_US_CHRL_8;
2121 if (termios->c_cflag & CSTOPB)
2122 mode |= ATMEL_US_NBSTOP_2;
2125 if (termios->c_cflag & PARENB) {
2126 /* Mark or Space parity */
2127 if (termios->c_cflag & CMSPAR) {
2128 if (termios->c_cflag & PARODD)
2129 mode |= ATMEL_US_PAR_MARK;
2131 mode |= ATMEL_US_PAR_SPACE;
2132 } else if (termios->c_cflag & PARODD)
2133 mode |= ATMEL_US_PAR_ODD;
2135 mode |= ATMEL_US_PAR_EVEN;
2137 mode |= ATMEL_US_PAR_NONE;
2139 spin_lock_irqsave(&port->lock, flags);
2141 port->read_status_mask = ATMEL_US_OVRE;
2142 if (termios->c_iflag & INPCK)
2143 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2144 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2145 port->read_status_mask |= ATMEL_US_RXBRK;
2147 if (atmel_use_pdc_rx(port))
2148 /* need to enable error interrupts */
2149 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2152 * Characters to ignore
2154 port->ignore_status_mask = 0;
2155 if (termios->c_iflag & IGNPAR)
2156 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2157 if (termios->c_iflag & IGNBRK) {
2158 port->ignore_status_mask |= ATMEL_US_RXBRK;
2160 * If we're ignoring parity and break indicators,
2161 * ignore overruns too (for real raw support).
2163 if (termios->c_iflag & IGNPAR)
2164 port->ignore_status_mask |= ATMEL_US_OVRE;
2166 /* TODO: Ignore all characters if CREAD is set.*/
2168 /* update the per-port timeout */
2169 uart_update_timeout(port, termios->c_cflag, baud);
2172 * save/disable interrupts. The tty layer will ensure that the
2173 * transmitter is empty if requested by the caller, so there's
2174 * no need to wait for it here.
2176 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2177 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2179 /* disable receiver and transmitter */
2180 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2183 if (port->rs485.flags & SER_RS485_ENABLED) {
2184 atmel_uart_writel(port, ATMEL_US_TTGR,
2185 port->rs485.delay_rts_after_send);
2186 mode |= ATMEL_US_USMODE_RS485;
2187 } else if (termios->c_cflag & CRTSCTS) {
2188 /* RS232 with hardware handshake (RTS/CTS) */
2189 if (atmel_use_fifo(port) &&
2190 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2192 * with ATMEL_US_USMODE_HWHS set, the controller will
2193 * be able to drive the RTS pin high/low when the RX
2194 * FIFO is above RXFTHRES/below RXFTHRES2.
2195 * It will also disable the transmitter when the CTS
2197 * This mode is not activated if CTS pin is a GPIO
2198 * because in this case, the transmitter is always
2199 * disabled (there must be an internal pull-up
2200 * responsible for this behaviour).
2201 * If the RTS pin is a GPIO, the controller won't be
2202 * able to drive it according to the FIFO thresholds,
2203 * but it will be handled by the driver.
2205 mode |= ATMEL_US_USMODE_HWHS;
2208 * For platforms without FIFO, the flow control is
2209 * handled by the driver.
2211 mode |= ATMEL_US_USMODE_NORMAL;
2214 /* RS232 without hadware handshake */
2215 mode |= ATMEL_US_USMODE_NORMAL;
2219 * Set the baud rate:
2220 * Fractional baudrate allows to setup output frequency more
2221 * accurately. This feature is enabled only when using normal mode.
2222 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2223 * Currently, OVER is always set to 0 so we get
2224 * baudrate = selected clock / (16 * (CD + FP / 8))
2226 * 8 CD + FP = selected clock / (2 * baudrate)
2228 if (atmel_port->has_frac_baudrate &&
2229 (mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_NORMAL) {
2230 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2232 fp = div & ATMEL_US_FP_MASK;
2234 cd = uart_get_divisor(port, baud);
2237 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2239 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2241 quot = cd | fp << ATMEL_US_FP_OFFSET;
2243 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2245 /* set the mode, clock divisor, parity, stop bits and data size */
2246 atmel_uart_writel(port, ATMEL_US_MR, mode);
2249 * when switching the mode, set the RTS line state according to the
2250 * new mode, otherwise keep the former state
2252 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2253 unsigned int rts_state;
2255 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2256 /* let the hardware control the RTS line */
2257 rts_state = ATMEL_US_RTSDIS;
2259 /* force RTS line to low level */
2260 rts_state = ATMEL_US_RTSEN;
2263 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2266 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2267 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2269 /* restore interrupts */
2270 atmel_uart_writel(port, ATMEL_US_IER, imr);
2272 /* CTS flow-control and modem-status interrupts */
2273 if (UART_ENABLE_MS(port, termios->c_cflag))
2274 atmel_enable_ms(port);
2276 atmel_disable_ms(port);
2278 spin_unlock_irqrestore(&port->lock, flags);
2281 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2283 if (termios->c_line == N_PPS) {
2284 port->flags |= UPF_HARDPPS_CD;
2285 spin_lock_irq(&port->lock);
2286 atmel_enable_ms(port);
2287 spin_unlock_irq(&port->lock);
2289 port->flags &= ~UPF_HARDPPS_CD;
2290 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2291 spin_lock_irq(&port->lock);
2292 atmel_disable_ms(port);
2293 spin_unlock_irq(&port->lock);
2299 * Return string describing the specified port
2301 static const char *atmel_type(struct uart_port *port)
2303 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2307 * Release the memory region(s) being used by 'port'.
2309 static void atmel_release_port(struct uart_port *port)
2311 struct platform_device *pdev = to_platform_device(port->dev);
2312 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2314 release_mem_region(port->mapbase, size);
2316 if (port->flags & UPF_IOREMAP) {
2317 iounmap(port->membase);
2318 port->membase = NULL;
2323 * Request the memory region(s) being used by 'port'.
2325 static int atmel_request_port(struct uart_port *port)
2327 struct platform_device *pdev = to_platform_device(port->dev);
2328 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2330 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2333 if (port->flags & UPF_IOREMAP) {
2334 port->membase = ioremap(port->mapbase, size);
2335 if (port->membase == NULL) {
2336 release_mem_region(port->mapbase, size);
2345 * Configure/autoconfigure the port.
2347 static void atmel_config_port(struct uart_port *port, int flags)
2349 if (flags & UART_CONFIG_TYPE) {
2350 port->type = PORT_ATMEL;
2351 atmel_request_port(port);
2356 * Verify the new serial_struct (for TIOCSSERIAL).
2358 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2361 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2363 if (port->irq != ser->irq)
2365 if (ser->io_type != SERIAL_IO_MEM)
2367 if (port->uartclk / 16 != ser->baud_base)
2369 if (port->mapbase != (unsigned long)ser->iomem_base)
2371 if (port->iobase != ser->port)
2378 #ifdef CONFIG_CONSOLE_POLL
2379 static int atmel_poll_get_char(struct uart_port *port)
2381 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2384 return atmel_uart_read_char(port);
2387 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2389 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2392 atmel_uart_write_char(port, ch);
2396 static const struct uart_ops atmel_pops = {
2397 .tx_empty = atmel_tx_empty,
2398 .set_mctrl = atmel_set_mctrl,
2399 .get_mctrl = atmel_get_mctrl,
2400 .stop_tx = atmel_stop_tx,
2401 .start_tx = atmel_start_tx,
2402 .stop_rx = atmel_stop_rx,
2403 .enable_ms = atmel_enable_ms,
2404 .break_ctl = atmel_break_ctl,
2405 .startup = atmel_startup,
2406 .shutdown = atmel_shutdown,
2407 .flush_buffer = atmel_flush_buffer,
2408 .set_termios = atmel_set_termios,
2409 .set_ldisc = atmel_set_ldisc,
2411 .release_port = atmel_release_port,
2412 .request_port = atmel_request_port,
2413 .config_port = atmel_config_port,
2414 .verify_port = atmel_verify_port,
2415 .pm = atmel_serial_pm,
2416 #ifdef CONFIG_CONSOLE_POLL
2417 .poll_get_char = atmel_poll_get_char,
2418 .poll_put_char = atmel_poll_put_char,
2423 * Configure the port from the platform device resource info.
2425 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2426 struct platform_device *pdev)
2429 struct uart_port *port = &atmel_port->uart;
2430 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2432 atmel_init_property(atmel_port, pdev);
2433 atmel_set_ops(port);
2435 atmel_init_rs485(port, pdev);
2437 port->iotype = UPIO_MEM;
2438 port->flags = UPF_BOOT_AUTOCONF;
2439 port->ops = &atmel_pops;
2441 port->dev = &pdev->dev;
2442 port->mapbase = pdev->resource[0].start;
2443 port->irq = pdev->resource[1].start;
2444 port->rs485_config = atmel_config_rs485;
2446 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2448 if (pdata && pdata->regs) {
2449 /* Already mapped by setup code */
2450 port->membase = pdata->regs;
2452 port->flags |= UPF_IOREMAP;
2453 port->membase = NULL;
2456 /* for console, the clock could already be configured */
2457 if (!atmel_port->clk) {
2458 atmel_port->clk = clk_get(&pdev->dev, "usart");
2459 if (IS_ERR(atmel_port->clk)) {
2460 ret = PTR_ERR(atmel_port->clk);
2461 atmel_port->clk = NULL;
2464 ret = clk_prepare_enable(atmel_port->clk);
2466 clk_put(atmel_port->clk);
2467 atmel_port->clk = NULL;
2470 port->uartclk = clk_get_rate(atmel_port->clk);
2471 clk_disable_unprepare(atmel_port->clk);
2472 /* only enable clock when USART is in use */
2475 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2476 if (port->rs485.flags & SER_RS485_ENABLED)
2477 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2478 else if (atmel_use_pdc_tx(port)) {
2479 port->fifosize = PDC_BUFFER_SIZE;
2480 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2482 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2488 struct platform_device *atmel_default_console_device; /* the serial console device */
2490 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2491 static void atmel_console_putchar(struct uart_port *port, int ch)
2493 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2495 atmel_uart_write_char(port, ch);
2499 * Interrupts are disabled on entering
2501 static void atmel_console_write(struct console *co, const char *s, u_int count)
2503 struct uart_port *port = &atmel_ports[co->index].uart;
2504 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2505 unsigned int status, imr;
2506 unsigned int pdc_tx;
2509 * First, save IMR and then disable interrupts
2511 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2512 atmel_uart_writel(port, ATMEL_US_IDR,
2513 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2515 /* Store PDC transmit status and disable it */
2516 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2517 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2519 /* Make sure that tx path is actually able to send characters */
2520 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2522 uart_console_write(port, s, count, atmel_console_putchar);
2525 * Finally, wait for transmitter to become empty
2529 status = atmel_uart_readl(port, ATMEL_US_CSR);
2530 } while (!(status & ATMEL_US_TXRDY));
2532 /* Restore PDC transmit status */
2534 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2536 /* set interrupts back the way they were */
2537 atmel_uart_writel(port, ATMEL_US_IER, imr);
2541 * If the port was already initialised (eg, by a boot loader),
2542 * try to determine the current setup.
2544 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2545 int *parity, int *bits)
2547 unsigned int mr, quot;
2550 * If the baud rate generator isn't running, the port wasn't
2551 * initialized by the boot loader.
2553 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2557 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2558 if (mr == ATMEL_US_CHRL_8)
2563 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2564 if (mr == ATMEL_US_PAR_EVEN)
2566 else if (mr == ATMEL_US_PAR_ODD)
2570 * The serial core only rounds down when matching this to a
2571 * supported baud rate. Make sure we don't end up slightly
2572 * lower than one of those, as it would make us fall through
2573 * to a much lower baud rate than we really want.
2575 *baud = port->uartclk / (16 * (quot - 1));
2578 static int __init atmel_console_setup(struct console *co, char *options)
2581 struct uart_port *port = &atmel_ports[co->index].uart;
2587 if (port->membase == NULL) {
2588 /* Port not initialized yet - delay setup */
2592 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2596 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2597 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2598 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2601 uart_parse_options(options, &baud, &parity, &bits, &flow);
2603 atmel_console_get_options(port, &baud, &parity, &bits);
2605 return uart_set_options(port, co, baud, parity, bits, flow);
2608 static struct uart_driver atmel_uart;
2610 static struct console atmel_console = {
2611 .name = ATMEL_DEVICENAME,
2612 .write = atmel_console_write,
2613 .device = uart_console_device,
2614 .setup = atmel_console_setup,
2615 .flags = CON_PRINTBUFFER,
2617 .data = &atmel_uart,
2620 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2623 * Early console initialization (before VM subsystem initialized).
2625 static int __init atmel_console_init(void)
2628 if (atmel_default_console_device) {
2629 struct atmel_uart_data *pdata =
2630 dev_get_platdata(&atmel_default_console_device->dev);
2631 int id = pdata->num;
2632 struct atmel_uart_port *atmel_port = &atmel_ports[id];
2634 atmel_port->backup_imr = 0;
2635 atmel_port->uart.line = id;
2637 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2638 ret = atmel_init_port(atmel_port, atmel_default_console_device);
2641 register_console(&atmel_console);
2647 console_initcall(atmel_console_init);
2650 * Late console initialization.
2652 static int __init atmel_late_console_init(void)
2654 if (atmel_default_console_device
2655 && !(atmel_console.flags & CON_ENABLED))
2656 register_console(&atmel_console);
2661 core_initcall(atmel_late_console_init);
2663 static inline bool atmel_is_console_port(struct uart_port *port)
2665 return port->cons && port->cons->index == port->line;
2669 #define ATMEL_CONSOLE_DEVICE NULL
2671 static inline bool atmel_is_console_port(struct uart_port *port)
2677 static struct uart_driver atmel_uart = {
2678 .owner = THIS_MODULE,
2679 .driver_name = "atmel_serial",
2680 .dev_name = ATMEL_DEVICENAME,
2681 .major = SERIAL_ATMEL_MAJOR,
2682 .minor = MINOR_START,
2683 .nr = ATMEL_MAX_UART,
2684 .cons = ATMEL_CONSOLE_DEVICE,
2688 static bool atmel_serial_clk_will_stop(void)
2690 #ifdef CONFIG_ARCH_AT91
2691 return at91_suspend_entering_slow_clock();
2697 static int atmel_serial_suspend(struct platform_device *pdev,
2700 struct uart_port *port = platform_get_drvdata(pdev);
2701 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2703 if (atmel_is_console_port(port) && console_suspend_enabled) {
2704 /* Drain the TX shifter */
2705 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2710 /* we can not wake up if we're running on slow clock */
2711 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2712 if (atmel_serial_clk_will_stop()) {
2713 unsigned long flags;
2715 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2716 atmel_port->suspended = true;
2717 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2718 device_set_wakeup_enable(&pdev->dev, 0);
2721 uart_suspend_port(&atmel_uart, port);
2726 static int atmel_serial_resume(struct platform_device *pdev)
2728 struct uart_port *port = platform_get_drvdata(pdev);
2729 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2730 unsigned long flags;
2732 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2733 if (atmel_port->pending) {
2734 atmel_handle_receive(port, atmel_port->pending);
2735 atmel_handle_status(port, atmel_port->pending,
2736 atmel_port->pending_status);
2737 atmel_handle_transmit(port, atmel_port->pending);
2738 atmel_port->pending = 0;
2740 atmel_port->suspended = false;
2741 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2743 uart_resume_port(&atmel_uart, port);
2744 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2749 #define atmel_serial_suspend NULL
2750 #define atmel_serial_resume NULL
2753 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2754 struct platform_device *pdev)
2756 atmel_port->fifo_size = 0;
2757 atmel_port->rts_low = 0;
2758 atmel_port->rts_high = 0;
2760 if (of_property_read_u32(pdev->dev.of_node,
2762 &atmel_port->fifo_size))
2765 if (!atmel_port->fifo_size)
2768 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2769 atmel_port->fifo_size = 0;
2770 dev_err(&pdev->dev, "Invalid FIFO size\n");
2775 * 0 <= rts_low <= rts_high <= fifo_size
2776 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2777 * to flush their internal TX FIFO, commonly up to 16 data, before
2778 * actually stopping to send new data. So we try to set the RTS High
2779 * Threshold to a reasonably high value respecting this 16 data
2780 * empirical rule when possible.
2782 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2783 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2784 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2785 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2787 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2788 atmel_port->fifo_size);
2789 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2790 atmel_port->rts_high);
2791 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2792 atmel_port->rts_low);
2795 static int atmel_serial_probe(struct platform_device *pdev)
2797 struct atmel_uart_port *atmel_port;
2798 struct device_node *np = pdev->dev.of_node;
2799 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2804 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2807 ret = of_alias_get_id(np, "serial");
2813 /* port id not found in platform data nor device-tree aliases:
2814 * auto-enumerate it */
2815 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2817 if (ret >= ATMEL_MAX_UART) {
2822 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2823 /* port already in use */
2828 atmel_port = &atmel_ports[ret];
2829 atmel_port->backup_imr = 0;
2830 atmel_port->uart.line = ret;
2831 atmel_serial_probe_fifos(atmel_port, pdev);
2833 atomic_set(&atmel_port->tasklet_shutdown, 0);
2834 spin_lock_init(&atmel_port->lock_suspended);
2836 ret = atmel_init_port(atmel_port, pdev);
2840 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2841 if (IS_ERR(atmel_port->gpios)) {
2842 ret = PTR_ERR(atmel_port->gpios);
2846 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2848 data = kmalloc(sizeof(struct atmel_uart_char)
2849 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2851 goto err_alloc_ring;
2852 atmel_port->rx_ring.buf = data;
2855 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2857 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2861 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2862 if (atmel_is_console_port(&atmel_port->uart)
2863 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2865 * The serial core enabled the clock for us, so undo
2866 * the clk_prepare_enable() in atmel_console_setup()
2868 clk_disable_unprepare(atmel_port->clk);
2872 device_init_wakeup(&pdev->dev, 1);
2873 platform_set_drvdata(pdev, atmel_port);
2876 * The peripheral clock has been disabled by atmel_init_port():
2877 * enable it before accessing I/O registers
2879 clk_prepare_enable(atmel_port->clk);
2881 if (rs485_enabled) {
2882 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2883 ATMEL_US_USMODE_NORMAL);
2884 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2889 * Get port name of usart or uart
2891 atmel_get_ip_name(&atmel_port->uart);
2894 * The peripheral clock can now safely be disabled till the port
2897 clk_disable_unprepare(atmel_port->clk);
2902 kfree(atmel_port->rx_ring.buf);
2903 atmel_port->rx_ring.buf = NULL;
2905 if (!atmel_is_console_port(&atmel_port->uart)) {
2906 clk_put(atmel_port->clk);
2907 atmel_port->clk = NULL;
2910 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2916 * Even if the driver is not modular, it makes sense to be able to
2917 * unbind a device: there can be many bound devices, and there are
2918 * situations where dynamic binding and unbinding can be useful.
2920 * For example, a connected device can require a specific firmware update
2921 * protocol that needs bitbanging on IO lines, but use the regular serial
2922 * port in the normal case.
2924 static int atmel_serial_remove(struct platform_device *pdev)
2926 struct uart_port *port = platform_get_drvdata(pdev);
2927 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2930 tasklet_kill(&atmel_port->tasklet_rx);
2931 tasklet_kill(&atmel_port->tasklet_tx);
2933 device_init_wakeup(&pdev->dev, 0);
2935 ret = uart_remove_one_port(&atmel_uart, port);
2937 kfree(atmel_port->rx_ring.buf);
2939 /* "port" is allocated statically, so we shouldn't free it */
2941 clear_bit(port->line, atmel_ports_in_use);
2943 clk_put(atmel_port->clk);
2944 atmel_port->clk = NULL;
2949 static struct platform_driver atmel_serial_driver = {
2950 .probe = atmel_serial_probe,
2951 .remove = atmel_serial_remove,
2952 .suspend = atmel_serial_suspend,
2953 .resume = atmel_serial_resume,
2955 .name = "atmel_usart",
2956 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2960 static int __init atmel_serial_init(void)
2964 ret = uart_register_driver(&atmel_uart);
2968 ret = platform_driver_register(&atmel_serial_driver);
2970 uart_unregister_driver(&atmel_uart);
2974 device_initcall(atmel_serial_init);