1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH MSIOF SPI Controller Interface
5 * Copyright (c) 2009 Magnus Damm
6 * Copyright (C) 2014 Renesas Electronics Corporation
7 * Copyright (C) 2014-2017 Glider bvba
10 #include <linux/bitmap.h>
11 #include <linux/clk.h>
12 #include <linux/completion.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmaengine.h>
16 #include <linux/err.h>
17 #include <linux/interrupt.h>
19 #include <linux/iopoll.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/sh_dma.h>
28 #include <linux/spi/sh_msiof.h>
29 #include <linux/spi/spi.h>
31 #include <asm/unaligned.h>
33 #define SH_MSIOF_FLAG_FIXED_DTDL_200 BIT(0)
35 struct sh_msiof_chipdata {
36 u32 bits_per_word_mask;
44 struct sh_msiof_spi_priv {
45 struct spi_controller *ctlr;
46 void __iomem *mapbase;
48 struct platform_device *pdev;
49 struct sh_msiof_spi_info *info;
50 struct completion done;
51 struct completion done_txdma;
52 unsigned int tx_fifo_size;
53 unsigned int rx_fifo_size;
54 unsigned int min_div_pow;
57 dma_addr_t tx_dma_addr;
58 dma_addr_t rx_dma_addr;
59 bool native_cs_inited;
64 #define MAX_SS 3 /* Maximum number of native chip selects */
66 #define SITMDR1 0x00 /* Transmit Mode Register 1 */
67 #define SITMDR2 0x04 /* Transmit Mode Register 2 */
68 #define SITMDR3 0x08 /* Transmit Mode Register 3 */
69 #define SIRMDR1 0x10 /* Receive Mode Register 1 */
70 #define SIRMDR2 0x14 /* Receive Mode Register 2 */
71 #define SIRMDR3 0x18 /* Receive Mode Register 3 */
72 #define SITSCR 0x20 /* Transmit Clock Select Register */
73 #define SIRSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
74 #define SICTR 0x28 /* Control Register */
75 #define SIFCTR 0x30 /* FIFO Control Register */
76 #define SISTR 0x40 /* Status Register */
77 #define SIIER 0x44 /* Interrupt Enable Register */
78 #define SITDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
79 #define SITDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
80 #define SITFDR 0x50 /* Transmit FIFO Data Register */
81 #define SIRDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
82 #define SIRDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
83 #define SIRFDR 0x60 /* Receive FIFO Data Register */
85 /* SITMDR1 and SIRMDR1 */
86 #define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */
87 #define SIMDR1_SYNCMD_MASK GENMASK(29, 28) /* SYNC Mode */
88 #define SIMDR1_SYNCMD_SPI (2 << 28) /* Level mode/SPI */
89 #define SIMDR1_SYNCMD_LR (3 << 28) /* L/R mode */
90 #define SIMDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
91 #define SIMDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
92 #define SIMDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
93 #define SIMDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
94 #define SIMDR1_FLD_MASK GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
95 #define SIMDR1_FLD_SHIFT 2
96 #define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */
98 #define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */
99 #define SITMDR1_SYNCCH_MASK GENMASK(27, 26) /* Sync Signal Channel Select */
100 #define SITMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
102 /* SITMDR2 and SIRMDR2 */
103 #define SIMDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
104 #define SIMDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
105 #define SIMDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */
107 /* SITSCR and SIRSCR */
108 #define SISCR_BRPS_MASK GENMASK(12, 8) /* Prescaler Setting (1-32) */
109 #define SISCR_BRPS(i) (((i) - 1) << 8)
110 #define SISCR_BRDV_MASK GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */
111 #define SISCR_BRDV_DIV_2 0
112 #define SISCR_BRDV_DIV_4 1
113 #define SISCR_BRDV_DIV_8 2
114 #define SISCR_BRDV_DIV_16 3
115 #define SISCR_BRDV_DIV_32 4
116 #define SISCR_BRDV_DIV_1 7
119 #define SICTR_TSCKIZ_MASK GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */
120 #define SICTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */
121 #define SICTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
122 #define SICTR_RSCKIZ_MASK GENMASK(29, 28) /* Receive Clock Polarity Select */
123 #define SICTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */
124 #define SICTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
125 #define SICTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
126 #define SICTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
127 #define SICTR_TXDIZ_MASK GENMASK(23, 22) /* Pin Output When TX is Disabled */
128 #define SICTR_TXDIZ_LOW (0 << 22) /* 0 */
129 #define SICTR_TXDIZ_HIGH (1 << 22) /* 1 */
130 #define SICTR_TXDIZ_HIZ (2 << 22) /* High-impedance */
131 #define SICTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */
132 #define SICTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */
133 #define SICTR_TXE BIT(9) /* Transmit Enable */
134 #define SICTR_RXE BIT(8) /* Receive Enable */
135 #define SICTR_TXRST BIT(1) /* Transmit Reset */
136 #define SICTR_RXRST BIT(0) /* Receive Reset */
139 #define SIFCTR_TFWM_MASK GENMASK(31, 29) /* Transmit FIFO Watermark */
140 #define SIFCTR_TFWM_64 (0UL << 29) /* Transfer Request when 64 empty stages */
141 #define SIFCTR_TFWM_32 (1UL << 29) /* Transfer Request when 32 empty stages */
142 #define SIFCTR_TFWM_24 (2UL << 29) /* Transfer Request when 24 empty stages */
143 #define SIFCTR_TFWM_16 (3UL << 29) /* Transfer Request when 16 empty stages */
144 #define SIFCTR_TFWM_12 (4UL << 29) /* Transfer Request when 12 empty stages */
145 #define SIFCTR_TFWM_8 (5UL << 29) /* Transfer Request when 8 empty stages */
146 #define SIFCTR_TFWM_4 (6UL << 29) /* Transfer Request when 4 empty stages */
147 #define SIFCTR_TFWM_1 (7UL << 29) /* Transfer Request when 1 empty stage */
148 #define SIFCTR_TFUA_MASK GENMASK(26, 20) /* Transmit FIFO Usable Area */
149 #define SIFCTR_TFUA_SHIFT 20
150 #define SIFCTR_TFUA(i) ((i) << SIFCTR_TFUA_SHIFT)
151 #define SIFCTR_RFWM_MASK GENMASK(15, 13) /* Receive FIFO Watermark */
152 #define SIFCTR_RFWM_1 (0 << 13) /* Transfer Request when 1 valid stages */
153 #define SIFCTR_RFWM_4 (1 << 13) /* Transfer Request when 4 valid stages */
154 #define SIFCTR_RFWM_8 (2 << 13) /* Transfer Request when 8 valid stages */
155 #define SIFCTR_RFWM_16 (3 << 13) /* Transfer Request when 16 valid stages */
156 #define SIFCTR_RFWM_32 (4 << 13) /* Transfer Request when 32 valid stages */
157 #define SIFCTR_RFWM_64 (5 << 13) /* Transfer Request when 64 valid stages */
158 #define SIFCTR_RFWM_128 (6 << 13) /* Transfer Request when 128 valid stages */
159 #define SIFCTR_RFWM_256 (7 << 13) /* Transfer Request when 256 valid stages */
160 #define SIFCTR_RFUA_MASK GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */
161 #define SIFCTR_RFUA_SHIFT 4
162 #define SIFCTR_RFUA(i) ((i) << SIFCTR_RFUA_SHIFT)
165 #define SISTR_TFEMP BIT(29) /* Transmit FIFO Empty */
166 #define SISTR_TDREQ BIT(28) /* Transmit Data Transfer Request */
167 #define SISTR_TEOF BIT(23) /* Frame Transmission End */
168 #define SISTR_TFSERR BIT(21) /* Transmit Frame Synchronization Error */
169 #define SISTR_TFOVF BIT(20) /* Transmit FIFO Overflow */
170 #define SISTR_TFUDF BIT(19) /* Transmit FIFO Underflow */
171 #define SISTR_RFFUL BIT(13) /* Receive FIFO Full */
172 #define SISTR_RDREQ BIT(12) /* Receive Data Transfer Request */
173 #define SISTR_REOF BIT(7) /* Frame Reception End */
174 #define SISTR_RFSERR BIT(5) /* Receive Frame Synchronization Error */
175 #define SISTR_RFUDF BIT(4) /* Receive FIFO Underflow */
176 #define SISTR_RFOVF BIT(3) /* Receive FIFO Overflow */
179 #define SIIER_TDMAE BIT(31) /* Transmit Data DMA Transfer Req. Enable */
180 #define SIIER_TFEMPE BIT(29) /* Transmit FIFO Empty Enable */
181 #define SIIER_TDREQE BIT(28) /* Transmit Data Transfer Request Enable */
182 #define SIIER_TEOFE BIT(23) /* Frame Transmission End Enable */
183 #define SIIER_TFSERRE BIT(21) /* Transmit Frame Sync Error Enable */
184 #define SIIER_TFOVFE BIT(20) /* Transmit FIFO Overflow Enable */
185 #define SIIER_TFUDFE BIT(19) /* Transmit FIFO Underflow Enable */
186 #define SIIER_RDMAE BIT(15) /* Receive Data DMA Transfer Req. Enable */
187 #define SIIER_RFFULE BIT(13) /* Receive FIFO Full Enable */
188 #define SIIER_RDREQE BIT(12) /* Receive Data Transfer Request Enable */
189 #define SIIER_REOFE BIT(7) /* Frame Reception End Enable */
190 #define SIIER_RFSERRE BIT(5) /* Receive Frame Sync Error Enable */
191 #define SIIER_RFUDFE BIT(4) /* Receive FIFO Underflow Enable */
192 #define SIIER_RFOVFE BIT(3) /* Receive FIFO Overflow Enable */
195 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
200 return ioread16(p->mapbase + reg_offs);
202 return ioread32(p->mapbase + reg_offs);
206 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
212 iowrite16(value, p->mapbase + reg_offs);
215 iowrite32(value, p->mapbase + reg_offs);
220 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
223 u32 mask = clr | set;
226 data = sh_msiof_read(p, SICTR);
229 sh_msiof_write(p, SICTR, data);
231 return readl_poll_timeout_atomic(p->mapbase + SICTR, data,
232 (data & mask) == set, 1, 100);
235 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
237 struct sh_msiof_spi_priv *p = data;
239 /* just disable the interrupt and wake up */
240 sh_msiof_write(p, SIIER, 0);
246 static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
248 u32 mask = SICTR_TXRST | SICTR_RXRST;
251 data = sh_msiof_read(p, SICTR);
253 sh_msiof_write(p, SICTR, data);
255 readl_poll_timeout_atomic(p->mapbase + SICTR, data, !(data & mask), 1,
259 static const u32 sh_msiof_spi_div_array[] = {
260 SISCR_BRDV_DIV_1, SISCR_BRDV_DIV_2, SISCR_BRDV_DIV_4,
261 SISCR_BRDV_DIV_8, SISCR_BRDV_DIV_16, SISCR_BRDV_DIV_32,
264 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
265 unsigned long parent_rate, u32 spi_hz)
269 unsigned int div_pow = p->min_div_pow;
271 if (!spi_hz || !parent_rate) {
272 WARN(1, "Invalid clock rate parameters %lu and %u\n",
273 parent_rate, spi_hz);
277 div = DIV_ROUND_UP(parent_rate, spi_hz);
279 /* SISCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
280 if (!div_pow && div <= 32 && div > 2)
284 brps = (div + 1) >> div_pow;
288 for (; brps > 32; div_pow++)
289 brps = (brps + 1) >> 1;
291 /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
292 dev_err(&p->pdev->dev,
293 "Requested SPI transfer rate %d is too low\n", spi_hz);
298 scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps);
299 sh_msiof_write(p, SITSCR, scr);
300 if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
301 sh_msiof_write(p, SIRSCR, scr);
304 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
307 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
311 * b'011 (SYNCDL only) : 300
315 if (dtdl_or_syncdl % 100)
316 return dtdl_or_syncdl / 100 + 5;
318 return dtdl_or_syncdl / 100;
321 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
328 /* check if DTDL and SYNCDL is allowed value */
329 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
330 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
334 /* check if the sum of DTDL and SYNCDL becomes an integer value */
335 if ((p->info->dtdl + p->info->syncdl) % 100) {
336 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
340 val = sh_msiof_get_delay_bit(p->info->dtdl) << SIMDR1_DTDL_SHIFT;
341 val |= sh_msiof_get_delay_bit(p->info->syncdl) << SIMDR1_SYNCDL_SHIFT;
346 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
348 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
354 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
360 tmp = SIMDR1_SYNCMD_SPI | 1 << SIMDR1_FLD_SHIFT | SIMDR1_XXSTP;
361 tmp |= !cs_high << SIMDR1_SYNCAC_SHIFT;
362 tmp |= lsb_first << SIMDR1_BITLSB_SHIFT;
363 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
364 if (spi_controller_is_slave(p->ctlr)) {
365 sh_msiof_write(p, SITMDR1, tmp | SITMDR1_PCON);
367 sh_msiof_write(p, SITMDR1,
368 tmp | SIMDR1_TRMD | SITMDR1_PCON |
369 (ss < MAX_SS ? ss : 0) << SITMDR1_SYNCCH_SHIFT);
371 if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) {
372 /* These bits are reserved if RX needs TX */
375 sh_msiof_write(p, SIRMDR1, tmp);
378 tmp |= SICTR_TSCKIZ_SCK | cpol << SICTR_TSCKIZ_POL_SHIFT;
379 tmp |= SICTR_RSCKIZ_SCK | cpol << SICTR_RSCKIZ_POL_SHIFT;
383 tmp |= edge << SICTR_TEDG_SHIFT;
384 tmp |= edge << SICTR_REDG_SHIFT;
385 tmp |= tx_hi_z ? SICTR_TXDIZ_HIZ : SICTR_TXDIZ_LOW;
386 sh_msiof_write(p, SICTR, tmp);
389 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
390 const void *tx_buf, void *rx_buf,
393 u32 dr2 = SIMDR2_BITLEN1(bits) | SIMDR2_WDLEN1(words);
395 if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
396 sh_msiof_write(p, SITMDR2, dr2);
398 sh_msiof_write(p, SITMDR2, dr2 | SIMDR2_GRPMASK1);
401 sh_msiof_write(p, SIRMDR2, dr2);
404 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
406 sh_msiof_write(p, SISTR,
407 sh_msiof_read(p, SISTR) & ~(SISTR_TDREQ | SISTR_RDREQ));
410 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
411 const void *tx_buf, int words, int fs)
413 const u8 *buf_8 = tx_buf;
416 for (k = 0; k < words; k++)
417 sh_msiof_write(p, SITFDR, buf_8[k] << fs);
420 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
421 const void *tx_buf, int words, int fs)
423 const u16 *buf_16 = tx_buf;
426 for (k = 0; k < words; k++)
427 sh_msiof_write(p, SITFDR, buf_16[k] << fs);
430 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
431 const void *tx_buf, int words, int fs)
433 const u16 *buf_16 = tx_buf;
436 for (k = 0; k < words; k++)
437 sh_msiof_write(p, SITFDR, get_unaligned(&buf_16[k]) << fs);
440 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
441 const void *tx_buf, int words, int fs)
443 const u32 *buf_32 = tx_buf;
446 for (k = 0; k < words; k++)
447 sh_msiof_write(p, SITFDR, buf_32[k] << fs);
450 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
451 const void *tx_buf, int words, int fs)
453 const u32 *buf_32 = tx_buf;
456 for (k = 0; k < words; k++)
457 sh_msiof_write(p, SITFDR, get_unaligned(&buf_32[k]) << fs);
460 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
461 const void *tx_buf, int words, int fs)
463 const u32 *buf_32 = tx_buf;
466 for (k = 0; k < words; k++)
467 sh_msiof_write(p, SITFDR, swab32(buf_32[k] << fs));
470 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
471 const void *tx_buf, int words, int fs)
473 const u32 *buf_32 = tx_buf;
476 for (k = 0; k < words; k++)
477 sh_msiof_write(p, SITFDR, swab32(get_unaligned(&buf_32[k]) << fs));
480 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
481 void *rx_buf, int words, int fs)
486 for (k = 0; k < words; k++)
487 buf_8[k] = sh_msiof_read(p, SIRFDR) >> fs;
490 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
491 void *rx_buf, int words, int fs)
493 u16 *buf_16 = rx_buf;
496 for (k = 0; k < words; k++)
497 buf_16[k] = sh_msiof_read(p, SIRFDR) >> fs;
500 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
501 void *rx_buf, int words, int fs)
503 u16 *buf_16 = rx_buf;
506 for (k = 0; k < words; k++)
507 put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_16[k]);
510 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
511 void *rx_buf, int words, int fs)
513 u32 *buf_32 = rx_buf;
516 for (k = 0; k < words; k++)
517 buf_32[k] = sh_msiof_read(p, SIRFDR) >> fs;
520 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
521 void *rx_buf, int words, int fs)
523 u32 *buf_32 = rx_buf;
526 for (k = 0; k < words; k++)
527 put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_32[k]);
530 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
531 void *rx_buf, int words, int fs)
533 u32 *buf_32 = rx_buf;
536 for (k = 0; k < words; k++)
537 buf_32[k] = swab32(sh_msiof_read(p, SIRFDR) >> fs);
540 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
541 void *rx_buf, int words, int fs)
543 u32 *buf_32 = rx_buf;
546 for (k = 0; k < words; k++)
547 put_unaligned(swab32(sh_msiof_read(p, SIRFDR) >> fs), &buf_32[k]);
550 static int sh_msiof_spi_setup(struct spi_device *spi)
552 struct sh_msiof_spi_priv *p =
553 spi_controller_get_devdata(spi->controller);
556 if (spi->cs_gpiod || spi_controller_is_slave(p->ctlr))
559 if (p->native_cs_inited &&
560 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
563 /* Configure native chip select mode/polarity early */
564 clr = SIMDR1_SYNCMD_MASK;
565 set = SIMDR1_SYNCMD_SPI;
566 if (spi->mode & SPI_CS_HIGH)
567 clr |= BIT(SIMDR1_SYNCAC_SHIFT);
569 set |= BIT(SIMDR1_SYNCAC_SHIFT);
570 pm_runtime_get_sync(&p->pdev->dev);
571 tmp = sh_msiof_read(p, SITMDR1) & ~clr;
572 sh_msiof_write(p, SITMDR1, tmp | set | SIMDR1_TRMD | SITMDR1_PCON);
573 tmp = sh_msiof_read(p, SIRMDR1) & ~clr;
574 sh_msiof_write(p, SIRMDR1, tmp | set);
575 pm_runtime_put(&p->pdev->dev);
576 p->native_cs_high = spi->mode & SPI_CS_HIGH;
577 p->native_cs_inited = true;
581 static int sh_msiof_prepare_message(struct spi_controller *ctlr,
582 struct spi_message *msg)
584 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
585 const struct spi_device *spi = msg->spi;
588 /* Configure pins before asserting CS */
590 ss = ctlr->unused_native_cs;
591 cs_high = p->native_cs_high;
593 ss = spi->chip_select;
594 cs_high = !!(spi->mode & SPI_CS_HIGH);
596 sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL),
597 !!(spi->mode & SPI_CPHA),
598 !!(spi->mode & SPI_3WIRE),
599 !!(spi->mode & SPI_LSB_FIRST), cs_high);
603 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
605 bool slave = spi_controller_is_slave(p->ctlr);
608 /* setup clock and rx/tx signals */
610 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TSCKE);
612 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_RXE);
614 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TXE);
616 /* start by setting frame bit */
618 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TFSE);
623 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
625 bool slave = spi_controller_is_slave(p->ctlr);
628 /* shut down frame, rx/tx and clock signals */
630 ret = sh_msiof_modify_ctr_wait(p, SICTR_TFSE, 0);
632 ret = sh_msiof_modify_ctr_wait(p, SICTR_TXE, 0);
634 ret = sh_msiof_modify_ctr_wait(p, SICTR_RXE, 0);
636 ret = sh_msiof_modify_ctr_wait(p, SICTR_TSCKE, 0);
641 static int sh_msiof_slave_abort(struct spi_controller *ctlr)
643 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
645 p->slave_aborted = true;
647 complete(&p->done_txdma);
651 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
652 struct completion *x)
654 if (spi_controller_is_slave(p->ctlr)) {
655 if (wait_for_completion_interruptible(x) ||
657 dev_dbg(&p->pdev->dev, "interrupted\n");
661 if (!wait_for_completion_timeout(x, HZ)) {
662 dev_err(&p->pdev->dev, "timeout\n");
670 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
671 void (*tx_fifo)(struct sh_msiof_spi_priv *,
672 const void *, int, int),
673 void (*rx_fifo)(struct sh_msiof_spi_priv *,
675 const void *tx_buf, void *rx_buf,
681 /* limit maximum word transfer to rx/tx fifo size */
683 words = min_t(int, words, p->tx_fifo_size);
685 words = min_t(int, words, p->rx_fifo_size);
687 /* the fifo contents need shifting */
688 fifo_shift = 32 - bits;
690 /* default FIFO watermarks for PIO */
691 sh_msiof_write(p, SIFCTR, 0);
693 /* setup msiof transfer mode registers */
694 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
695 sh_msiof_write(p, SIIER, SIIER_TEOFE | SIIER_REOFE);
699 tx_fifo(p, tx_buf, words, fifo_shift);
701 reinit_completion(&p->done);
702 p->slave_aborted = false;
704 ret = sh_msiof_spi_start(p, rx_buf);
706 dev_err(&p->pdev->dev, "failed to start hardware\n");
710 /* wait for tx fifo to be emptied / rx fifo to be filled */
711 ret = sh_msiof_wait_for_completion(p, &p->done);
717 rx_fifo(p, rx_buf, words, fifo_shift);
719 /* clear status bits */
720 sh_msiof_reset_str(p);
722 ret = sh_msiof_spi_stop(p, rx_buf);
724 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
731 sh_msiof_reset_str(p);
732 sh_msiof_spi_stop(p, rx_buf);
734 sh_msiof_write(p, SIIER, 0);
738 static void sh_msiof_dma_complete(void *arg)
743 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
744 void *rx, unsigned int len)
747 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
751 /* First prepare and submit the DMA request(s), as this may fail */
753 ier_bits |= SIIER_RDREQE | SIIER_RDMAE;
754 desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx,
755 p->rx_dma_addr, len, DMA_DEV_TO_MEM,
756 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
760 desc_rx->callback = sh_msiof_dma_complete;
761 desc_rx->callback_param = &p->done;
762 cookie = dmaengine_submit(desc_rx);
763 if (dma_submit_error(cookie))
768 ier_bits |= SIIER_TDREQE | SIIER_TDMAE;
769 dma_sync_single_for_device(p->ctlr->dma_tx->device->dev,
770 p->tx_dma_addr, len, DMA_TO_DEVICE);
771 desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx,
772 p->tx_dma_addr, len, DMA_MEM_TO_DEV,
773 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
779 desc_tx->callback = sh_msiof_dma_complete;
780 desc_tx->callback_param = &p->done_txdma;
781 cookie = dmaengine_submit(desc_tx);
782 if (dma_submit_error(cookie)) {
788 /* 1 stage FIFO watermarks for DMA */
789 sh_msiof_write(p, SIFCTR, SIFCTR_TFWM_1 | SIFCTR_RFWM_1);
791 /* setup msiof transfer mode registers (32-bit words) */
792 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
794 sh_msiof_write(p, SIIER, ier_bits);
796 reinit_completion(&p->done);
798 reinit_completion(&p->done_txdma);
799 p->slave_aborted = false;
803 dma_async_issue_pending(p->ctlr->dma_rx);
805 dma_async_issue_pending(p->ctlr->dma_tx);
807 ret = sh_msiof_spi_start(p, rx);
809 dev_err(&p->pdev->dev, "failed to start hardware\n");
814 /* wait for tx DMA completion */
815 ret = sh_msiof_wait_for_completion(p, &p->done_txdma);
821 /* wait for rx DMA completion */
822 ret = sh_msiof_wait_for_completion(p, &p->done);
826 sh_msiof_write(p, SIIER, 0);
828 /* wait for tx fifo to be emptied */
829 sh_msiof_write(p, SIIER, SIIER_TEOFE);
830 ret = sh_msiof_wait_for_completion(p, &p->done);
835 /* clear status bits */
836 sh_msiof_reset_str(p);
838 ret = sh_msiof_spi_stop(p, rx);
840 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
845 dma_sync_single_for_cpu(p->ctlr->dma_rx->device->dev,
846 p->rx_dma_addr, len, DMA_FROM_DEVICE);
851 sh_msiof_reset_str(p);
852 sh_msiof_spi_stop(p, rx);
855 dmaengine_terminate_all(p->ctlr->dma_tx);
858 dmaengine_terminate_all(p->ctlr->dma_rx);
859 sh_msiof_write(p, SIIER, 0);
863 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
865 /* src or dst can be unaligned, but not both */
866 if ((unsigned long)src & 3) {
868 *dst++ = swab32(get_unaligned(src));
871 } else if ((unsigned long)dst & 3) {
873 put_unaligned(swab32(*src++), dst);
878 *dst++ = swab32(*src++);
882 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
884 /* src or dst can be unaligned, but not both */
885 if ((unsigned long)src & 3) {
887 *dst++ = swahw32(get_unaligned(src));
890 } else if ((unsigned long)dst & 3) {
892 put_unaligned(swahw32(*src++), dst);
897 *dst++ = swahw32(*src++);
901 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
903 memcpy(dst, src, words * 4);
906 static int sh_msiof_transfer_one(struct spi_controller *ctlr,
907 struct spi_device *spi,
908 struct spi_transfer *t)
910 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
911 void (*copy32)(u32 *, const u32 *, unsigned int);
912 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
913 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
914 const void *tx_buf = t->tx_buf;
915 void *rx_buf = t->rx_buf;
916 unsigned int len = t->len;
917 unsigned int bits = t->bits_per_word;
918 unsigned int bytes_per_word;
924 /* reset registers */
925 sh_msiof_spi_reset_regs(p);
927 /* setup clocks (clock already enabled in chipselect()) */
928 if (!spi_controller_is_slave(p->ctlr))
929 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
931 while (ctlr->dma_tx && len > 15) {
933 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
934 * words, with byte resp. word swapping.
939 l = min(round_down(len, 4), p->tx_fifo_size * 4);
941 l = min(round_down(len, 4), p->rx_fifo_size * 4);
944 copy32 = copy_bswap32;
945 } else if (bits <= 16) {
946 copy32 = copy_wswap32;
948 copy32 = copy_plain32;
952 copy32(p->tx_dma_page, tx_buf, l / 4);
954 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
955 if (ret == -EAGAIN) {
956 dev_warn_once(&p->pdev->dev,
957 "DMA not available, falling back to PIO\n");
964 copy32(rx_buf, p->rx_dma_page, l / 4);
975 if (bits <= 8 && len > 15) {
982 /* setup bytes per word and fifo read/write functions */
985 tx_fifo = sh_msiof_spi_write_fifo_8;
986 rx_fifo = sh_msiof_spi_read_fifo_8;
987 } else if (bits <= 16) {
989 if ((unsigned long)tx_buf & 0x01)
990 tx_fifo = sh_msiof_spi_write_fifo_16u;
992 tx_fifo = sh_msiof_spi_write_fifo_16;
994 if ((unsigned long)rx_buf & 0x01)
995 rx_fifo = sh_msiof_spi_read_fifo_16u;
997 rx_fifo = sh_msiof_spi_read_fifo_16;
1000 if ((unsigned long)tx_buf & 0x03)
1001 tx_fifo = sh_msiof_spi_write_fifo_s32u;
1003 tx_fifo = sh_msiof_spi_write_fifo_s32;
1005 if ((unsigned long)rx_buf & 0x03)
1006 rx_fifo = sh_msiof_spi_read_fifo_s32u;
1008 rx_fifo = sh_msiof_spi_read_fifo_s32;
1011 if ((unsigned long)tx_buf & 0x03)
1012 tx_fifo = sh_msiof_spi_write_fifo_32u;
1014 tx_fifo = sh_msiof_spi_write_fifo_32;
1016 if ((unsigned long)rx_buf & 0x03)
1017 rx_fifo = sh_msiof_spi_read_fifo_32u;
1019 rx_fifo = sh_msiof_spi_read_fifo_32;
1022 /* transfer in fifo sized chunks */
1023 words = len / bytes_per_word;
1026 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
1032 tx_buf += n * bytes_per_word;
1034 rx_buf += n * bytes_per_word;
1037 if (words == 0 && (len % bytes_per_word)) {
1038 words = len % bytes_per_word;
1039 bits = t->bits_per_word;
1041 tx_fifo = sh_msiof_spi_write_fifo_8;
1042 rx_fifo = sh_msiof_spi_read_fifo_8;
1049 static const struct sh_msiof_chipdata sh_data = {
1050 .bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32),
1057 static const struct sh_msiof_chipdata rcar_gen2_data = {
1058 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1059 SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1062 .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1066 static const struct sh_msiof_chipdata rcar_gen3_data = {
1067 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1068 SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1071 .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1075 static const struct sh_msiof_chipdata rcar_r8a7795_data = {
1076 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1077 SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1080 .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1082 .flags = SH_MSIOF_FLAG_FIXED_DTDL_200,
1085 static const struct of_device_id sh_msiof_match[] = {
1086 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1087 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
1088 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data },
1089 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
1090 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
1091 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
1092 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
1093 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
1094 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1095 { .compatible = "renesas,msiof-r8a7795", .data = &rcar_r8a7795_data },
1096 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
1097 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1098 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
1101 MODULE_DEVICE_TABLE(of, sh_msiof_match);
1104 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1106 struct sh_msiof_spi_info *info;
1107 struct device_node *np = dev->of_node;
1110 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
1114 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
1117 /* Parse the MSIOF properties */
1118 if (info->mode == MSIOF_SPI_MASTER)
1119 of_property_read_u32(np, "num-cs", &num_cs);
1120 of_property_read_u32(np, "renesas,tx-fifo-size",
1121 &info->tx_fifo_override);
1122 of_property_read_u32(np, "renesas,rx-fifo-size",
1123 &info->rx_fifo_override);
1124 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1125 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1127 info->num_chipselect = num_cs;
1132 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1138 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1139 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1141 dma_cap_mask_t mask;
1142 struct dma_chan *chan;
1143 struct dma_slave_config cfg;
1147 dma_cap_set(DMA_SLAVE, mask);
1149 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1150 (void *)(unsigned long)id, dev,
1151 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1153 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1157 memset(&cfg, 0, sizeof(cfg));
1158 cfg.direction = dir;
1159 if (dir == DMA_MEM_TO_DEV) {
1160 cfg.dst_addr = port_addr;
1161 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1163 cfg.src_addr = port_addr;
1164 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1167 ret = dmaengine_slave_config(chan, &cfg);
1169 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1170 dma_release_channel(chan);
1177 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1179 struct platform_device *pdev = p->pdev;
1180 struct device *dev = &pdev->dev;
1181 const struct sh_msiof_spi_info *info = p->info;
1182 unsigned int dma_tx_id, dma_rx_id;
1183 const struct resource *res;
1184 struct spi_controller *ctlr;
1185 struct device *tx_dev, *rx_dev;
1188 /* In the OF case we will get the slave IDs from the DT */
1191 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1192 dma_tx_id = info->dma_tx_id;
1193 dma_rx_id = info->dma_rx_id;
1195 /* The driver assumes no error */
1199 /* The DMA engine uses the second register set, if present */
1200 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1202 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1205 ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1206 dma_tx_id, res->start + SITFDR);
1210 ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1211 dma_rx_id, res->start + SIRFDR);
1215 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1216 if (!p->tx_dma_page)
1219 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1220 if (!p->rx_dma_page)
1223 tx_dev = ctlr->dma_tx->device->dev;
1224 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1226 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1229 rx_dev = ctlr->dma_rx->device->dev;
1230 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1232 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1235 dev_info(dev, "DMA available");
1239 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1241 free_page((unsigned long)p->rx_dma_page);
1243 free_page((unsigned long)p->tx_dma_page);
1245 dma_release_channel(ctlr->dma_rx);
1247 dma_release_channel(ctlr->dma_tx);
1248 ctlr->dma_tx = NULL;
1252 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1254 struct spi_controller *ctlr = p->ctlr;
1259 dma_unmap_single(ctlr->dma_rx->device->dev, p->rx_dma_addr, PAGE_SIZE,
1261 dma_unmap_single(ctlr->dma_tx->device->dev, p->tx_dma_addr, PAGE_SIZE,
1263 free_page((unsigned long)p->rx_dma_page);
1264 free_page((unsigned long)p->tx_dma_page);
1265 dma_release_channel(ctlr->dma_rx);
1266 dma_release_channel(ctlr->dma_tx);
1269 static int sh_msiof_spi_probe(struct platform_device *pdev)
1271 struct spi_controller *ctlr;
1272 const struct sh_msiof_chipdata *chipdata;
1273 struct sh_msiof_spi_info *info;
1274 struct sh_msiof_spi_priv *p;
1278 chipdata = of_device_get_match_data(&pdev->dev);
1280 info = sh_msiof_spi_parse_dt(&pdev->dev);
1282 chipdata = (const void *)pdev->id_entry->driver_data;
1283 info = dev_get_platdata(&pdev->dev);
1287 dev_err(&pdev->dev, "failed to obtain device info\n");
1291 if (chipdata->flags & SH_MSIOF_FLAG_FIXED_DTDL_200)
1294 if (info->mode == MSIOF_SPI_SLAVE)
1295 ctlr = spi_alloc_slave(&pdev->dev,
1296 sizeof(struct sh_msiof_spi_priv));
1298 ctlr = spi_alloc_master(&pdev->dev,
1299 sizeof(struct sh_msiof_spi_priv));
1303 p = spi_controller_get_devdata(ctlr);
1305 platform_set_drvdata(pdev, p);
1308 p->min_div_pow = chipdata->min_div_pow;
1310 init_completion(&p->done);
1311 init_completion(&p->done_txdma);
1313 p->clk = devm_clk_get(&pdev->dev, NULL);
1314 if (IS_ERR(p->clk)) {
1315 dev_err(&pdev->dev, "cannot get clock\n");
1316 ret = PTR_ERR(p->clk);
1320 i = platform_get_irq(pdev, 0);
1326 p->mapbase = devm_platform_ioremap_resource(pdev, 0);
1327 if (IS_ERR(p->mapbase)) {
1328 ret = PTR_ERR(p->mapbase);
1332 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1333 dev_name(&pdev->dev), p);
1335 dev_err(&pdev->dev, "unable to request irq\n");
1340 pm_runtime_enable(&pdev->dev);
1342 /* Platform data may override FIFO sizes */
1343 p->tx_fifo_size = chipdata->tx_fifo_size;
1344 p->rx_fifo_size = chipdata->rx_fifo_size;
1345 if (p->info->tx_fifo_override)
1346 p->tx_fifo_size = p->info->tx_fifo_override;
1347 if (p->info->rx_fifo_override)
1348 p->rx_fifo_size = p->info->rx_fifo_override;
1350 /* init controller code */
1351 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1352 ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1353 ctlr->flags = chipdata->ctlr_flags;
1354 ctlr->bus_num = pdev->id;
1355 ctlr->num_chipselect = p->info->num_chipselect;
1356 ctlr->dev.of_node = pdev->dev.of_node;
1357 ctlr->setup = sh_msiof_spi_setup;
1358 ctlr->prepare_message = sh_msiof_prepare_message;
1359 ctlr->slave_abort = sh_msiof_slave_abort;
1360 ctlr->bits_per_word_mask = chipdata->bits_per_word_mask;
1361 ctlr->auto_runtime_pm = true;
1362 ctlr->transfer_one = sh_msiof_transfer_one;
1363 ctlr->use_gpio_descriptors = true;
1364 ctlr->max_native_cs = MAX_SS;
1366 ret = sh_msiof_request_dma(p);
1368 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1370 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1372 dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1379 sh_msiof_release_dma(p);
1380 pm_runtime_disable(&pdev->dev);
1382 spi_controller_put(ctlr);
1386 static int sh_msiof_spi_remove(struct platform_device *pdev)
1388 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1390 sh_msiof_release_dma(p);
1391 pm_runtime_disable(&pdev->dev);
1395 static const struct platform_device_id spi_driver_ids[] = {
1396 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1399 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1401 #ifdef CONFIG_PM_SLEEP
1402 static int sh_msiof_spi_suspend(struct device *dev)
1404 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
1406 return spi_controller_suspend(p->ctlr);
1409 static int sh_msiof_spi_resume(struct device *dev)
1411 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
1413 return spi_controller_resume(p->ctlr);
1416 static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
1417 sh_msiof_spi_resume);
1418 #define DEV_PM_OPS (&sh_msiof_spi_pm_ops)
1420 #define DEV_PM_OPS NULL
1421 #endif /* CONFIG_PM_SLEEP */
1423 static struct platform_driver sh_msiof_spi_drv = {
1424 .probe = sh_msiof_spi_probe,
1425 .remove = sh_msiof_spi_remove,
1426 .id_table = spi_driver_ids,
1428 .name = "spi_sh_msiof",
1430 .of_match_table = of_match_ptr(sh_msiof_match),
1433 module_platform_driver(sh_msiof_spi_drv);
1435 MODULE_DESCRIPTION("SuperH MSIOF SPI Controller Interface Driver");
1436 MODULE_AUTHOR("Magnus Damm");
1437 MODULE_LICENSE("GPL v2");
1438 MODULE_ALIAS("platform:spi_sh_msiof");