2 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 * Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
9 * General Purpose functions for the global management of the
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/param.h>
21 #include <linux/string.h>
22 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/delay.h>
27 #include <linux/ioport.h>
28 #include <linux/crc32.h>
29 #include <linux/mod_devicetable.h>
30 #include <linux/of_platform.h>
33 #include <asm/pgtable.h>
34 #include <soc/fsl/qe/immap_qe.h>
35 #include <soc/fsl/qe/qe.h>
37 #include <asm/rheap.h>
39 static void qe_snums_init(void);
40 static int qe_sdma_init(void);
42 static DEFINE_SPINLOCK(qe_lock);
43 DEFINE_SPINLOCK(cmxgcr_lock);
44 EXPORT_SYMBOL(cmxgcr_lock);
55 enum qe_snum_state state;
58 /* We allocate this here because it is used almost exclusively for
59 * the communication processor devices.
61 struct qe_immap __iomem *qe_immr;
62 EXPORT_SYMBOL(qe_immr);
64 static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
65 static unsigned int qe_num_of_snum;
67 static phys_addr_t qebase = -1;
69 phys_addr_t get_qe_base(void)
71 struct device_node *qe;
78 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
80 qe = of_find_node_by_type(NULL, "qe");
85 ret = of_address_to_resource(qe, 0, &res);
93 EXPORT_SYMBOL(get_qe_base);
98 qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
102 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
103 QE_CR_PROTOCOL_UNSPECIFIED, 0);
105 /* Reclaim the MURAM memory for our use. */
109 panic("sdma init failed!");
112 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
115 u8 mcn_shift = 0, dev_shift = 0;
118 spin_lock_irqsave(&qe_lock, flags);
119 if (cmd == QE_RESET) {
120 out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
122 if (cmd == QE_ASSIGN_PAGE) {
123 /* Here device is the SNUM, not sub-block */
124 dev_shift = QE_CR_SNUM_SHIFT;
125 } else if (cmd == QE_ASSIGN_RISC) {
126 /* Here device is the SNUM, and mcnProtocol is
127 * e_QeCmdRiscAssignment value */
128 dev_shift = QE_CR_SNUM_SHIFT;
129 mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
131 if (device == QE_CR_SUBBLOCK_USB)
132 mcn_shift = QE_CR_MCN_USB_SHIFT;
134 mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
137 out_be32(&qe_immr->cp.cecdr, cmd_input);
138 out_be32(&qe_immr->cp.cecr,
139 (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
140 mcn_protocol << mcn_shift));
143 /* wait for the QE_CR_FLG to clear */
144 ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
146 /* On timeout (e.g. failure), the expression will be false (ret == 0),
147 otherwise it will be true (ret == 1). */
148 spin_unlock_irqrestore(&qe_lock, flags);
152 EXPORT_SYMBOL(qe_issue_cmd);
154 /* Set a baud rate generator. This needs lots of work. There are
155 * 16 BRGs, which can be connected to the QE channels or output
156 * as clocks. The BRGs are in two different block of internal
157 * memory mapped space.
158 * The BRG clock is the QE clock divided by 2.
159 * It was set up long ago during the initial boot phase and is
161 * Baud rate clocks are zero-based in the driver code (as that maps
162 * to port numbers). Documentation uses 1-based numbering.
164 static unsigned int brg_clk = 0;
166 #define CLK_GRAN (1000)
167 #define CLK_GRAN_LIMIT (5)
169 unsigned int qe_get_brg_clk(void)
171 struct device_node *qe;
179 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
181 qe = of_find_node_by_type(NULL, "qe");
186 prop = of_get_property(qe, "brg-frequency", &size);
187 if (prop && size == sizeof(*prop))
192 /* round this if near to a multiple of CLK_GRAN */
193 mod = brg_clk % CLK_GRAN;
195 if (mod < CLK_GRAN_LIMIT)
197 else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
198 brg_clk += CLK_GRAN - mod;
203 EXPORT_SYMBOL(qe_get_brg_clk);
205 /* Program the BRG to the given sampling rate and multiplier
207 * @brg: the BRG, QE_BRG1 - QE_BRG16
208 * @rate: the desired sampling rate
209 * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
210 * GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
211 * then 'multiplier' should be 8.
213 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
215 u32 divisor, tempval;
218 if ((brg < QE_BRG1) || (brg > QE_BRG16))
221 divisor = qe_get_brg_clk() / (rate * multiplier);
223 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
224 div16 = QE_BRGC_DIV16;
228 /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
229 that the BRG divisor must be even if you're not using divide-by-16
231 if (!div16 && (divisor & 1) && (divisor > 3))
234 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
235 QE_BRGC_ENABLE | div16;
237 out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
241 EXPORT_SYMBOL(qe_setbrg);
243 /* Convert a string to a QE clock source enum
245 * This function takes a string, typically from a property in the device
246 * tree, and returns the corresponding "enum qe_clock" value.
248 enum qe_clock qe_clock_source(const char *source)
252 if (strcasecmp(source, "none") == 0)
255 if (strcmp(source, "tsync_pin") == 0)
258 if (strcmp(source, "rsync_pin") == 0)
261 if (strncasecmp(source, "brg", 3) == 0) {
262 i = simple_strtoul(source + 3, NULL, 10);
263 if ((i >= 1) && (i <= 16))
264 return (QE_BRG1 - 1) + i;
269 if (strncasecmp(source, "clk", 3) == 0) {
270 i = simple_strtoul(source + 3, NULL, 10);
271 if ((i >= 1) && (i <= 24))
272 return (QE_CLK1 - 1) + i;
279 EXPORT_SYMBOL(qe_clock_source);
281 /* Initialize SNUMs (thread serial numbers) according to
282 * QE Module Control chapter, SNUM table
284 static void qe_snums_init(void)
287 static const u8 snum_init_76[] = {
288 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
289 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
290 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
291 0xD8, 0xD9, 0xE8, 0xE9, 0x44, 0x45, 0x4C, 0x4D,
292 0x54, 0x55, 0x5C, 0x5D, 0x64, 0x65, 0x6C, 0x6D,
293 0x74, 0x75, 0x7C, 0x7D, 0x84, 0x85, 0x8C, 0x8D,
294 0x94, 0x95, 0x9C, 0x9D, 0xA4, 0xA5, 0xAC, 0xAD,
295 0xB4, 0xB5, 0xBC, 0xBD, 0xC4, 0xC5, 0xCC, 0xCD,
296 0xD4, 0xD5, 0xDC, 0xDD, 0xE4, 0xE5, 0xEC, 0xED,
297 0xF4, 0xF5, 0xFC, 0xFD,
299 static const u8 snum_init_46[] = {
300 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
301 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
302 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
303 0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
304 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
305 0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
307 static const u8 *snum_init;
309 qe_num_of_snum = qe_get_num_of_snums();
311 if (qe_num_of_snum == 76)
312 snum_init = snum_init_76;
314 snum_init = snum_init_46;
316 for (i = 0; i < qe_num_of_snum; i++) {
317 snums[i].num = snum_init[i];
318 snums[i].state = QE_SNUM_STATE_FREE;
322 int qe_get_snum(void)
328 spin_lock_irqsave(&qe_lock, flags);
329 for (i = 0; i < qe_num_of_snum; i++) {
330 if (snums[i].state == QE_SNUM_STATE_FREE) {
331 snums[i].state = QE_SNUM_STATE_USED;
336 spin_unlock_irqrestore(&qe_lock, flags);
340 EXPORT_SYMBOL(qe_get_snum);
342 void qe_put_snum(u8 snum)
346 for (i = 0; i < qe_num_of_snum; i++) {
347 if (snums[i].num == snum) {
348 snums[i].state = QE_SNUM_STATE_FREE;
353 EXPORT_SYMBOL(qe_put_snum);
355 static int qe_sdma_init(void)
357 struct sdma __iomem *sdma = &qe_immr->sdma;
358 static unsigned long sdma_buf_offset = (unsigned long)-ENOMEM;
363 /* allocate 2 internal temporary buffers (512 bytes size each) for
365 if (IS_ERR_VALUE(sdma_buf_offset)) {
366 sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
367 if (IS_ERR_VALUE(sdma_buf_offset))
371 out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
372 out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
373 (0x1 << QE_SDMR_CEN_SHIFT)));
378 /* The maximum number of RISCs we support */
379 #define MAX_QE_RISC 4
381 /* Firmware information stored here for qe_get_firmware_info() */
382 static struct qe_firmware_info qe_firmware_info;
385 * Set to 1 if QE firmware has been uploaded, and therefore
386 * qe_firmware_info contains valid data.
388 static int qe_firmware_uploaded;
391 * Upload a QE microcode
393 * This function is a worker function for qe_upload_firmware(). It does
394 * the actual uploading of the microcode.
396 static void qe_upload_microcode(const void *base,
397 const struct qe_microcode *ucode)
399 const __be32 *code = base + be32_to_cpu(ucode->code_offset);
402 if (ucode->major || ucode->minor || ucode->revision)
403 printk(KERN_INFO "qe-firmware: "
404 "uploading microcode '%s' version %u.%u.%u\n",
405 ucode->id, ucode->major, ucode->minor, ucode->revision);
407 printk(KERN_INFO "qe-firmware: "
408 "uploading microcode '%s'\n", ucode->id);
410 /* Use auto-increment */
411 out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
412 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
414 for (i = 0; i < be32_to_cpu(ucode->count); i++)
415 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
417 /* Set I-RAM Ready Register */
418 out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
422 * Upload a microcode to the I-RAM at a specific address.
424 * See Documentation/powerpc/qe_firmware.txt for information on QE microcode
427 * Currently, only version 1 is supported, so the 'version' field must be
430 * The SOC model and revision are not validated, they are only displayed for
431 * informational purposes.
433 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
434 * all of the microcode structures, minus the CRC.
436 * 'length' is the size that the structure says it is, including the CRC.
438 int qe_upload_firmware(const struct qe_firmware *firmware)
443 size_t calc_size = sizeof(struct qe_firmware);
445 const struct qe_header *hdr;
448 printk(KERN_ERR "qe-firmware: invalid pointer\n");
452 hdr = &firmware->header;
453 length = be32_to_cpu(hdr->length);
455 /* Check the magic */
456 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
457 (hdr->magic[2] != 'F')) {
458 printk(KERN_ERR "qe-firmware: not a microcode\n");
462 /* Check the version */
463 if (hdr->version != 1) {
464 printk(KERN_ERR "qe-firmware: unsupported version\n");
468 /* Validate some of the fields */
469 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
470 printk(KERN_ERR "qe-firmware: invalid data\n");
474 /* Validate the length and check if there's a CRC */
475 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
477 for (i = 0; i < firmware->count; i++)
479 * For situations where the second RISC uses the same microcode
480 * as the first, the 'code_offset' and 'count' fields will be
481 * zero, so it's okay to add those.
483 calc_size += sizeof(__be32) *
484 be32_to_cpu(firmware->microcode[i].count);
486 /* Validate the length */
487 if (length != calc_size + sizeof(__be32)) {
488 printk(KERN_ERR "qe-firmware: invalid length\n");
492 /* Validate the CRC */
493 crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
494 if (crc != crc32(0, firmware, calc_size)) {
495 printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
500 * If the microcode calls for it, split the I-RAM.
502 if (!firmware->split)
503 setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
505 if (firmware->soc.model)
507 "qe-firmware: firmware '%s' for %u V%u.%u\n",
508 firmware->id, be16_to_cpu(firmware->soc.model),
509 firmware->soc.major, firmware->soc.minor);
511 printk(KERN_INFO "qe-firmware: firmware '%s'\n",
515 * The QE only supports one microcode per RISC, so clear out all the
516 * saved microcode information and put in the new.
518 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
519 strlcpy(qe_firmware_info.id, firmware->id, sizeof(qe_firmware_info.id));
520 qe_firmware_info.extended_modes = firmware->extended_modes;
521 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
522 sizeof(firmware->vtraps));
524 /* Loop through each microcode. */
525 for (i = 0; i < firmware->count; i++) {
526 const struct qe_microcode *ucode = &firmware->microcode[i];
528 /* Upload a microcode if it's present */
529 if (ucode->code_offset)
530 qe_upload_microcode(firmware, ucode);
532 /* Program the traps for this processor */
533 for (j = 0; j < 16; j++) {
534 u32 trap = be32_to_cpu(ucode->traps[j]);
537 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
541 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
544 qe_firmware_uploaded = 1;
548 EXPORT_SYMBOL(qe_upload_firmware);
551 * Get info on the currently-loaded firmware
553 * This function also checks the device tree to see if the boot loader has
554 * uploaded a firmware already.
556 struct qe_firmware_info *qe_get_firmware_info(void)
558 static int initialized;
559 struct property *prop;
560 struct device_node *qe;
561 struct device_node *fw = NULL;
566 * If we haven't checked yet, and a driver hasn't uploaded a firmware
567 * yet, then check the device tree for information.
569 if (qe_firmware_uploaded)
570 return &qe_firmware_info;
578 * Newer device trees have an "fsl,qe" compatible property for the QE
579 * node, but we still need to support older device trees.
581 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
583 qe = of_find_node_by_type(NULL, "qe");
588 /* Find the 'firmware' child node */
589 for_each_child_of_node(qe, fw) {
590 if (strcmp(fw->name, "firmware") == 0)
596 /* Did we find the 'firmware' node? */
600 qe_firmware_uploaded = 1;
602 /* Copy the data into qe_firmware_info*/
603 sprop = of_get_property(fw, "id", NULL);
605 strlcpy(qe_firmware_info.id, sprop,
606 sizeof(qe_firmware_info.id));
608 prop = of_find_property(fw, "extended-modes", NULL);
609 if (prop && (prop->length == sizeof(u64))) {
610 const u64 *iprop = prop->value;
612 qe_firmware_info.extended_modes = *iprop;
615 prop = of_find_property(fw, "virtual-traps", NULL);
616 if (prop && (prop->length == 32)) {
617 const u32 *iprop = prop->value;
619 for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++)
620 qe_firmware_info.vtraps[i] = iprop[i];
625 return &qe_firmware_info;
627 EXPORT_SYMBOL(qe_get_firmware_info);
629 unsigned int qe_get_num_of_risc(void)
631 struct device_node *qe;
633 unsigned int num_of_risc = 0;
636 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
638 /* Older devices trees did not have an "fsl,qe"
639 * compatible property, so we need to look for
640 * the QE node by name.
642 qe = of_find_node_by_type(NULL, "qe");
647 prop = of_get_property(qe, "fsl,qe-num-riscs", &size);
648 if (prop && size == sizeof(*prop))
655 EXPORT_SYMBOL(qe_get_num_of_risc);
657 unsigned int qe_get_num_of_snums(void)
659 struct device_node *qe;
661 unsigned int num_of_snums;
664 num_of_snums = 28; /* The default number of snum for threads is 28 */
665 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
667 /* Older devices trees did not have an "fsl,qe"
668 * compatible property, so we need to look for
669 * the QE node by name.
671 qe = of_find_node_by_type(NULL, "qe");
676 prop = of_get_property(qe, "fsl,qe-num-snums", &size);
677 if (prop && size == sizeof(*prop)) {
678 num_of_snums = *prop;
679 if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) {
680 /* No QE ever has fewer than 28 SNUMs */
681 pr_err("QE: number of snum is invalid\n");
691 EXPORT_SYMBOL(qe_get_num_of_snums);
693 static int __init qe_init(void)
695 struct device_node *np;
697 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
704 subsys_initcall(qe_init);
706 #if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx)
707 static int qe_resume(struct platform_device *ofdev)
709 if (!qe_alive_during_sleep())
714 static int qe_probe(struct platform_device *ofdev)
719 static const struct of_device_id qe_ids[] = {
720 { .compatible = "fsl,qe", },
724 static struct platform_driver qe_driver = {
727 .of_match_table = qe_ids,
733 static int __init qe_drv_init(void)
735 return platform_driver_register(&qe_driver);
737 device_initcall(qe_drv_init);
738 #endif /* defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx) */