1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm self-authenticating modem subsystem remoteproc driver
5 * Copyright (C) 2016 Linaro Ltd.
6 * Copyright (C) 2014 Sony Mobile Communications AB
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/devcoredump.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_reserved_mem.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_domain.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regmap.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/remoteproc.h>
27 #include <linux/reset.h>
28 #include <linux/soc/qcom/mdt_loader.h>
29 #include <linux/iopoll.h>
30 #include <linux/slab.h>
32 #include "remoteproc_internal.h"
33 #include "qcom_common.h"
34 #include "qcom_pil_info.h"
35 #include "qcom_q6v5.h"
37 #include <linux/qcom_scm.h>
39 #define MPSS_CRASH_REASON_SMEM 421
41 #define MBA_LOG_SIZE SZ_4K
43 /* RMB Status Register Values */
44 #define RMB_PBL_SUCCESS 0x1
46 #define RMB_MBA_XPU_UNLOCKED 0x1
47 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2
48 #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3
49 #define RMB_MBA_AUTH_COMPLETE 0x4
51 /* PBL/MBA interface registers */
52 #define RMB_MBA_IMAGE_REG 0x00
53 #define RMB_PBL_STATUS_REG 0x04
54 #define RMB_MBA_COMMAND_REG 0x08
55 #define RMB_MBA_STATUS_REG 0x0C
56 #define RMB_PMI_META_DATA_REG 0x10
57 #define RMB_PMI_CODE_START_REG 0x14
58 #define RMB_PMI_CODE_LENGTH_REG 0x18
59 #define RMB_MBA_MSS_STATUS 0x40
60 #define RMB_MBA_ALT_RESET 0x44
62 #define RMB_CMD_META_DATA_READY 0x1
63 #define RMB_CMD_LOAD_READY 0x2
65 /* QDSP6SS Register Offsets */
66 #define QDSP6SS_RESET_REG 0x014
67 #define QDSP6SS_GFMUX_CTL_REG 0x020
68 #define QDSP6SS_PWR_CTL_REG 0x030
69 #define QDSP6SS_MEM_PWR_CTL 0x0B0
70 #define QDSP6V6SS_MEM_PWR_CTL 0x034
71 #define QDSP6SS_STRAP_ACC 0x110
73 /* AXI Halt Register Offsets */
74 #define AXI_HALTREQ_REG 0x0
75 #define AXI_HALTACK_REG 0x4
76 #define AXI_IDLE_REG 0x8
77 #define AXI_GATING_VALID_OVERRIDE BIT(0)
79 #define HALT_ACK_TIMEOUT_US 100000
82 #define Q6SS_STOP_CORE BIT(0)
83 #define Q6SS_CORE_ARES BIT(1)
84 #define Q6SS_BUS_ARES_ENABLE BIT(2)
87 #define Q6SS_CBCR_CLKEN BIT(0)
88 #define Q6SS_CBCR_CLKOFF BIT(31)
89 #define Q6SS_CBCR_TIMEOUT_US 200
91 /* QDSP6SS_GFMUX_CTL */
92 #define Q6SS_CLK_ENABLE BIT(1)
95 #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0)
96 #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1)
97 #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2)
98 #define Q6SS_L2TAG_SLP_NRET_N BIT(16)
99 #define Q6SS_ETB_SLP_NRET_N BIT(17)
100 #define Q6SS_L2DATA_STBY_N BIT(18)
101 #define Q6SS_SLP_RET_N BIT(19)
102 #define Q6SS_CLAMP_IO BIT(20)
103 #define QDSS_BHS_ON BIT(21)
104 #define QDSS_LDO_BYP BIT(22)
106 /* QDSP6v56 parameters */
107 #define QDSP6v56_LDO_BYP BIT(25)
108 #define QDSP6v56_BHS_ON BIT(24)
109 #define QDSP6v56_CLAMP_WL BIT(21)
110 #define QDSP6v56_CLAMP_QMC_MEM BIT(22)
111 #define QDSP6SS_XO_CBCR 0x0038
112 #define QDSP6SS_ACC_OVERRIDE_VAL 0x20
114 /* QDSP6v65 parameters */
115 #define QDSP6SS_CORE_CBCR 0x20
116 #define QDSP6SS_SLEEP 0x3C
117 #define QDSP6SS_BOOT_CORE_START 0x400
118 #define QDSP6SS_BOOT_CMD 0x404
119 #define BOOT_FSM_TIMEOUT 10000
122 struct regulator *reg;
127 struct qcom_mss_reg_res {
133 struct rproc_hexagon_res {
134 const char *hexagon_mba_image;
135 struct qcom_mss_reg_res *proxy_supply;
136 struct qcom_mss_reg_res *active_supply;
137 char **proxy_clk_names;
138 char **reset_clk_names;
139 char **active_clk_names;
140 char **active_pd_names;
141 char **proxy_pd_names;
143 bool need_mem_protection;
153 void __iomem *reg_base;
154 void __iomem *rmb_base;
156 struct regmap *halt_map;
157 struct regmap *conn_map;
164 struct reset_control *mss_restart;
165 struct reset_control *pdc_reset;
167 struct qcom_q6v5 q6v5;
169 struct clk *active_clks[8];
170 struct clk *reset_clks[4];
171 struct clk *proxy_clks[4];
172 struct device *active_pds[1];
173 struct device *proxy_pds[3];
174 int active_clk_count;
180 struct reg_info active_regs[1];
181 struct reg_info proxy_regs[3];
182 int active_reg_count;
185 bool dump_mba_loaded;
186 size_t current_dump_size;
187 size_t total_dump_size;
189 phys_addr_t mba_phys;
194 phys_addr_t mdata_phys;
197 phys_addr_t mpss_phys;
198 phys_addr_t mpss_reloc;
201 struct qcom_rproc_glink glink_subdev;
202 struct qcom_rproc_subdev smd_subdev;
203 struct qcom_rproc_ssr ssr_subdev;
204 struct qcom_sysmon *sysmon;
205 bool need_mem_protection;
211 const char *hexagon_mdt_image;
224 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
225 const struct qcom_mss_reg_res *reg_res)
233 for (i = 0; reg_res[i].supply; i++) {
234 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
235 if (IS_ERR(regs[i].reg)) {
236 rc = PTR_ERR(regs[i].reg);
237 if (rc != -EPROBE_DEFER)
238 dev_err(dev, "Failed to get %s\n regulator",
243 regs[i].uV = reg_res[i].uV;
244 regs[i].uA = reg_res[i].uA;
250 static int q6v5_regulator_enable(struct q6v5 *qproc,
251 struct reg_info *regs, int count)
256 for (i = 0; i < count; i++) {
257 if (regs[i].uV > 0) {
258 ret = regulator_set_voltage(regs[i].reg,
259 regs[i].uV, INT_MAX);
262 "Failed to request voltage for %d.\n",
268 if (regs[i].uA > 0) {
269 ret = regulator_set_load(regs[i].reg,
273 "Failed to set regulator mode\n");
278 ret = regulator_enable(regs[i].reg);
280 dev_err(qproc->dev, "Regulator enable failed\n");
287 for (; i >= 0; i--) {
289 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
292 regulator_set_load(regs[i].reg, 0);
294 regulator_disable(regs[i].reg);
300 static void q6v5_regulator_disable(struct q6v5 *qproc,
301 struct reg_info *regs, int count)
305 for (i = 0; i < count; i++) {
307 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
310 regulator_set_load(regs[i].reg, 0);
312 regulator_disable(regs[i].reg);
316 static int q6v5_clk_enable(struct device *dev,
317 struct clk **clks, int count)
322 for (i = 0; i < count; i++) {
323 rc = clk_prepare_enable(clks[i]);
325 dev_err(dev, "Clock enable failed\n");
332 for (i--; i >= 0; i--)
333 clk_disable_unprepare(clks[i]);
338 static void q6v5_clk_disable(struct device *dev,
339 struct clk **clks, int count)
343 for (i = 0; i < count; i++)
344 clk_disable_unprepare(clks[i]);
347 static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
353 for (i = 0; i < pd_count; i++) {
354 dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
355 ret = pm_runtime_get_sync(pds[i]);
357 pm_runtime_put_noidle(pds[i]);
358 dev_pm_genpd_set_performance_state(pds[i], 0);
359 goto unroll_pd_votes;
366 for (i--; i >= 0; i--) {
367 dev_pm_genpd_set_performance_state(pds[i], 0);
368 pm_runtime_put(pds[i]);
374 static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
379 for (i = 0; i < pd_count; i++) {
380 dev_pm_genpd_set_performance_state(pds[i], 0);
381 pm_runtime_put(pds[i]);
385 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
386 bool local, bool remote, phys_addr_t addr,
389 struct qcom_scm_vmperm next[2];
392 if (!qproc->need_mem_protection)
395 if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) &&
396 remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA)))
400 next[perms].vmid = QCOM_SCM_VMID_HLOS;
401 next[perms].perm = QCOM_SCM_PERM_RWX;
406 next[perms].vmid = QCOM_SCM_VMID_MSS_MSA;
407 next[perms].perm = QCOM_SCM_PERM_RW;
411 return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
412 current_perm, next, perms);
415 static void q6v5_debug_policy_load(struct q6v5 *qproc)
417 const struct firmware *dp_fw;
419 if (reject_firmware_direct(&dp_fw, "msadp", qproc->dev))
422 if (SZ_1M + dp_fw->size <= qproc->mba_size) {
423 memcpy(qproc->mba_region + SZ_1M, dp_fw->data, dp_fw->size);
424 qproc->dp_size = dp_fw->size;
427 release_firmware(dp_fw);
430 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
432 struct q6v5 *qproc = rproc->priv;
434 /* MBA is restricted to a maximum size of 1M */
435 if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
436 dev_err(qproc->dev, "MBA firmware load failed\n");
440 memcpy(qproc->mba_region, fw->data, fw->size);
441 q6v5_debug_policy_load(qproc);
446 static int q6v5_reset_assert(struct q6v5 *qproc)
450 if (qproc->has_alt_reset) {
451 reset_control_assert(qproc->pdc_reset);
452 ret = reset_control_reset(qproc->mss_restart);
453 reset_control_deassert(qproc->pdc_reset);
454 } else if (qproc->has_spare_reg) {
456 * When the AXI pipeline is being reset with the Q6 modem partly
457 * operational there is possibility of AXI valid signal to
458 * glitch, leading to spurious transactions and Q6 hangs. A work
459 * around is employed by asserting the AXI_GATING_VALID_OVERRIDE
460 * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE
461 * is withdrawn post MSS assert followed by a MSS deassert,
462 * while holding the PDC reset.
464 reset_control_assert(qproc->pdc_reset);
465 regmap_update_bits(qproc->conn_map, qproc->conn_box,
466 AXI_GATING_VALID_OVERRIDE, 1);
467 reset_control_assert(qproc->mss_restart);
468 reset_control_deassert(qproc->pdc_reset);
469 regmap_update_bits(qproc->conn_map, qproc->conn_box,
470 AXI_GATING_VALID_OVERRIDE, 0);
471 ret = reset_control_deassert(qproc->mss_restart);
473 ret = reset_control_assert(qproc->mss_restart);
479 static int q6v5_reset_deassert(struct q6v5 *qproc)
483 if (qproc->has_alt_reset) {
484 reset_control_assert(qproc->pdc_reset);
485 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
486 ret = reset_control_reset(qproc->mss_restart);
487 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
488 reset_control_deassert(qproc->pdc_reset);
489 } else if (qproc->has_spare_reg) {
490 ret = reset_control_reset(qproc->mss_restart);
492 ret = reset_control_deassert(qproc->mss_restart);
498 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
500 unsigned long timeout;
503 timeout = jiffies + msecs_to_jiffies(ms);
505 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
509 if (time_after(jiffies, timeout))
518 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
521 unsigned long timeout;
524 timeout = jiffies + msecs_to_jiffies(ms);
526 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
532 else if (status && val == status)
535 if (time_after(jiffies, timeout))
544 static void q6v5_dump_mba_logs(struct q6v5 *qproc)
546 struct rproc *rproc = qproc->rproc;
549 if (!qproc->has_mba_logs)
552 if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys,
556 data = vmalloc(MBA_LOG_SIZE);
560 memcpy(data, qproc->mba_region, MBA_LOG_SIZE);
561 dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL);
564 static int q6v5proc_reset(struct q6v5 *qproc)
570 if (qproc->version == MSS_SDM845) {
571 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
572 val |= Q6SS_CBCR_CLKEN;
573 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
575 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
576 val, !(val & Q6SS_CBCR_CLKOFF), 1,
577 Q6SS_CBCR_TIMEOUT_US);
579 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
583 /* De-assert QDSP6 stop core */
584 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
585 /* Trigger boot FSM */
586 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
588 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
589 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
591 dev_err(qproc->dev, "Boot FSM failed to complete.\n");
592 /* Reset the modem so that boot FSM is in reset state */
593 q6v5_reset_deassert(qproc);
598 } else if (qproc->version == MSS_SC7180) {
599 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
600 val |= Q6SS_CBCR_CLKEN;
601 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
603 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
604 val, !(val & Q6SS_CBCR_CLKOFF), 1,
605 Q6SS_CBCR_TIMEOUT_US);
607 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
611 /* Turn on the XO clock needed for PLL setup */
612 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
613 val |= Q6SS_CBCR_CLKEN;
614 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
616 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
617 val, !(val & Q6SS_CBCR_CLKOFF), 1,
618 Q6SS_CBCR_TIMEOUT_US);
620 dev_err(qproc->dev, "QDSP6SS XO clock timed out\n");
624 /* Configure Q6 core CBCR to auto-enable after reset sequence */
625 val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
626 val |= Q6SS_CBCR_CLKEN;
627 writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
629 /* De-assert the Q6 stop core signal */
630 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
632 /* Wait for 10 us for any staggering logic to settle */
633 usleep_range(10, 20);
635 /* Trigger the boot FSM to start the Q6 out-of-reset sequence */
636 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
638 /* Poll the MSS_STATUS for FSM completion */
639 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
640 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
642 dev_err(qproc->dev, "Boot FSM failed to complete.\n");
643 /* Reset the modem so that boot FSM is in reset state */
644 q6v5_reset_deassert(qproc);
648 } else if (qproc->version == MSS_MSM8996 ||
649 qproc->version == MSS_MSM8998) {
652 /* Override the ACC value if required */
653 writel(QDSP6SS_ACC_OVERRIDE_VAL,
654 qproc->reg_base + QDSP6SS_STRAP_ACC);
656 /* Assert resets, stop core */
657 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
658 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
659 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
661 /* BHS require xo cbcr to be enabled */
662 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
663 val |= Q6SS_CBCR_CLKEN;
664 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
666 /* Read CLKOFF bit to go low indicating CLK is enabled */
667 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
668 val, !(val & Q6SS_CBCR_CLKOFF), 1,
669 Q6SS_CBCR_TIMEOUT_US);
672 "xo cbcr enabling timed out (rc:%d)\n", ret);
675 /* Enable power block headswitch and wait for it to stabilize */
676 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
677 val |= QDSP6v56_BHS_ON;
678 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
679 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
682 /* Put LDO in bypass mode */
683 val |= QDSP6v56_LDO_BYP;
684 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
686 /* Deassert QDSP6 compiler memory clamp */
687 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
688 val &= ~QDSP6v56_CLAMP_QMC_MEM;
689 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
691 /* Deassert memory peripheral sleep and L2 memory standby */
692 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
693 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
695 /* Turn on L1, L2, ETB and JU memories 1 at a time */
696 if (qproc->version == MSS_MSM8996) {
697 mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
701 mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
704 val = readl(qproc->reg_base + mem_pwr_ctl);
705 for (; i >= 0; i--) {
707 writel(val, qproc->reg_base + mem_pwr_ctl);
709 * Read back value to ensure the write is done then
710 * wait for 1us for both memory peripheral and data
713 val |= readl(qproc->reg_base + mem_pwr_ctl);
716 /* Remove word line clamp */
717 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
718 val &= ~QDSP6v56_CLAMP_WL;
719 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
721 /* Assert resets, stop core */
722 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
723 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
724 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
726 /* Enable power block headswitch and wait for it to stabilize */
727 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
728 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
729 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
730 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
733 * Turn on memories. L2 banks should be done individually
734 * to minimize inrush current.
736 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
737 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
738 Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
739 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
740 val |= Q6SS_L2DATA_SLP_NRET_N_2;
741 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
742 val |= Q6SS_L2DATA_SLP_NRET_N_1;
743 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
744 val |= Q6SS_L2DATA_SLP_NRET_N_0;
745 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
747 /* Remove IO clamp */
748 val &= ~Q6SS_CLAMP_IO;
749 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
751 /* Bring core out of reset */
752 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
753 val &= ~Q6SS_CORE_ARES;
754 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
756 /* Turn on core clock */
757 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
758 val |= Q6SS_CLK_ENABLE;
759 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
761 /* Start core execution */
762 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
763 val &= ~Q6SS_STOP_CORE;
764 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
767 /* Wait for PBL status */
768 ret = q6v5_rmb_pbl_wait(qproc, 1000);
769 if (ret == -ETIMEDOUT) {
770 dev_err(qproc->dev, "PBL boot timed out\n");
771 } else if (ret != RMB_PBL_SUCCESS) {
772 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
781 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
782 struct regmap *halt_map,
788 /* Check if we're already idle */
789 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
793 /* Assert halt request */
794 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
797 regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val,
798 val, 1000, HALT_ACK_TIMEOUT_US);
800 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
802 dev_err(qproc->dev, "port failed halt\n");
804 /* Clear halt request (port will remain halted until reset) */
805 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
808 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
810 unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
819 metadata = qcom_mdt_read_metadata(fw, &size);
820 if (IS_ERR(metadata))
821 return PTR_ERR(metadata);
823 if (qproc->mdata_phys) {
824 if (size > qproc->mdata_size) {
826 dev_err(qproc->dev, "metadata size outside memory range\n");
830 phys = qproc->mdata_phys;
831 ptr = memremap(qproc->mdata_phys, size, MEMREMAP_WC);
834 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
835 &qproc->mdata_phys, size);
839 ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
842 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
847 memcpy(ptr, metadata, size);
849 if (qproc->mdata_phys)
852 /* Hypervisor mapping to access metadata by modem */
853 mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
854 ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true,
858 "assigning Q6 access to metadata failed: %d\n", ret);
863 writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
864 writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
866 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
867 if (ret == -ETIMEDOUT)
868 dev_err(qproc->dev, "MPSS header authentication timed out\n");
870 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
872 /* Metadata authentication done, remove modem access */
873 xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false,
877 "mdt buffer not reclaimed system may become unstable\n");
880 if (!qproc->mdata_phys)
881 dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
885 return ret < 0 ? ret : 0;
888 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
890 if (phdr->p_type != PT_LOAD)
893 if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
902 static int q6v5_mba_load(struct q6v5 *qproc)
906 bool mba_load_err = false;
908 qcom_q6v5_prepare(&qproc->q6v5);
910 ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count);
912 dev_err(qproc->dev, "failed to enable active power domains\n");
916 ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
918 dev_err(qproc->dev, "failed to enable proxy power domains\n");
919 goto disable_active_pds;
922 ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
923 qproc->proxy_reg_count);
925 dev_err(qproc->dev, "failed to enable proxy supplies\n");
926 goto disable_proxy_pds;
929 ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
930 qproc->proxy_clk_count);
932 dev_err(qproc->dev, "failed to enable proxy clocks\n");
933 goto disable_proxy_reg;
936 ret = q6v5_regulator_enable(qproc, qproc->active_regs,
937 qproc->active_reg_count);
939 dev_err(qproc->dev, "failed to enable supplies\n");
940 goto disable_proxy_clk;
943 ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
944 qproc->reset_clk_count);
946 dev_err(qproc->dev, "failed to enable reset clocks\n");
950 ret = q6v5_reset_deassert(qproc);
952 dev_err(qproc->dev, "failed to deassert mss restart\n");
953 goto disable_reset_clks;
956 ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
957 qproc->active_clk_count);
959 dev_err(qproc->dev, "failed to enable clocks\n");
964 * Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
965 * the Q6 access to this region.
967 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
968 qproc->mpss_phys, qproc->mpss_size);
970 dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret);
971 goto disable_active_clks;
974 /* Assign MBA image access in DDR to q6 */
975 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true,
976 qproc->mba_phys, qproc->mba_size);
979 "assigning Q6 access to mba memory failed: %d\n", ret);
980 goto disable_active_clks;
983 writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
984 if (qproc->dp_size) {
985 writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG);
986 writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
989 ret = q6v5proc_reset(qproc);
993 ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
994 if (ret == -ETIMEDOUT) {
995 dev_err(qproc->dev, "MBA boot timed out\n");
997 } else if (ret != RMB_MBA_XPU_UNLOCKED &&
998 ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
999 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
1001 goto halt_axi_ports;
1004 qproc->dump_mba_loaded = true;
1008 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1009 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1010 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1011 mba_load_err = true;
1013 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1014 false, qproc->mba_phys,
1016 if (xfermemop_ret) {
1018 "Failed to reclaim mba buffer, system may become unstable\n");
1019 } else if (mba_load_err) {
1020 q6v5_dump_mba_logs(qproc);
1023 disable_active_clks:
1024 q6v5_clk_disable(qproc->dev, qproc->active_clks,
1025 qproc->active_clk_count);
1027 q6v5_reset_assert(qproc);
1029 q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1030 qproc->reset_clk_count);
1032 q6v5_regulator_disable(qproc, qproc->active_regs,
1033 qproc->active_reg_count);
1035 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1036 qproc->proxy_clk_count);
1038 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1039 qproc->proxy_reg_count);
1041 q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1043 q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
1045 qcom_q6v5_unprepare(&qproc->q6v5);
1050 static void q6v5_mba_reclaim(struct q6v5 *qproc)
1055 qproc->dump_mba_loaded = false;
1058 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1059 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1060 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1061 if (qproc->version == MSS_MSM8996) {
1063 * To avoid high MX current during LPASS/MSS restart.
1065 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1066 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
1067 QDSP6v56_CLAMP_QMC_MEM;
1068 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1071 q6v5_reset_assert(qproc);
1073 q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1074 qproc->reset_clk_count);
1075 q6v5_clk_disable(qproc->dev, qproc->active_clks,
1076 qproc->active_clk_count);
1077 q6v5_regulator_disable(qproc, qproc->active_regs,
1078 qproc->active_reg_count);
1079 q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
1081 /* In case of failure or coredump scenario where reclaiming MBA memory
1082 * could not happen reclaim it here.
1084 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false,
1089 ret = qcom_q6v5_unprepare(&qproc->q6v5);
1091 q6v5_pds_disable(qproc, qproc->proxy_pds,
1092 qproc->proxy_pd_count);
1093 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1094 qproc->proxy_clk_count);
1095 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1096 qproc->proxy_reg_count);
1100 static int q6v5_reload_mba(struct rproc *rproc)
1102 struct q6v5 *qproc = rproc->priv;
1103 const struct firmware *fw;
1106 ret = reject_firmware(&fw, rproc->firmware, qproc->dev);
1110 q6v5_load(rproc, fw);
1111 ret = q6v5_mba_load(qproc);
1112 release_firmware(fw);
1117 static int q6v5_mpss_load(struct q6v5 *qproc)
1119 const struct elf32_phdr *phdrs;
1120 const struct elf32_phdr *phdr;
1121 const struct firmware *seg_fw;
1122 const struct firmware *fw;
1123 struct elf32_hdr *ehdr;
1124 phys_addr_t mpss_reloc;
1125 phys_addr_t boot_addr;
1126 phys_addr_t min_addr = PHYS_ADDR_MAX;
1127 phys_addr_t max_addr = 0;
1129 bool relocate = false;
1138 fw_name_len = strlen(qproc->hexagon_mdt_image);
1139 if (fw_name_len <= 4)
1142 fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
1146 ret = reject_firmware(&fw, fw_name, qproc->dev);
1148 dev_err(qproc->dev, "unable to load %s\n", fw_name);
1152 /* Initialize the RMB validator */
1153 writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1155 ret = q6v5_mpss_init_image(qproc, fw);
1157 goto release_firmware;
1159 ehdr = (struct elf32_hdr *)fw->data;
1160 phdrs = (struct elf32_phdr *)(ehdr + 1);
1162 for (i = 0; i < ehdr->e_phnum; i++) {
1165 if (!q6v5_phdr_valid(phdr))
1168 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
1171 if (phdr->p_paddr < min_addr)
1172 min_addr = phdr->p_paddr;
1174 if (phdr->p_paddr + phdr->p_memsz > max_addr)
1175 max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
1179 * In case of a modem subsystem restart on secure devices, the modem
1180 * memory can be reclaimed only after MBA is loaded.
1182 q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false,
1183 qproc->mpss_phys, qproc->mpss_size);
1185 /* Share ownership between Linux and MSS, during segment loading */
1186 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true,
1187 qproc->mpss_phys, qproc->mpss_size);
1190 "assigning Q6 access to mpss memory failed: %d\n", ret);
1192 goto release_firmware;
1195 mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
1196 qproc->mpss_reloc = mpss_reloc;
1197 /* Load firmware segments */
1198 for (i = 0; i < ehdr->e_phnum; i++) {
1201 if (!q6v5_phdr_valid(phdr))
1204 offset = phdr->p_paddr - mpss_reloc;
1205 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
1206 dev_err(qproc->dev, "segment outside memory range\n");
1208 goto release_firmware;
1211 if (phdr->p_filesz > phdr->p_memsz) {
1213 "refusing to load segment %d with p_filesz > p_memsz\n",
1216 goto release_firmware;
1219 ptr = memremap(qproc->mpss_phys + offset, phdr->p_memsz, MEMREMAP_WC);
1222 "unable to map memory region: %pa+%zx-%x\n",
1223 &qproc->mpss_phys, offset, phdr->p_memsz);
1224 goto release_firmware;
1227 if (phdr->p_filesz && phdr->p_offset < fw->size) {
1228 /* Firmware is large enough to be non-split */
1229 if (phdr->p_offset + phdr->p_filesz > fw->size) {
1231 "failed to load segment %d from truncated file %s\n",
1235 goto release_firmware;
1238 memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
1239 } else if (phdr->p_filesz) {
1240 /* Replace "xxx.xxx" with "xxx.bxx" */
1241 sprintf(fw_name + fw_name_len - 3, "b%02d", i);
1242 ret = reject_firmware_into_buf(&seg_fw, fw_name, qproc->dev,
1243 ptr, phdr->p_filesz);
1245 dev_err(qproc->dev, "failed to load %s\n", fw_name);
1247 goto release_firmware;
1250 if (seg_fw->size != phdr->p_filesz) {
1252 "failed to load segment %d from truncated file %s\n",
1255 release_firmware(seg_fw);
1257 goto release_firmware;
1260 release_firmware(seg_fw);
1263 if (phdr->p_memsz > phdr->p_filesz) {
1264 memset(ptr + phdr->p_filesz, 0,
1265 phdr->p_memsz - phdr->p_filesz);
1268 size += phdr->p_memsz;
1270 code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1272 boot_addr = relocate ? qproc->mpss_phys : min_addr;
1273 writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1274 writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1276 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1278 ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
1280 dev_err(qproc->dev, "MPSS authentication failed: %d\n",
1282 goto release_firmware;
1286 /* Transfer ownership of modem ddr region to q6 */
1287 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1288 qproc->mpss_phys, qproc->mpss_size);
1291 "assigning Q6 access to mpss memory failed: %d\n", ret);
1293 goto release_firmware;
1296 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
1297 if (ret == -ETIMEDOUT)
1298 dev_err(qproc->dev, "MPSS authentication timed out\n");
1300 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
1302 qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size);
1305 release_firmware(fw);
1309 return ret < 0 ? ret : 0;
1312 static void qcom_q6v5_dump_segment(struct rproc *rproc,
1313 struct rproc_dump_segment *segment,
1314 void *dest, size_t cp_offset, size_t size)
1317 struct q6v5 *qproc = rproc->priv;
1318 int offset = segment->da - qproc->mpss_reloc;
1321 /* Unlock mba before copying segments */
1322 if (!qproc->dump_mba_loaded) {
1323 ret = q6v5_reload_mba(rproc);
1325 /* Reset ownership back to Linux to copy segments */
1326 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1334 ptr = memremap(qproc->mpss_phys + offset + cp_offset, size, MEMREMAP_WC);
1337 memcpy(dest, ptr, size);
1340 memset(dest, 0xff, size);
1343 qproc->current_dump_size += size;
1345 /* Reclaim mba after copying segments */
1346 if (qproc->current_dump_size == qproc->total_dump_size) {
1347 if (qproc->dump_mba_loaded) {
1348 /* Try to reset ownership back to Q6 */
1349 q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1353 q6v5_mba_reclaim(qproc);
1358 static int q6v5_start(struct rproc *rproc)
1360 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1364 ret = q6v5_mba_load(qproc);
1368 dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n",
1369 qproc->dp_size ? "" : "out");
1371 ret = q6v5_mpss_load(qproc);
1375 ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
1376 if (ret == -ETIMEDOUT) {
1377 dev_err(qproc->dev, "start timed out\n");
1381 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1382 false, qproc->mba_phys,
1386 "Failed to reclaim mba buffer system may become unstable\n");
1388 /* Reset Dump Segment Mask */
1389 qproc->current_dump_size = 0;
1394 q6v5_mba_reclaim(qproc);
1395 q6v5_dump_mba_logs(qproc);
1400 static int q6v5_stop(struct rproc *rproc)
1402 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1405 ret = qcom_q6v5_request_stop(&qproc->q6v5);
1406 if (ret == -ETIMEDOUT)
1407 dev_err(qproc->dev, "timed out on wait\n");
1409 q6v5_mba_reclaim(qproc);
1414 static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
1415 const struct firmware *mba_fw)
1417 const struct firmware *fw;
1418 const struct elf32_phdr *phdrs;
1419 const struct elf32_phdr *phdr;
1420 const struct elf32_hdr *ehdr;
1421 struct q6v5 *qproc = rproc->priv;
1425 ret = reject_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
1427 dev_err(qproc->dev, "unable to load %s\n",
1428 qproc->hexagon_mdt_image);
1432 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1434 ehdr = (struct elf32_hdr *)fw->data;
1435 phdrs = (struct elf32_phdr *)(ehdr + 1);
1436 qproc->total_dump_size = 0;
1438 for (i = 0; i < ehdr->e_phnum; i++) {
1441 if (!q6v5_phdr_valid(phdr))
1444 ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
1446 qcom_q6v5_dump_segment,
1451 qproc->total_dump_size += phdr->p_memsz;
1454 release_firmware(fw);
1458 static const struct rproc_ops q6v5_ops = {
1459 .start = q6v5_start,
1461 .parse_fw = qcom_q6v5_register_dump_segments,
1465 static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
1467 struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
1469 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1470 qproc->proxy_clk_count);
1471 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1472 qproc->proxy_reg_count);
1473 q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1476 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
1478 struct of_phandle_args args;
1479 struct resource *res;
1482 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
1483 qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
1484 if (IS_ERR(qproc->reg_base))
1485 return PTR_ERR(qproc->reg_base);
1487 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
1488 qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
1489 if (IS_ERR(qproc->rmb_base))
1490 return PTR_ERR(qproc->rmb_base);
1492 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1493 "qcom,halt-regs", 3, 0, &args);
1495 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1499 qproc->halt_map = syscon_node_to_regmap(args.np);
1500 of_node_put(args.np);
1501 if (IS_ERR(qproc->halt_map))
1502 return PTR_ERR(qproc->halt_map);
1504 qproc->halt_q6 = args.args[0];
1505 qproc->halt_modem = args.args[1];
1506 qproc->halt_nc = args.args[2];
1508 if (qproc->has_spare_reg) {
1509 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1513 dev_err(&pdev->dev, "failed to parse spare-regs\n");
1517 qproc->conn_map = syscon_node_to_regmap(args.np);
1518 of_node_put(args.np);
1519 if (IS_ERR(qproc->conn_map))
1520 return PTR_ERR(qproc->conn_map);
1522 qproc->conn_box = args.args[0];
1528 static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1536 for (i = 0; clk_names[i]; i++) {
1537 clks[i] = devm_clk_get(dev, clk_names[i]);
1538 if (IS_ERR(clks[i])) {
1539 int rc = PTR_ERR(clks[i]);
1541 if (rc != -EPROBE_DEFER)
1542 dev_err(dev, "Failed to get %s clock\n",
1551 static int q6v5_pds_attach(struct device *dev, struct device **devs,
1561 while (pd_names[num_pds])
1564 for (i = 0; i < num_pds; i++) {
1565 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
1566 if (IS_ERR_OR_NULL(devs[i])) {
1567 ret = PTR_ERR(devs[i]) ? : -ENODATA;
1575 for (i--; i >= 0; i--)
1576 dev_pm_domain_detach(devs[i], false);
1581 static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
1586 for (i = 0; i < pd_count; i++)
1587 dev_pm_domain_detach(pds[i], false);
1590 static int q6v5_init_reset(struct q6v5 *qproc)
1592 qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1594 if (IS_ERR(qproc->mss_restart)) {
1595 dev_err(qproc->dev, "failed to acquire mss restart\n");
1596 return PTR_ERR(qproc->mss_restart);
1599 if (qproc->has_alt_reset || qproc->has_spare_reg) {
1600 qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
1602 if (IS_ERR(qproc->pdc_reset)) {
1603 dev_err(qproc->dev, "failed to acquire pdc reset\n");
1604 return PTR_ERR(qproc->pdc_reset);
1611 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1613 struct device_node *child;
1614 struct reserved_mem *rmem;
1615 struct device_node *node;
1620 * In the absence of mba/mpss sub-child, extract the mba and mpss
1621 * reserved memory regions from device's memory-region property.
1623 child = of_get_child_by_name(qproc->dev->of_node, "mba");
1625 node = of_parse_phandle(qproc->dev->of_node,
1626 "memory-region", 0);
1628 node = of_parse_phandle(child, "memory-region", 0);
1632 ret = of_address_to_resource(node, 0, &r);
1635 dev_err(qproc->dev, "unable to resolve mba region\n");
1639 qproc->mba_phys = r.start;
1640 qproc->mba_size = resource_size(&r);
1641 qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
1642 if (!qproc->mba_region) {
1643 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1644 &r.start, qproc->mba_size);
1649 node = of_parse_phandle(qproc->dev->of_node,
1650 "memory-region", 1);
1652 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1653 node = of_parse_phandle(child, "memory-region", 0);
1657 ret = of_address_to_resource(node, 0, &r);
1660 dev_err(qproc->dev, "unable to resolve mpss region\n");
1664 qproc->mpss_phys = qproc->mpss_reloc = r.start;
1665 qproc->mpss_size = resource_size(&r);
1668 node = of_parse_phandle(qproc->dev->of_node, "memory-region", 2);
1670 child = of_get_child_by_name(qproc->dev->of_node, "metadata");
1671 node = of_parse_phandle(child, "memory-region", 0);
1678 rmem = of_reserved_mem_lookup(node);
1680 dev_err(qproc->dev, "unable to resolve metadata region\n");
1684 qproc->mdata_phys = rmem->base;
1685 qproc->mdata_size = rmem->size;
1690 static int q6v5_probe(struct platform_device *pdev)
1692 const struct rproc_hexagon_res *desc;
1694 struct rproc *rproc;
1695 const char *mba_image;
1698 desc = of_device_get_match_data(&pdev->dev);
1702 if (desc->need_mem_protection && !qcom_scm_is_available())
1703 return -EPROBE_DEFER;
1705 mba_image = desc->hexagon_mba_image;
1706 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1708 if (ret < 0 && ret != -EINVAL)
1711 rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
1712 mba_image, sizeof(*qproc));
1714 dev_err(&pdev->dev, "failed to allocate rproc\n");
1718 rproc->auto_boot = false;
1719 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1721 qproc = (struct q6v5 *)rproc->priv;
1722 qproc->dev = &pdev->dev;
1723 qproc->rproc = rproc;
1724 qproc->hexagon_mdt_image = "/*(DEBLOBBED)*/";
1725 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1726 1, &qproc->hexagon_mdt_image);
1727 if (ret < 0 && ret != -EINVAL)
1730 platform_set_drvdata(pdev, qproc);
1732 qproc->has_spare_reg = desc->has_spare_reg;
1733 ret = q6v5_init_mem(qproc, pdev);
1737 ret = q6v5_alloc_memory_region(qproc);
1741 ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
1742 desc->proxy_clk_names);
1744 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
1747 qproc->proxy_clk_count = ret;
1749 ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
1750 desc->reset_clk_names);
1752 dev_err(&pdev->dev, "Failed to get reset clocks.\n");
1755 qproc->reset_clk_count = ret;
1757 ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
1758 desc->active_clk_names);
1760 dev_err(&pdev->dev, "Failed to get active clocks.\n");
1763 qproc->active_clk_count = ret;
1765 ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1766 desc->proxy_supply);
1768 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
1771 qproc->proxy_reg_count = ret;
1773 ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs,
1774 desc->active_supply);
1776 dev_err(&pdev->dev, "Failed to get active regulators.\n");
1779 qproc->active_reg_count = ret;
1781 ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds,
1782 desc->active_pd_names);
1784 dev_err(&pdev->dev, "Failed to attach active power domains\n");
1787 qproc->active_pd_count = ret;
1789 ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
1790 desc->proxy_pd_names);
1792 dev_err(&pdev->dev, "Failed to init power domains\n");
1793 goto detach_active_pds;
1795 qproc->proxy_pd_count = ret;
1797 qproc->has_alt_reset = desc->has_alt_reset;
1798 ret = q6v5_init_reset(qproc);
1800 goto detach_proxy_pds;
1802 qproc->version = desc->version;
1803 qproc->need_mem_protection = desc->need_mem_protection;
1804 qproc->has_mba_logs = desc->has_mba_logs;
1806 ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
1809 goto detach_proxy_pds;
1811 qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
1812 qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
1813 qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss");
1814 qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
1815 qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
1816 qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
1817 if (IS_ERR(qproc->sysmon)) {
1818 ret = PTR_ERR(qproc->sysmon);
1819 goto remove_subdevs;
1822 ret = rproc_add(rproc);
1824 goto remove_sysmon_subdev;
1828 remove_sysmon_subdev:
1829 qcom_remove_sysmon_subdev(qproc->sysmon);
1831 qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
1832 qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
1833 qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
1835 q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1837 q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
1844 static int q6v5_remove(struct platform_device *pdev)
1846 struct q6v5 *qproc = platform_get_drvdata(pdev);
1847 struct rproc *rproc = qproc->rproc;
1851 qcom_remove_sysmon_subdev(qproc->sysmon);
1852 qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
1853 qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
1854 qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
1856 q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1857 q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
1864 static const struct rproc_hexagon_res sc7180_mss = {
1865 .hexagon_mba_image = "/*(DEBLOBBED)*/",
1866 .proxy_clk_names = (char*[]){
1870 .reset_clk_names = (char*[]){
1876 .active_clk_names = (char*[]){
1881 .active_pd_names = (char*[]){
1885 .proxy_pd_names = (char*[]){
1891 .need_mem_protection = true,
1892 .has_alt_reset = false,
1893 .has_mba_logs = true,
1894 .has_spare_reg = true,
1895 .version = MSS_SC7180,
1898 static const struct rproc_hexagon_res sdm845_mss = {
1899 .hexagon_mba_image = "/*(DEBLOBBED)*/",
1900 .proxy_clk_names = (char*[]){
1905 .reset_clk_names = (char*[]){
1910 .active_clk_names = (char*[]){
1917 .active_pd_names = (char*[]){
1921 .proxy_pd_names = (char*[]){
1927 .need_mem_protection = true,
1928 .has_alt_reset = true,
1929 .has_mba_logs = false,
1930 .has_spare_reg = false,
1931 .version = MSS_SDM845,
1934 static const struct rproc_hexagon_res msm8998_mss = {
1935 .hexagon_mba_image = "/*(DEBLOBBED)*/",
1936 .proxy_clk_names = (char*[]){
1942 .active_clk_names = (char*[]){
1950 .proxy_pd_names = (char*[]){
1955 .need_mem_protection = true,
1956 .has_alt_reset = false,
1957 .has_mba_logs = false,
1958 .has_spare_reg = false,
1959 .version = MSS_MSM8998,
1962 static const struct rproc_hexagon_res msm8996_mss = {
1963 .hexagon_mba_image = "/*(DEBLOBBED)*/",
1964 .proxy_supply = (struct qcom_mss_reg_res[]) {
1971 .proxy_clk_names = (char*[]){
1977 .active_clk_names = (char*[]){
1986 .need_mem_protection = true,
1987 .has_alt_reset = false,
1988 .has_mba_logs = false,
1989 .has_spare_reg = false,
1990 .version = MSS_MSM8996,
1993 static const struct rproc_hexagon_res msm8916_mss = {
1994 .hexagon_mba_image = "/*(DEBLOBBED)*/",
1995 .proxy_supply = (struct qcom_mss_reg_res[]) {
2010 .proxy_clk_names = (char*[]){
2014 .active_clk_names = (char*[]){
2020 .need_mem_protection = false,
2021 .has_alt_reset = false,
2022 .has_mba_logs = false,
2023 .has_spare_reg = false,
2024 .version = MSS_MSM8916,
2027 static const struct rproc_hexagon_res msm8974_mss = {
2028 .hexagon_mba_image = "/*(DEBLOBBED)*/",
2029 .proxy_supply = (struct qcom_mss_reg_res[]) {
2044 .active_supply = (struct qcom_mss_reg_res[]) {
2052 .proxy_clk_names = (char*[]){
2056 .active_clk_names = (char*[]){
2062 .need_mem_protection = false,
2063 .has_alt_reset = false,
2064 .has_mba_logs = false,
2065 .has_spare_reg = false,
2066 .version = MSS_MSM8974,
2069 static const struct of_device_id q6v5_of_match[] = {
2070 { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
2071 { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
2072 { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
2073 { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
2074 { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
2075 { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
2076 { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
2079 MODULE_DEVICE_TABLE(of, q6v5_of_match);
2081 static struct platform_driver q6v5_driver = {
2082 .probe = q6v5_probe,
2083 .remove = q6v5_remove,
2085 .name = "qcom-q6v5-mss",
2086 .of_match_table = q6v5_of_match,
2089 module_platform_driver(q6v5_driver);
2091 MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
2092 MODULE_LICENSE("GPL v2");