2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
9 * Author: Thomas Abraham <thomas.ab@samsung.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqdomain.h>
25 #include <linux/irq.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/of_irq.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/err.h>
33 #include "pinctrl-samsung.h"
34 #include "pinctrl-exynos.h"
36 struct exynos_irq_chip {
44 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
46 return container_of(chip, struct exynos_irq_chip, chip);
49 static const struct samsung_pin_bank_type bank_type_off = {
50 .fld_width = { 4, 1, 2, 2, 2, 2, },
51 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
54 static const struct samsung_pin_bank_type bank_type_alive = {
55 .fld_width = { 4, 1, 2, 2, },
56 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
59 static void exynos_irq_mask(struct irq_data *irqd)
61 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
62 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
63 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
64 struct samsung_pinctrl_drv_data *d = bank->drvdata;
65 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
69 spin_lock_irqsave(&bank->slock, flags);
71 mask = readl(d->virt_base + reg_mask);
72 mask |= 1 << irqd->hwirq;
73 writel(mask, d->virt_base + reg_mask);
75 spin_unlock_irqrestore(&bank->slock, flags);
78 static void exynos_irq_ack(struct irq_data *irqd)
80 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
81 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
82 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
83 struct samsung_pinctrl_drv_data *d = bank->drvdata;
84 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
86 writel(1 << irqd->hwirq, d->virt_base + reg_pend);
89 static void exynos_irq_unmask(struct irq_data *irqd)
91 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
92 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
93 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
94 struct samsung_pinctrl_drv_data *d = bank->drvdata;
95 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
100 * Ack level interrupts right before unmask
102 * If we don't do this we'll get a double-interrupt. Level triggered
103 * interrupts must not fire an interrupt if the level is not
104 * _currently_ active, even if it was active while the interrupt was
107 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
108 exynos_irq_ack(irqd);
110 spin_lock_irqsave(&bank->slock, flags);
112 mask = readl(d->virt_base + reg_mask);
113 mask &= ~(1 << irqd->hwirq);
114 writel(mask, d->virt_base + reg_mask);
116 spin_unlock_irqrestore(&bank->slock, flags);
119 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
121 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
122 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
123 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
124 struct samsung_pinctrl_drv_data *d = bank->drvdata;
125 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
126 unsigned int con, trig_type;
127 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
130 case IRQ_TYPE_EDGE_RISING:
131 trig_type = EXYNOS_EINT_EDGE_RISING;
133 case IRQ_TYPE_EDGE_FALLING:
134 trig_type = EXYNOS_EINT_EDGE_FALLING;
136 case IRQ_TYPE_EDGE_BOTH:
137 trig_type = EXYNOS_EINT_EDGE_BOTH;
139 case IRQ_TYPE_LEVEL_HIGH:
140 trig_type = EXYNOS_EINT_LEVEL_HIGH;
142 case IRQ_TYPE_LEVEL_LOW:
143 trig_type = EXYNOS_EINT_LEVEL_LOW;
146 pr_err("unsupported external interrupt type\n");
150 if (type & IRQ_TYPE_EDGE_BOTH)
151 irq_set_handler_locked(irqd, handle_edge_irq);
153 irq_set_handler_locked(irqd, handle_level_irq);
155 con = readl(d->virt_base + reg_con);
156 con &= ~(EXYNOS_EINT_CON_MASK << shift);
157 con |= trig_type << shift;
158 writel(con, d->virt_base + reg_con);
163 static int exynos_irq_request_resources(struct irq_data *irqd)
165 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
166 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
167 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
168 const struct samsung_pin_bank_type *bank_type = bank->type;
169 struct samsung_pinctrl_drv_data *d = bank->drvdata;
170 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
171 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
177 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
179 dev_err(bank->gpio_chip.parent,
180 "unable to lock pin %s-%lu IRQ\n",
181 bank->name, irqd->hwirq);
185 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
186 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
187 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
189 spin_lock_irqsave(&bank->slock, flags);
191 con = readl(d->virt_base + reg_con);
192 con &= ~(mask << shift);
193 con |= EXYNOS_EINT_FUNC << shift;
194 writel(con, d->virt_base + reg_con);
196 spin_unlock_irqrestore(&bank->slock, flags);
201 static void exynos_irq_release_resources(struct irq_data *irqd)
203 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
204 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
205 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
206 const struct samsung_pin_bank_type *bank_type = bank->type;
207 struct samsung_pinctrl_drv_data *d = bank->drvdata;
208 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
209 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
214 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
215 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
216 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
218 spin_lock_irqsave(&bank->slock, flags);
220 con = readl(d->virt_base + reg_con);
221 con &= ~(mask << shift);
222 con |= FUNC_INPUT << shift;
223 writel(con, d->virt_base + reg_con);
225 spin_unlock_irqrestore(&bank->slock, flags);
227 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
231 * irq_chip for gpio interrupts.
233 static struct exynos_irq_chip exynos_gpio_irq_chip = {
235 .name = "exynos_gpio_irq_chip",
236 .irq_unmask = exynos_irq_unmask,
237 .irq_mask = exynos_irq_mask,
238 .irq_ack = exynos_irq_ack,
239 .irq_set_type = exynos_irq_set_type,
240 .irq_request_resources = exynos_irq_request_resources,
241 .irq_release_resources = exynos_irq_release_resources,
243 .eint_con = EXYNOS_GPIO_ECON_OFFSET,
244 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
245 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
248 static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
251 struct samsung_pin_bank *b = h->host_data;
253 irq_set_chip_data(virq, b);
254 irq_set_chip_and_handler(virq, &b->irq_chip->chip,
260 * irq domain callbacks for external gpio and wakeup interrupt controllers.
262 static const struct irq_domain_ops exynos_eint_irqd_ops = {
263 .map = exynos_eint_irq_map,
264 .xlate = irq_domain_xlate_twocell,
267 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
269 struct samsung_pinctrl_drv_data *d = data;
270 struct samsung_pin_bank *bank = d->pin_banks;
271 unsigned int svc, group, pin, virq;
273 svc = readl(d->virt_base + EXYNOS_SVC_OFFSET);
274 group = EXYNOS_SVC_GROUP(svc);
275 pin = svc & EXYNOS_SVC_NUM_MASK;
281 virq = irq_linear_revmap(bank->irq_domain, pin);
284 generic_handle_irq(virq);
288 struct exynos_eint_gpio_save {
296 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
297 * @d: driver data of samsung pinctrl driver.
299 static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
301 struct samsung_pin_bank *bank;
302 struct device *dev = d->dev;
307 dev_err(dev, "irq number not available\n");
311 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
312 0, dev_name(dev), d);
314 dev_err(dev, "irq request failed\n");
319 for (i = 0; i < d->nr_banks; ++i, ++bank) {
320 if (bank->eint_type != EINT_TYPE_GPIO)
322 bank->irq_domain = irq_domain_add_linear(bank->of_node,
323 bank->nr_pins, &exynos_eint_irqd_ops, bank);
324 if (!bank->irq_domain) {
325 dev_err(dev, "gpio irq domain add failed\n");
330 bank->soc_priv = devm_kzalloc(d->dev,
331 sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
332 if (!bank->soc_priv) {
333 irq_domain_remove(bank->irq_domain);
338 bank->irq_chip = &exynos_gpio_irq_chip;
344 for (--i, --bank; i >= 0; --i, --bank) {
345 if (bank->eint_type != EINT_TYPE_GPIO)
347 irq_domain_remove(bank->irq_domain);
353 static u32 exynos_eint_wake_mask = 0xffffffff;
355 u32 exynos_get_eint_wake_mask(void)
357 return exynos_eint_wake_mask;
360 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
362 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
363 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
365 pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
368 exynos_eint_wake_mask |= bit;
370 exynos_eint_wake_mask &= ~bit;
376 * irq_chip for wakeup interrupts
378 static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = {
380 .name = "exynos4210_wkup_irq_chip",
381 .irq_unmask = exynos_irq_unmask,
382 .irq_mask = exynos_irq_mask,
383 .irq_ack = exynos_irq_ack,
384 .irq_set_type = exynos_irq_set_type,
385 .irq_set_wake = exynos_wkup_irq_set_wake,
386 .irq_request_resources = exynos_irq_request_resources,
387 .irq_release_resources = exynos_irq_release_resources,
389 .eint_con = EXYNOS_WKUP_ECON_OFFSET,
390 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
391 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
394 static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = {
396 .name = "exynos7_wkup_irq_chip",
397 .irq_unmask = exynos_irq_unmask,
398 .irq_mask = exynos_irq_mask,
399 .irq_ack = exynos_irq_ack,
400 .irq_set_type = exynos_irq_set_type,
401 .irq_set_wake = exynos_wkup_irq_set_wake,
402 .irq_request_resources = exynos_irq_request_resources,
403 .irq_release_resources = exynos_irq_release_resources,
405 .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
406 .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
407 .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
410 /* list of external wakeup controllers supported */
411 static const struct of_device_id exynos_wkup_irq_ids[] = {
412 { .compatible = "samsung,exynos4210-wakeup-eint",
413 .data = &exynos4210_wkup_irq_chip },
414 { .compatible = "samsung,exynos7-wakeup-eint",
415 .data = &exynos7_wkup_irq_chip },
419 /* interrupt handler for wakeup interrupts 0..15 */
420 static void exynos_irq_eint0_15(struct irq_desc *desc)
422 struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);
423 struct samsung_pin_bank *bank = eintd->bank;
424 struct irq_chip *chip = irq_desc_get_chip(desc);
427 chained_irq_enter(chip, desc);
429 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
430 generic_handle_irq(eint_irq);
432 chained_irq_exit(chip, desc);
435 static inline void exynos_irq_demux_eint(unsigned long pend,
436 struct irq_domain *domain)
442 generic_handle_irq(irq_find_mapping(domain, irq));
447 /* interrupt handler for wakeup interrupt 16 */
448 static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
450 struct irq_chip *chip = irq_desc_get_chip(desc);
451 struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc);
452 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
457 chained_irq_enter(chip, desc);
459 for (i = 0; i < eintd->nr_banks; ++i) {
460 struct samsung_pin_bank *b = eintd->banks[i];
461 pend = readl(d->virt_base + b->irq_chip->eint_pend
463 mask = readl(d->virt_base + b->irq_chip->eint_mask
465 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
468 chained_irq_exit(chip, desc);
472 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
473 * @d: driver data of samsung pinctrl driver.
475 static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
477 struct device *dev = d->dev;
478 struct device_node *wkup_np = NULL;
479 struct device_node *np;
480 struct samsung_pin_bank *bank;
481 struct exynos_weint_data *weint_data;
482 struct exynos_muxed_weint_data *muxed_data;
483 struct exynos_irq_chip *irq_chip;
484 unsigned int muxed_banks = 0;
488 for_each_child_of_node(dev->of_node, np) {
489 const struct of_device_id *match;
491 match = of_match_node(exynos_wkup_irq_ids, np);
493 irq_chip = kmemdup(match->data,
494 sizeof(*irq_chip), GFP_KERNEL);
503 for (i = 0; i < d->nr_banks; ++i, ++bank) {
504 if (bank->eint_type != EINT_TYPE_WKUP)
507 bank->irq_domain = irq_domain_add_linear(bank->of_node,
508 bank->nr_pins, &exynos_eint_irqd_ops, bank);
509 if (!bank->irq_domain) {
510 dev_err(dev, "wkup irq domain add failed\n");
514 bank->irq_chip = irq_chip;
516 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
517 bank->eint_type = EINT_TYPE_WKUP_MUX;
522 weint_data = devm_kzalloc(dev, bank->nr_pins
523 * sizeof(*weint_data), GFP_KERNEL);
525 dev_err(dev, "could not allocate memory for weint_data\n");
529 for (idx = 0; idx < bank->nr_pins; ++idx) {
530 irq = irq_of_parse_and_map(bank->of_node, idx);
532 dev_err(dev, "irq number for eint-%s-%d not found\n",
536 weint_data[idx].irq = idx;
537 weint_data[idx].bank = bank;
538 irq_set_chained_handler_and_data(irq,
547 irq = irq_of_parse_and_map(wkup_np, 0);
549 dev_err(dev, "irq number for muxed EINTs not found\n");
553 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
554 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
556 dev_err(dev, "could not allocate memory for muxed_data\n");
560 irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31,
565 for (i = 0; i < d->nr_banks; ++i, ++bank) {
566 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
569 muxed_data->banks[idx++] = bank;
571 muxed_data->nr_banks = muxed_banks;
576 static void exynos_pinctrl_suspend_bank(
577 struct samsung_pinctrl_drv_data *drvdata,
578 struct samsung_pin_bank *bank)
580 struct exynos_eint_gpio_save *save = bank->soc_priv;
581 void __iomem *regs = drvdata->virt_base;
583 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
584 + bank->eint_offset);
585 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
586 + 2 * bank->eint_offset);
587 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
588 + 2 * bank->eint_offset + 4);
589 save->eint_mask = readl(regs + bank->irq_chip->eint_mask
590 + bank->eint_offset);
592 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
593 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
594 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
595 pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
598 static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
600 struct samsung_pin_bank *bank = drvdata->pin_banks;
603 for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
604 if (bank->eint_type == EINT_TYPE_GPIO)
605 exynos_pinctrl_suspend_bank(drvdata, bank);
608 static void exynos_pinctrl_resume_bank(
609 struct samsung_pinctrl_drv_data *drvdata,
610 struct samsung_pin_bank *bank)
612 struct exynos_eint_gpio_save *save = bank->soc_priv;
613 void __iomem *regs = drvdata->virt_base;
615 pr_debug("%s: con %#010x => %#010x\n", bank->name,
616 readl(regs + EXYNOS_GPIO_ECON_OFFSET
617 + bank->eint_offset), save->eint_con);
618 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
619 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
620 + 2 * bank->eint_offset), save->eint_fltcon0);
621 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
622 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
623 + 2 * bank->eint_offset + 4), save->eint_fltcon1);
624 pr_debug("%s: mask %#010x => %#010x\n", bank->name,
625 readl(regs + bank->irq_chip->eint_mask
626 + bank->eint_offset), save->eint_mask);
628 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
629 + bank->eint_offset);
630 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
631 + 2 * bank->eint_offset);
632 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
633 + 2 * bank->eint_offset + 4);
634 writel(save->eint_mask, regs + bank->irq_chip->eint_mask
635 + bank->eint_offset);
638 static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
640 struct samsung_pin_bank *bank = drvdata->pin_banks;
643 for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
644 if (bank->eint_type == EINT_TYPE_GPIO)
645 exynos_pinctrl_resume_bank(drvdata, bank);
648 /* pin banks of s5pv210 pin-controller */
649 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
650 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
651 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
652 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
653 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
654 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
655 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
656 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
657 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
658 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
659 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
660 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
661 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
662 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
663 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
664 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
665 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
666 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
667 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
668 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
669 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
670 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
671 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
672 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
673 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
674 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
675 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
676 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
677 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
678 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
679 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
680 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
681 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
682 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
683 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
686 const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
688 /* pin-controller instance 0 data */
689 .pin_banks = s5pv210_pin_bank,
690 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
691 .eint_gpio_init = exynos_eint_gpio_init,
692 .eint_wkup_init = exynos_eint_wkup_init,
693 .suspend = exynos_pinctrl_suspend,
694 .resume = exynos_pinctrl_resume,
698 /* pin banks of exynos3250 pin-controller 0 */
699 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
700 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
701 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
702 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
703 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
704 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
705 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
706 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
709 /* pin banks of exynos3250 pin-controller 1 */
710 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
711 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
712 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
713 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
714 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
715 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
716 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
717 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
718 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
719 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
720 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
721 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
722 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
723 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
724 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
725 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
726 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
730 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
731 * two gpio/pin-mux/pinconfig controllers.
733 const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
735 /* pin-controller instance 0 data */
736 .pin_banks = exynos3250_pin_banks0,
737 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
738 .eint_gpio_init = exynos_eint_gpio_init,
739 .suspend = exynos_pinctrl_suspend,
740 .resume = exynos_pinctrl_resume,
742 /* pin-controller instance 1 data */
743 .pin_banks = exynos3250_pin_banks1,
744 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
745 .eint_gpio_init = exynos_eint_gpio_init,
746 .eint_wkup_init = exynos_eint_wkup_init,
747 .suspend = exynos_pinctrl_suspend,
748 .resume = exynos_pinctrl_resume,
752 /* pin banks of exynos4210 pin-controller 0 */
753 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
754 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
755 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
756 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
757 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
758 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
759 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
760 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
761 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
762 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
763 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
764 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
765 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
766 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
767 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
768 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
769 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
772 /* pin banks of exynos4210 pin-controller 1 */
773 static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
774 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
775 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
776 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
777 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
778 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
779 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
780 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
781 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
782 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
783 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
784 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
785 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
786 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
787 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
788 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
789 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
790 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
791 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
792 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
793 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
796 /* pin banks of exynos4210 pin-controller 2 */
797 static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
798 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
802 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
803 * three gpio/pin-mux/pinconfig controllers.
805 const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
807 /* pin-controller instance 0 data */
808 .pin_banks = exynos4210_pin_banks0,
809 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
810 .eint_gpio_init = exynos_eint_gpio_init,
811 .suspend = exynos_pinctrl_suspend,
812 .resume = exynos_pinctrl_resume,
814 /* pin-controller instance 1 data */
815 .pin_banks = exynos4210_pin_banks1,
816 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
817 .eint_gpio_init = exynos_eint_gpio_init,
818 .eint_wkup_init = exynos_eint_wkup_init,
819 .suspend = exynos_pinctrl_suspend,
820 .resume = exynos_pinctrl_resume,
822 /* pin-controller instance 2 data */
823 .pin_banks = exynos4210_pin_banks2,
824 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
828 /* pin banks of exynos4x12 pin-controller 0 */
829 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
830 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
831 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
832 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
833 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
834 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
835 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
836 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
837 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
838 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
839 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
840 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
841 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
842 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
845 /* pin banks of exynos4x12 pin-controller 1 */
846 static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
847 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
848 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
849 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
850 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
851 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
852 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
853 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
854 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
855 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
856 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
857 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
858 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
859 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
860 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
861 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
862 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
863 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
864 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
865 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
866 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
867 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
868 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
869 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
872 /* pin banks of exynos4x12 pin-controller 2 */
873 static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
874 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
877 /* pin banks of exynos4x12 pin-controller 3 */
878 static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
879 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
880 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
881 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
882 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
883 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
887 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
888 * four gpio/pin-mux/pinconfig controllers.
890 const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
892 /* pin-controller instance 0 data */
893 .pin_banks = exynos4x12_pin_banks0,
894 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
895 .eint_gpio_init = exynos_eint_gpio_init,
896 .suspend = exynos_pinctrl_suspend,
897 .resume = exynos_pinctrl_resume,
899 /* pin-controller instance 1 data */
900 .pin_banks = exynos4x12_pin_banks1,
901 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
902 .eint_gpio_init = exynos_eint_gpio_init,
903 .eint_wkup_init = exynos_eint_wkup_init,
904 .suspend = exynos_pinctrl_suspend,
905 .resume = exynos_pinctrl_resume,
907 /* pin-controller instance 2 data */
908 .pin_banks = exynos4x12_pin_banks2,
909 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
910 .eint_gpio_init = exynos_eint_gpio_init,
911 .suspend = exynos_pinctrl_suspend,
912 .resume = exynos_pinctrl_resume,
914 /* pin-controller instance 3 data */
915 .pin_banks = exynos4x12_pin_banks3,
916 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
917 .eint_gpio_init = exynos_eint_gpio_init,
918 .suspend = exynos_pinctrl_suspend,
919 .resume = exynos_pinctrl_resume,
923 /* pin banks of exynos4415 pin-controller 0 */
924 static const struct samsung_pin_bank_data exynos4415_pin_banks0[] = {
925 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
926 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
927 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
928 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
929 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
930 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
931 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
932 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
933 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
934 EXYNOS_PIN_BANK_EINTG(1, 0x1C0, "gpf2", 0x38),
937 /* pin banks of exynos4415 pin-controller 1 */
938 static const struct samsung_pin_bank_data exynos4415_pin_banks1[] = {
939 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
940 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
941 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
942 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
943 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpl0", 0x18),
944 EXYNOS_PIN_BANK_EINTN(6, 0x120, "mp00"),
945 EXYNOS_PIN_BANK_EINTN(4, 0x140, "mp01"),
946 EXYNOS_PIN_BANK_EINTN(6, 0x160, "mp02"),
947 EXYNOS_PIN_BANK_EINTN(8, 0x180, "mp03"),
948 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "mp04"),
949 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "mp05"),
950 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "mp06"),
951 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
952 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
953 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
954 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
955 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
956 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
957 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
958 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
959 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
962 /* pin banks of exynos4415 pin-controller 2 */
963 static const struct samsung_pin_bank_data exynos4415_pin_banks2[] = {
964 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
965 EXYNOS_PIN_BANK_EINTN(2, 0x000, "etc1"),
969 * Samsung pinctrl driver data for Exynos4415 SoC. Exynos4415 SoC includes
970 * three gpio/pin-mux/pinconfig controllers.
972 const struct samsung_pin_ctrl exynos4415_pin_ctrl[] = {
974 /* pin-controller instance 0 data */
975 .pin_banks = exynos4415_pin_banks0,
976 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks0),
977 .eint_gpio_init = exynos_eint_gpio_init,
978 .suspend = exynos_pinctrl_suspend,
979 .resume = exynos_pinctrl_resume,
981 /* pin-controller instance 1 data */
982 .pin_banks = exynos4415_pin_banks1,
983 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks1),
984 .eint_gpio_init = exynos_eint_gpio_init,
985 .eint_wkup_init = exynos_eint_wkup_init,
986 .suspend = exynos_pinctrl_suspend,
987 .resume = exynos_pinctrl_resume,
989 /* pin-controller instance 2 data */
990 .pin_banks = exynos4415_pin_banks2,
991 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks2),
992 .eint_gpio_init = exynos_eint_gpio_init,
993 .suspend = exynos_pinctrl_suspend,
994 .resume = exynos_pinctrl_resume,
998 /* pin banks of exynos5250 pin-controller 0 */
999 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
1000 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1001 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1002 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1003 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1004 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1005 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1006 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
1007 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
1008 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
1009 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
1010 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
1011 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
1012 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
1013 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
1014 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
1015 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
1016 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
1017 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
1018 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
1019 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
1020 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
1021 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1022 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1023 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1024 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1027 /* pin banks of exynos5250 pin-controller 1 */
1028 static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
1029 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1030 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1031 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
1032 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
1033 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
1034 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
1035 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
1036 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
1037 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
1040 /* pin banks of exynos5250 pin-controller 2 */
1041 static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
1042 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
1043 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
1044 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
1045 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
1046 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
1049 /* pin banks of exynos5250 pin-controller 3 */
1050 static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
1051 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1055 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
1056 * four gpio/pin-mux/pinconfig controllers.
1058 const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
1060 /* pin-controller instance 0 data */
1061 .pin_banks = exynos5250_pin_banks0,
1062 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
1063 .eint_gpio_init = exynos_eint_gpio_init,
1064 .eint_wkup_init = exynos_eint_wkup_init,
1065 .suspend = exynos_pinctrl_suspend,
1066 .resume = exynos_pinctrl_resume,
1068 /* pin-controller instance 1 data */
1069 .pin_banks = exynos5250_pin_banks1,
1070 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
1071 .eint_gpio_init = exynos_eint_gpio_init,
1072 .suspend = exynos_pinctrl_suspend,
1073 .resume = exynos_pinctrl_resume,
1075 /* pin-controller instance 2 data */
1076 .pin_banks = exynos5250_pin_banks2,
1077 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
1078 .eint_gpio_init = exynos_eint_gpio_init,
1079 .suspend = exynos_pinctrl_suspend,
1080 .resume = exynos_pinctrl_resume,
1082 /* pin-controller instance 3 data */
1083 .pin_banks = exynos5250_pin_banks3,
1084 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
1085 .eint_gpio_init = exynos_eint_gpio_init,
1086 .suspend = exynos_pinctrl_suspend,
1087 .resume = exynos_pinctrl_resume,
1091 /* pin banks of exynos5260 pin-controller 0 */
1092 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
1093 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
1094 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
1095 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1096 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1097 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
1098 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
1099 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
1100 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
1101 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
1102 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
1103 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
1104 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
1105 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
1106 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
1107 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
1108 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
1109 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
1110 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
1111 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
1112 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
1113 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
1116 /* pin banks of exynos5260 pin-controller 1 */
1117 static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
1118 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
1119 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
1120 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1121 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1122 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
1125 /* pin banks of exynos5260 pin-controller 2 */
1126 static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
1127 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1128 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1132 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
1133 * three gpio/pin-mux/pinconfig controllers.
1135 const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
1137 /* pin-controller instance 0 data */
1138 .pin_banks = exynos5260_pin_banks0,
1139 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
1140 .eint_gpio_init = exynos_eint_gpio_init,
1141 .eint_wkup_init = exynos_eint_wkup_init,
1143 /* pin-controller instance 1 data */
1144 .pin_banks = exynos5260_pin_banks1,
1145 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
1146 .eint_gpio_init = exynos_eint_gpio_init,
1148 /* pin-controller instance 2 data */
1149 .pin_banks = exynos5260_pin_banks2,
1150 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
1151 .eint_gpio_init = exynos_eint_gpio_init,
1155 /* pin banks of exynos5410 pin-controller 0 */
1156 static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
1157 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1158 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1159 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1160 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1161 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1162 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1163 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
1164 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
1165 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
1166 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
1167 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
1168 EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
1169 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
1170 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
1171 EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
1172 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),
1173 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),
1174 EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),
1175 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),
1176 EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
1177 EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
1178 EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
1179 EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
1180 EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
1181 EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
1182 EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),
1183 EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),
1184 EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),
1185 EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),
1186 EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),
1187 EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),
1188 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1189 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1190 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1191 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1194 /* pin banks of exynos5410 pin-controller 1 */
1195 static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
1196 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
1197 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
1198 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
1199 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),
1200 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),
1201 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),
1202 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),
1203 EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),
1204 EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),
1207 /* pin banks of exynos5410 pin-controller 2 */
1208 static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
1209 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
1210 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
1211 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
1212 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
1213 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
1216 /* pin banks of exynos5410 pin-controller 3 */
1217 static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
1218 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1222 * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
1223 * four gpio/pin-mux/pinconfig controllers.
1225 const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
1227 /* pin-controller instance 0 data */
1228 .pin_banks = exynos5410_pin_banks0,
1229 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0),
1230 .eint_gpio_init = exynos_eint_gpio_init,
1231 .eint_wkup_init = exynos_eint_wkup_init,
1232 .suspend = exynos_pinctrl_suspend,
1233 .resume = exynos_pinctrl_resume,
1235 /* pin-controller instance 1 data */
1236 .pin_banks = exynos5410_pin_banks1,
1237 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1),
1238 .eint_gpio_init = exynos_eint_gpio_init,
1239 .suspend = exynos_pinctrl_suspend,
1240 .resume = exynos_pinctrl_resume,
1242 /* pin-controller instance 2 data */
1243 .pin_banks = exynos5410_pin_banks2,
1244 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2),
1245 .eint_gpio_init = exynos_eint_gpio_init,
1246 .suspend = exynos_pinctrl_suspend,
1247 .resume = exynos_pinctrl_resume,
1249 /* pin-controller instance 3 data */
1250 .pin_banks = exynos5410_pin_banks3,
1251 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3),
1252 .eint_gpio_init = exynos_eint_gpio_init,
1253 .suspend = exynos_pinctrl_suspend,
1254 .resume = exynos_pinctrl_resume,
1258 /* pin banks of exynos5420 pin-controller 0 */
1259 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
1260 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
1261 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1262 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1263 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1264 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1267 /* pin banks of exynos5420 pin-controller 1 */
1268 static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
1269 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
1270 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
1271 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1272 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1273 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
1274 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
1275 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
1276 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
1277 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
1278 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
1279 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
1280 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
1281 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
1284 /* pin banks of exynos5420 pin-controller 2 */
1285 static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
1286 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1287 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1288 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
1289 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
1290 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
1291 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
1292 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
1293 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
1296 /* pin banks of exynos5420 pin-controller 3 */
1297 static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
1298 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1299 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1300 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1301 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1302 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1303 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1304 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
1305 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
1306 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
1309 /* pin banks of exynos5420 pin-controller 4 */
1310 static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
1311 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1315 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
1316 * four gpio/pin-mux/pinconfig controllers.
1318 const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
1320 /* pin-controller instance 0 data */
1321 .pin_banks = exynos5420_pin_banks0,
1322 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
1323 .eint_gpio_init = exynos_eint_gpio_init,
1324 .eint_wkup_init = exynos_eint_wkup_init,
1326 /* pin-controller instance 1 data */
1327 .pin_banks = exynos5420_pin_banks1,
1328 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
1329 .eint_gpio_init = exynos_eint_gpio_init,
1331 /* pin-controller instance 2 data */
1332 .pin_banks = exynos5420_pin_banks2,
1333 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
1334 .eint_gpio_init = exynos_eint_gpio_init,
1336 /* pin-controller instance 3 data */
1337 .pin_banks = exynos5420_pin_banks3,
1338 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
1339 .eint_gpio_init = exynos_eint_gpio_init,
1341 /* pin-controller instance 4 data */
1342 .pin_banks = exynos5420_pin_banks4,
1343 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
1344 .eint_gpio_init = exynos_eint_gpio_init,
1348 /* pin banks of exynos5433 pin-controller - ALIVE */
1349 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = {
1350 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1351 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1352 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1353 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1356 /* pin banks of exynos5433 pin-controller - AUD */
1357 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = {
1358 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1359 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1362 /* pin banks of exynos5433 pin-controller - CPIF */
1363 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = {
1364 EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
1367 /* pin banks of exynos5433 pin-controller - eSE */
1368 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = {
1369 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
1372 /* pin banks of exynos5433 pin-controller - FINGER */
1373 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = {
1374 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
1377 /* pin banks of exynos5433 pin-controller - FSYS */
1378 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = {
1379 EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
1380 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
1381 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
1382 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
1383 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
1384 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
1387 /* pin banks of exynos5433 pin-controller - IMEM */
1388 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = {
1389 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
1392 /* pin banks of exynos5433 pin-controller - NFC */
1393 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = {
1394 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
1397 /* pin banks of exynos5433 pin-controller - PERIC */
1398 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = {
1399 EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
1400 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
1401 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
1402 EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
1403 EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
1404 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
1405 EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
1406 EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
1407 EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
1408 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
1409 EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
1410 EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
1411 EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
1412 EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
1413 EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
1414 EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
1415 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
1418 /* pin banks of exynos5433 pin-controller - TOUCH */
1419 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = {
1420 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
1424 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
1425 * ten gpio/pin-mux/pinconfig controllers.
1427 const struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
1429 /* pin-controller instance 0 data */
1430 .pin_banks = exynos5433_pin_banks0,
1431 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
1432 .eint_wkup_init = exynos_eint_wkup_init,
1433 .suspend = exynos_pinctrl_suspend,
1434 .resume = exynos_pinctrl_resume,
1436 /* pin-controller instance 1 data */
1437 .pin_banks = exynos5433_pin_banks1,
1438 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1),
1439 .eint_gpio_init = exynos_eint_gpio_init,
1440 .suspend = exynos_pinctrl_suspend,
1441 .resume = exynos_pinctrl_resume,
1443 /* pin-controller instance 2 data */
1444 .pin_banks = exynos5433_pin_banks2,
1445 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2),
1446 .eint_gpio_init = exynos_eint_gpio_init,
1447 .suspend = exynos_pinctrl_suspend,
1448 .resume = exynos_pinctrl_resume,
1450 /* pin-controller instance 3 data */
1451 .pin_banks = exynos5433_pin_banks3,
1452 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3),
1453 .eint_gpio_init = exynos_eint_gpio_init,
1454 .suspend = exynos_pinctrl_suspend,
1455 .resume = exynos_pinctrl_resume,
1457 /* pin-controller instance 4 data */
1458 .pin_banks = exynos5433_pin_banks4,
1459 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4),
1460 .eint_gpio_init = exynos_eint_gpio_init,
1461 .suspend = exynos_pinctrl_suspend,
1462 .resume = exynos_pinctrl_resume,
1464 /* pin-controller instance 5 data */
1465 .pin_banks = exynos5433_pin_banks5,
1466 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5),
1467 .eint_gpio_init = exynos_eint_gpio_init,
1468 .suspend = exynos_pinctrl_suspend,
1469 .resume = exynos_pinctrl_resume,
1471 /* pin-controller instance 6 data */
1472 .pin_banks = exynos5433_pin_banks6,
1473 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6),
1474 .eint_gpio_init = exynos_eint_gpio_init,
1475 .suspend = exynos_pinctrl_suspend,
1476 .resume = exynos_pinctrl_resume,
1478 /* pin-controller instance 7 data */
1479 .pin_banks = exynos5433_pin_banks7,
1480 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7),
1481 .eint_gpio_init = exynos_eint_gpio_init,
1482 .suspend = exynos_pinctrl_suspend,
1483 .resume = exynos_pinctrl_resume,
1485 /* pin-controller instance 8 data */
1486 .pin_banks = exynos5433_pin_banks8,
1487 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8),
1488 .eint_gpio_init = exynos_eint_gpio_init,
1489 .suspend = exynos_pinctrl_suspend,
1490 .resume = exynos_pinctrl_resume,
1492 /* pin-controller instance 9 data */
1493 .pin_banks = exynos5433_pin_banks9,
1494 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9),
1495 .eint_gpio_init = exynos_eint_gpio_init,
1496 .suspend = exynos_pinctrl_suspend,
1497 .resume = exynos_pinctrl_resume,
1501 /* pin banks of exynos7 pin-controller - ALIVE */
1502 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
1503 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1504 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1505 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1506 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1509 /* pin banks of exynos7 pin-controller - BUS0 */
1510 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
1511 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
1512 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
1513 EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
1514 EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
1515 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
1516 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
1517 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
1518 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
1519 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
1520 EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
1521 EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
1522 EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
1523 EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
1524 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
1525 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
1528 /* pin banks of exynos7 pin-controller - NFC */
1529 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
1530 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
1533 /* pin banks of exynos7 pin-controller - TOUCH */
1534 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
1535 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
1538 /* pin banks of exynos7 pin-controller - FF */
1539 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
1540 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
1543 /* pin banks of exynos7 pin-controller - ESE */
1544 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
1545 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
1548 /* pin banks of exynos7 pin-controller - FSYS0 */
1549 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
1550 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
1553 /* pin banks of exynos7 pin-controller - FSYS1 */
1554 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
1555 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
1556 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
1557 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
1558 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
1561 /* pin banks of exynos7 pin-controller - BUS1 */
1562 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
1563 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
1564 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
1565 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
1566 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
1567 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
1568 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
1569 EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
1570 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
1571 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
1572 EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
1575 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {
1576 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1577 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1580 const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
1582 /* pin-controller instance 0 Alive data */
1583 .pin_banks = exynos7_pin_banks0,
1584 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
1585 .eint_wkup_init = exynos_eint_wkup_init,
1587 /* pin-controller instance 1 BUS0 data */
1588 .pin_banks = exynos7_pin_banks1,
1589 .nr_banks = ARRAY_SIZE(exynos7_pin_banks1),
1590 .eint_gpio_init = exynos_eint_gpio_init,
1592 /* pin-controller instance 2 NFC data */
1593 .pin_banks = exynos7_pin_banks2,
1594 .nr_banks = ARRAY_SIZE(exynos7_pin_banks2),
1595 .eint_gpio_init = exynos_eint_gpio_init,
1597 /* pin-controller instance 3 TOUCH data */
1598 .pin_banks = exynos7_pin_banks3,
1599 .nr_banks = ARRAY_SIZE(exynos7_pin_banks3),
1600 .eint_gpio_init = exynos_eint_gpio_init,
1602 /* pin-controller instance 4 FF data */
1603 .pin_banks = exynos7_pin_banks4,
1604 .nr_banks = ARRAY_SIZE(exynos7_pin_banks4),
1605 .eint_gpio_init = exynos_eint_gpio_init,
1607 /* pin-controller instance 5 ESE data */
1608 .pin_banks = exynos7_pin_banks5,
1609 .nr_banks = ARRAY_SIZE(exynos7_pin_banks5),
1610 .eint_gpio_init = exynos_eint_gpio_init,
1612 /* pin-controller instance 6 FSYS0 data */
1613 .pin_banks = exynos7_pin_banks6,
1614 .nr_banks = ARRAY_SIZE(exynos7_pin_banks6),
1615 .eint_gpio_init = exynos_eint_gpio_init,
1617 /* pin-controller instance 7 FSYS1 data */
1618 .pin_banks = exynos7_pin_banks7,
1619 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7),
1620 .eint_gpio_init = exynos_eint_gpio_init,
1622 /* pin-controller instance 8 BUS1 data */
1623 .pin_banks = exynos7_pin_banks8,
1624 .nr_banks = ARRAY_SIZE(exynos7_pin_banks8),
1625 .eint_gpio_init = exynos_eint_gpio_init,
1627 /* pin-controller instance 9 AUD data */
1628 .pin_banks = exynos7_pin_banks9,
1629 .nr_banks = ARRAY_SIZE(exynos7_pin_banks9),
1630 .eint_gpio_init = exynos_eint_gpio_init,