1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91 pinctrl driver based on at91 pinmux core
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/init.h>
12 #include <linux/of_device.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/slab.h>
16 #include <linux/interrupt.h>
18 #include <linux/gpio/driver.h>
19 #include <linux/pinctrl/machine.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 /* Since we request GPIOs from ourself */
24 #include <linux/pinctrl/consumer.h>
26 #include "pinctrl-at91.h"
29 #define MAX_GPIO_BANKS 5
30 #define MAX_NB_GPIO_PER_BANK 32
32 struct at91_pinctrl_mux_ops;
34 struct at91_gpio_chip {
35 struct gpio_chip chip;
36 struct pinctrl_gpio_range range;
37 struct at91_gpio_chip *next; /* Bank sharing same clock */
38 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
39 int pioc_virq; /* PIO bank Linux virtual interrupt */
40 int pioc_idx; /* PIO bank index */
41 void __iomem *regbase; /* PIO bank virtual address */
42 struct clk *clock; /* associated clock */
43 struct at91_pinctrl_mux_ops *ops; /* ops */
46 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
48 static int gpio_banks;
50 #define PULL_UP (1 << 0)
51 #define MULTI_DRIVE (1 << 1)
52 #define DEGLITCH (1 << 2)
53 #define PULL_DOWN (1 << 3)
54 #define DIS_SCHMIT (1 << 4)
55 #define DRIVE_STRENGTH_SHIFT 5
56 #define DRIVE_STRENGTH_MASK 0x3
57 #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
58 #define OUTPUT (1 << 7)
59 #define OUTPUT_VAL_SHIFT 8
60 #define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
61 #define SLEWRATE_SHIFT 9
62 #define SLEWRATE_MASK 0x1
63 #define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
64 #define DEBOUNCE (1 << 16)
65 #define DEBOUNCE_VAL_SHIFT 17
66 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
69 * These defines will translated the dt binding settings to our internal
70 * settings. They are not necessarily the same value as the register setting.
71 * The actual drive strength current of low, medium and high must be looked up
72 * from the corresponding device datasheet. This value is different for pins
73 * that are even in the same banks. It is also dependent on VCC.
74 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
75 * strength when there is no dt config for it.
77 enum drive_strength_bit {
78 DRIVE_STRENGTH_BIT_DEF,
79 DRIVE_STRENGTH_BIT_LOW,
80 DRIVE_STRENGTH_BIT_MED,
81 DRIVE_STRENGTH_BIT_HI,
84 #define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
92 #define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
95 * struct at91_pmx_func - describes AT91 pinmux functions
96 * @name: the name of this specific function
97 * @groups: corresponding pin groups
98 * @ngroups: the number of groups
100 struct at91_pmx_func {
108 AT91_MUX_PERIPH_A = 1,
109 AT91_MUX_PERIPH_B = 2,
110 AT91_MUX_PERIPH_C = 3,
111 AT91_MUX_PERIPH_D = 4,
115 * struct at91_pmx_pin - describes an At91 pin mux
116 * @bank: the bank of the pin
117 * @pin: the pin number in the @bank
118 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
119 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
121 struct at91_pmx_pin {
129 * struct at91_pin_group - describes an At91 pin group
130 * @name: the name of this specific pin group
131 * @pins_conf: the mux mode for each pin in this group. The size of this
132 * array is the same as pins.
133 * @pins: an array of discrete physical pins used in this group, taken
134 * from the driver-local pin enumeration space
135 * @npins: the number of pins in this group array, i.e. the number of
136 * elements in .pins so we can iterate over that array
138 struct at91_pin_group {
140 struct at91_pmx_pin *pins_conf;
146 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
147 * on new IP with support for periph C and D the way to mux in
148 * periph A and B has changed
149 * So provide the right call back
150 * if not present means the IP does not support it
151 * @get_periph: return the periph mode configured
152 * @mux_A_periph: mux as periph A
153 * @mux_B_periph: mux as periph B
154 * @mux_C_periph: mux as periph C
155 * @mux_D_periph: mux as periph D
156 * @get_deglitch: get deglitch status
157 * @set_deglitch: enable/disable deglitch
158 * @get_debounce: get debounce status
159 * @set_debounce: enable/disable debounce
160 * @get_pulldown: get pulldown status
161 * @set_pulldown: enable/disable pulldown
162 * @get_schmitt_trig: get schmitt trigger status
163 * @disable_schmitt_trig: disable schmitt trigger
164 * @get_drivestrength: get driver strength
165 * @set_drivestrength: set driver strength
166 * @get_slewrate: get slew rate
167 * @set_slewrate: set slew rate
168 * @irq_type: return irq type
170 struct at91_pinctrl_mux_ops {
171 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
172 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
173 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
174 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
175 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
176 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
177 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
178 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
179 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
180 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
181 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
182 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
183 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
184 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
185 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
187 unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
188 void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
190 int (*irq_type)(struct irq_data *d, unsigned type);
193 static int gpio_irq_type(struct irq_data *d, unsigned type);
194 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
196 struct at91_pinctrl {
198 struct pinctrl_dev *pctl;
205 struct at91_pmx_func *functions;
208 struct at91_pin_group *groups;
211 struct at91_pinctrl_mux_ops *ops;
214 static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
215 const struct at91_pinctrl *info,
218 const struct at91_pin_group *grp = NULL;
221 for (i = 0; i < info->ngroups; i++) {
222 if (strcmp(info->groups[i].name, name))
225 grp = &info->groups[i];
226 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
233 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
235 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
237 return info->ngroups;
240 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
243 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
245 return info->groups[selector].name;
248 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
249 const unsigned **pins,
252 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
254 if (selector >= info->ngroups)
257 *pins = info->groups[selector].pins;
258 *npins = info->groups[selector].npins;
263 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
266 seq_printf(s, "%s", dev_name(pctldev->dev));
269 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
270 struct device_node *np,
271 struct pinctrl_map **map, unsigned *num_maps)
273 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
274 const struct at91_pin_group *grp;
275 struct pinctrl_map *new_map;
276 struct device_node *parent;
281 * first find the group of this node and check if we need to create
282 * config maps for pins
284 grp = at91_pinctrl_find_group_by_name(info, np->name);
286 dev_err(info->dev, "unable to find group for node %pOFn\n",
291 map_num += grp->npins;
292 new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
301 parent = of_get_parent(np);
303 devm_kfree(pctldev->dev, new_map);
306 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
307 new_map[0].data.mux.function = parent->name;
308 new_map[0].data.mux.group = np->name;
311 /* create config map */
313 for (i = 0; i < grp->npins; i++) {
314 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
315 new_map[i].data.configs.group_or_pin =
316 pin_get_name(pctldev, grp->pins[i]);
317 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
318 new_map[i].data.configs.num_configs = 1;
321 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
322 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
327 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
328 struct pinctrl_map *map, unsigned num_maps)
332 static const struct pinctrl_ops at91_pctrl_ops = {
333 .get_groups_count = at91_get_groups_count,
334 .get_group_name = at91_get_group_name,
335 .get_group_pins = at91_get_group_pins,
336 .pin_dbg_show = at91_pin_dbg_show,
337 .dt_node_to_map = at91_dt_node_to_map,
338 .dt_free_map = at91_dt_free_map,
341 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
344 if (!gpio_chips[bank])
347 return gpio_chips[bank]->regbase;
350 static inline int pin_to_bank(unsigned pin)
352 return pin /= MAX_NB_GPIO_PER_BANK;
355 static unsigned pin_to_mask(unsigned int pin)
360 static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
362 /* return the shift value for a pin for "two bit" per pin registers,
363 * i.e. drive strength */
364 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
365 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
368 static unsigned sama5d3_get_drive_register(unsigned int pin)
370 /* drive strength is split between two registers
371 * with two bits per pin */
372 return (pin >= MAX_NB_GPIO_PER_BANK/2)
373 ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
376 static unsigned at91sam9x5_get_drive_register(unsigned int pin)
378 /* drive strength is split between two registers
379 * with two bits per pin */
380 return (pin >= MAX_NB_GPIO_PER_BANK/2)
381 ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
384 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
386 writel_relaxed(mask, pio + PIO_IDR);
389 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
391 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
394 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
397 writel_relaxed(mask, pio + PIO_PPDDR);
399 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
402 static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val)
404 *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1;
405 return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1;
408 static void at91_mux_set_output(void __iomem *pio, unsigned int mask,
409 bool is_on, bool val)
411 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
412 writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
415 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
417 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
420 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
422 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
425 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
427 writel_relaxed(mask, pio + PIO_ASR);
430 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
432 writel_relaxed(mask, pio + PIO_BSR);
435 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
438 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
440 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
444 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
446 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
448 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
452 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
454 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
455 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
458 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
460 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
461 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
464 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
468 if (readl_relaxed(pio + PIO_PSR) & mask)
469 return AT91_MUX_GPIO;
471 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
472 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
477 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
481 if (readl_relaxed(pio + PIO_PSR) & mask)
482 return AT91_MUX_GPIO;
484 select = readl_relaxed(pio + PIO_ABSR) & mask;
489 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
491 return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
494 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
496 writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
499 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
501 if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
502 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
507 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
510 writel_relaxed(mask, pio + PIO_IFSCDR);
511 at91_mux_set_deglitch(pio, mask, is_on);
514 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
516 *div = readl_relaxed(pio + PIO_SCDR);
518 return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
519 ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
522 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
526 writel_relaxed(mask, pio + PIO_IFSCER);
527 writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
528 writel_relaxed(mask, pio + PIO_IFER);
530 writel_relaxed(mask, pio + PIO_IFSCDR);
533 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
535 return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
538 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
541 writel_relaxed(mask, pio + PIO_PUDR);
543 writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
546 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
548 writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
551 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
553 return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
556 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
558 unsigned tmp = readl_relaxed(reg);
560 tmp = tmp >> two_bit_pin_value_shift_amount(pin);
562 return tmp & DRIVE_STRENGTH_MASK;
565 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
568 unsigned tmp = read_drive_strength(pio +
569 sama5d3_get_drive_register(pin), pin);
571 /* SAMA5 strength is 1:1 with our defines,
572 * except 0 is equivalent to low per datasheet */
574 tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
579 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
582 unsigned tmp = read_drive_strength(pio +
583 at91sam9x5_get_drive_register(pin), pin);
585 /* strength is inverse in SAM9x5s hardware with the pinctrl defines
586 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
587 tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
592 static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
595 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
598 return DRIVE_STRENGTH_BIT_HI;
600 return DRIVE_STRENGTH_BIT_LOW;
603 static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
605 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
607 if ((tmp & BIT(pin)))
608 return SLEWRATE_BIT_ENA;
610 return SLEWRATE_BIT_DIS;
613 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
615 unsigned tmp = readl_relaxed(reg);
616 unsigned shift = two_bit_pin_value_shift_amount(pin);
618 tmp &= ~(DRIVE_STRENGTH_MASK << shift);
619 tmp |= strength << shift;
621 writel_relaxed(tmp, reg);
624 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
627 /* do nothing if setting is zero */
631 /* strength is 1 to 1 with setting for SAMA5 */
632 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
635 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
638 /* do nothing if setting is zero */
642 /* strength is inverse on SAM9x5s with our defines
643 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
644 setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
646 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
650 static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
655 if (setting <= DRIVE_STRENGTH_BIT_DEF ||
656 setting == DRIVE_STRENGTH_BIT_MED ||
657 setting > DRIVE_STRENGTH_BIT_HI)
660 tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
662 /* Strength is 0: low, 1: hi */
663 if (setting == DRIVE_STRENGTH_BIT_LOW)
668 writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
671 static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
676 if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
679 tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
681 if (setting == SLEWRATE_BIT_DIS)
686 writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
689 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
690 .get_periph = at91_mux_get_periph,
691 .mux_A_periph = at91_mux_set_A_periph,
692 .mux_B_periph = at91_mux_set_B_periph,
693 .get_deglitch = at91_mux_get_deglitch,
694 .set_deglitch = at91_mux_set_deglitch,
695 .irq_type = gpio_irq_type,
698 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
699 .get_periph = at91_mux_pio3_get_periph,
700 .mux_A_periph = at91_mux_pio3_set_A_periph,
701 .mux_B_periph = at91_mux_pio3_set_B_periph,
702 .mux_C_periph = at91_mux_pio3_set_C_periph,
703 .mux_D_periph = at91_mux_pio3_set_D_periph,
704 .get_deglitch = at91_mux_pio3_get_deglitch,
705 .set_deglitch = at91_mux_pio3_set_deglitch,
706 .get_debounce = at91_mux_pio3_get_debounce,
707 .set_debounce = at91_mux_pio3_set_debounce,
708 .get_pulldown = at91_mux_pio3_get_pulldown,
709 .set_pulldown = at91_mux_pio3_set_pulldown,
710 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
711 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
712 .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
713 .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
714 .irq_type = alt_gpio_irq_type,
717 static const struct at91_pinctrl_mux_ops sam9x60_ops = {
718 .get_periph = at91_mux_pio3_get_periph,
719 .mux_A_periph = at91_mux_pio3_set_A_periph,
720 .mux_B_periph = at91_mux_pio3_set_B_periph,
721 .mux_C_periph = at91_mux_pio3_set_C_periph,
722 .mux_D_periph = at91_mux_pio3_set_D_periph,
723 .get_deglitch = at91_mux_pio3_get_deglitch,
724 .set_deglitch = at91_mux_pio3_set_deglitch,
725 .get_debounce = at91_mux_pio3_get_debounce,
726 .set_debounce = at91_mux_pio3_set_debounce,
727 .get_pulldown = at91_mux_pio3_get_pulldown,
728 .set_pulldown = at91_mux_pio3_set_pulldown,
729 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
730 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
731 .get_drivestrength = at91_mux_sam9x60_get_drivestrength,
732 .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
733 .get_slewrate = at91_mux_sam9x60_get_slewrate,
734 .set_slewrate = at91_mux_sam9x60_set_slewrate,
735 .irq_type = alt_gpio_irq_type,
738 static struct at91_pinctrl_mux_ops sama5d3_ops = {
739 .get_periph = at91_mux_pio3_get_periph,
740 .mux_A_periph = at91_mux_pio3_set_A_periph,
741 .mux_B_periph = at91_mux_pio3_set_B_periph,
742 .mux_C_periph = at91_mux_pio3_set_C_periph,
743 .mux_D_periph = at91_mux_pio3_set_D_periph,
744 .get_deglitch = at91_mux_pio3_get_deglitch,
745 .set_deglitch = at91_mux_pio3_set_deglitch,
746 .get_debounce = at91_mux_pio3_get_debounce,
747 .set_debounce = at91_mux_pio3_set_debounce,
748 .get_pulldown = at91_mux_pio3_get_pulldown,
749 .set_pulldown = at91_mux_pio3_set_pulldown,
750 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
751 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
752 .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
753 .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
754 .irq_type = alt_gpio_irq_type,
757 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
760 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
761 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
763 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
764 pin->bank + 'A', pin->pin, pin->conf);
768 static int pin_check_config(struct at91_pinctrl *info, const char *name,
769 int index, const struct at91_pmx_pin *pin)
773 /* check if it's a valid config */
774 if (pin->bank >= gpio_banks) {
775 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
776 name, index, pin->bank, gpio_banks);
780 if (!gpio_chips[pin->bank]) {
781 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
782 name, index, pin->bank);
786 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
787 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
788 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
797 if (mux >= info->nmux) {
798 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
799 name, index, mux, info->nmux);
803 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
804 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
805 name, index, mux, pin->bank + 'A', pin->pin);
812 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
814 writel_relaxed(mask, pio + PIO_PDR);
817 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
819 writel_relaxed(mask, pio + PIO_PER);
820 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
823 static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
826 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
827 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
828 const struct at91_pmx_pin *pin;
829 uint32_t npins = info->groups[group].npins;
834 dev_dbg(info->dev, "enable function %s group %s\n",
835 info->functions[selector].name, info->groups[group].name);
837 /* first check that all the pins of the group are valid with a valid
839 for (i = 0; i < npins; i++) {
841 ret = pin_check_config(info, info->groups[group].name, i, pin);
846 for (i = 0; i < npins; i++) {
848 at91_pin_dbg(info->dev, pin);
849 pio = pin_to_controller(info, pin->bank);
854 mask = pin_to_mask(pin->pin);
855 at91_mux_disable_interrupt(pio, mask);
858 at91_mux_gpio_enable(pio, mask, 1);
860 case AT91_MUX_PERIPH_A:
861 info->ops->mux_A_periph(pio, mask);
863 case AT91_MUX_PERIPH_B:
864 info->ops->mux_B_periph(pio, mask);
866 case AT91_MUX_PERIPH_C:
867 if (!info->ops->mux_C_periph)
869 info->ops->mux_C_periph(pio, mask);
871 case AT91_MUX_PERIPH_D:
872 if (!info->ops->mux_D_periph)
874 info->ops->mux_D_periph(pio, mask);
878 at91_mux_gpio_disable(pio, mask);
884 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
886 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
888 return info->nfunctions;
891 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
894 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
896 return info->functions[selector].name;
899 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
900 const char * const **groups,
901 unsigned * const num_groups)
903 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
905 *groups = info->functions[selector].groups;
906 *num_groups = info->functions[selector].ngroups;
911 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
912 struct pinctrl_gpio_range *range,
915 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
916 struct at91_gpio_chip *at91_chip;
917 struct gpio_chip *chip;
921 dev_err(npct->dev, "invalid range\n");
925 dev_err(npct->dev, "missing GPIO chip in range\n");
929 at91_chip = gpiochip_get_data(chip);
931 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
933 mask = 1 << (offset - chip->base);
935 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
936 offset, 'A' + range->id, offset - chip->base, mask);
938 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
943 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
944 struct pinctrl_gpio_range *range,
947 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
949 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
950 /* Set the pin to some default state, GPIO is usually default */
953 static const struct pinmux_ops at91_pmx_ops = {
954 .get_functions_count = at91_pmx_get_funcs_count,
955 .get_function_name = at91_pmx_get_func_name,
956 .get_function_groups = at91_pmx_get_groups,
957 .set_mux = at91_pmx_set,
958 .gpio_request_enable = at91_gpio_request_enable,
959 .gpio_disable_free = at91_gpio_disable_free,
962 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
963 unsigned pin_id, unsigned long *config)
965 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
972 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
973 pio = pin_to_controller(info, pin_to_bank(pin_id));
978 pin = pin_id % MAX_NB_GPIO_PER_BANK;
980 if (at91_mux_get_multidrive(pio, pin))
981 *config |= MULTI_DRIVE;
983 if (at91_mux_get_pullup(pio, pin))
986 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
988 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
989 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
990 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
991 *config |= PULL_DOWN;
992 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
993 *config |= DIS_SCHMIT;
994 if (info->ops->get_drivestrength)
995 *config |= (info->ops->get_drivestrength(pio, pin)
996 << DRIVE_STRENGTH_SHIFT);
997 if (info->ops->get_slewrate)
998 *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
999 if (at91_mux_get_output(pio, pin, &out))
1000 *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
1005 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
1006 unsigned pin_id, unsigned long *configs,
1007 unsigned num_configs)
1009 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1013 unsigned long config;
1016 for (i = 0; i < num_configs; i++) {
1017 config = configs[i];
1020 "%s:%d, pin_id=%d, config=0x%lx",
1021 __func__, __LINE__, pin_id, config);
1022 pio = pin_to_controller(info, pin_to_bank(pin_id));
1027 pin = pin_id % MAX_NB_GPIO_PER_BANK;
1028 mask = pin_to_mask(pin);
1030 if (config & PULL_UP && config & PULL_DOWN)
1033 at91_mux_set_output(pio, mask, config & OUTPUT,
1034 (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
1035 at91_mux_set_pullup(pio, mask, config & PULL_UP);
1036 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
1037 if (info->ops->set_deglitch)
1038 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
1039 if (info->ops->set_debounce)
1040 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
1041 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
1042 if (info->ops->set_pulldown)
1043 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
1044 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
1045 info->ops->disable_schmitt_trig(pio, mask);
1046 if (info->ops->set_drivestrength)
1047 info->ops->set_drivestrength(pio, pin,
1048 (config & DRIVE_STRENGTH)
1049 >> DRIVE_STRENGTH_SHIFT);
1050 if (info->ops->set_slewrate)
1051 info->ops->set_slewrate(pio, pin,
1052 (config & SLEWRATE) >> SLEWRATE_SHIFT);
1054 } /* for each config */
1059 #define DBG_SHOW_FLAG(flag) do { \
1060 if (config & flag) { \
1063 seq_puts(s, #flag); \
1068 #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \
1069 if ((config & mask) == flag) { \
1072 seq_puts(s, #name); \
1077 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1078 struct seq_file *s, unsigned pin_id)
1080 unsigned long config;
1081 int val, num_conf = 0;
1083 at91_pinconf_get(pctldev, pin_id, &config);
1085 DBG_SHOW_FLAG(MULTI_DRIVE);
1086 DBG_SHOW_FLAG(PULL_UP);
1087 DBG_SHOW_FLAG(PULL_DOWN);
1088 DBG_SHOW_FLAG(DIS_SCHMIT);
1089 DBG_SHOW_FLAG(DEGLITCH);
1090 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
1091 DRIVE_STRENGTH_LOW);
1092 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
1093 DRIVE_STRENGTH_MED);
1094 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
1096 DBG_SHOW_FLAG(SLEWRATE);
1097 DBG_SHOW_FLAG(DEBOUNCE);
1098 if (config & DEBOUNCE) {
1099 val = config >> DEBOUNCE_VAL_SHIFT;
1100 seq_printf(s, "(%d)", val);
1106 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
1107 struct seq_file *s, unsigned group)
1111 static const struct pinconf_ops at91_pinconf_ops = {
1112 .pin_config_get = at91_pinconf_get,
1113 .pin_config_set = at91_pinconf_set,
1114 .pin_config_dbg_show = at91_pinconf_dbg_show,
1115 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
1118 static struct pinctrl_desc at91_pinctrl_desc = {
1119 .pctlops = &at91_pctrl_ops,
1120 .pmxops = &at91_pmx_ops,
1121 .confops = &at91_pinconf_ops,
1122 .owner = THIS_MODULE,
1125 static const char *gpio_compat = "atmel,at91rm9200-gpio";
1127 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
1128 struct device_node *np)
1130 struct device_node *child;
1132 for_each_child_of_node(np, child) {
1133 if (of_device_is_compatible(child, gpio_compat)) {
1134 if (of_device_is_available(child))
1135 info->nactive_banks++;
1138 info->ngroups += of_get_child_count(child);
1143 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1144 struct device_node *np)
1150 list = of_get_property(np, "atmel,mux-mask", &size);
1152 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1156 size /= sizeof(*list);
1157 if (!size || size % gpio_banks) {
1158 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1161 info->nmux = size / gpio_banks;
1163 info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32),
1165 if (!info->mux_mask)
1168 ret = of_property_read_u32_array(np, "atmel,mux-mask",
1169 info->mux_mask, size);
1171 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1175 static int at91_pinctrl_parse_groups(struct device_node *np,
1176 struct at91_pin_group *grp,
1177 struct at91_pinctrl *info, u32 index)
1179 struct at91_pmx_pin *pin;
1184 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
1186 /* Initialise group */
1187 grp->name = np->name;
1190 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1191 * do sanity check and calculate pins number
1193 list = of_get_property(np, "atmel,pins", &size);
1194 /* we do not check return since it's safe node passed down */
1195 size /= sizeof(*list);
1196 if (!size || size % 4) {
1197 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1201 grp->npins = size / 4;
1202 pin = grp->pins_conf = devm_kcalloc(info->dev,
1204 sizeof(struct at91_pmx_pin),
1206 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
1208 if (!grp->pins_conf || !grp->pins)
1211 for (i = 0, j = 0; i < size; i += 4, j++) {
1212 pin->bank = be32_to_cpu(*list++);
1213 pin->pin = be32_to_cpu(*list++);
1214 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1215 pin->mux = be32_to_cpu(*list++);
1216 pin->conf = be32_to_cpu(*list++);
1218 at91_pin_dbg(info->dev, pin);
1225 static int at91_pinctrl_parse_functions(struct device_node *np,
1226 struct at91_pinctrl *info, u32 index)
1228 struct device_node *child;
1229 struct at91_pmx_func *func;
1230 struct at91_pin_group *grp;
1232 static u32 grp_index;
1235 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
1237 func = &info->functions[index];
1239 /* Initialise function */
1240 func->name = np->name;
1241 func->ngroups = of_get_child_count(np);
1242 if (func->ngroups == 0) {
1243 dev_err(info->dev, "no groups defined\n");
1246 func->groups = devm_kcalloc(info->dev,
1247 func->ngroups, sizeof(char *), GFP_KERNEL);
1251 for_each_child_of_node(np, child) {
1252 func->groups[i] = child->name;
1253 grp = &info->groups[grp_index++];
1254 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1264 static const struct of_device_id at91_pinctrl_of_match[] = {
1265 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1266 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1267 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1268 { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
1272 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1273 struct at91_pinctrl *info)
1278 struct device_node *np = pdev->dev.of_node;
1279 struct device_node *child;
1284 info->dev = &pdev->dev;
1285 info->ops = (struct at91_pinctrl_mux_ops *)
1286 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1287 at91_pinctrl_child_count(info, np);
1289 if (gpio_banks < 1) {
1290 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
1294 ret = at91_pinctrl_mux_mask(info, np);
1298 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1300 dev_dbg(&pdev->dev, "mux-mask\n");
1301 tmp = info->mux_mask;
1302 for (i = 0; i < gpio_banks; i++) {
1303 for (j = 0; j < info->nmux; j++, tmp++) {
1304 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1308 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1309 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1310 info->functions = devm_kcalloc(&pdev->dev,
1312 sizeof(struct at91_pmx_func),
1314 if (!info->functions)
1317 info->groups = devm_kcalloc(&pdev->dev,
1319 sizeof(struct at91_pin_group),
1324 dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
1325 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1326 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1330 for_each_child_of_node(np, child) {
1331 if (of_device_is_compatible(child, gpio_compat))
1333 ret = at91_pinctrl_parse_functions(child, info, i++);
1335 dev_err(&pdev->dev, "failed to parse function\n");
1344 static int at91_pinctrl_probe(struct platform_device *pdev)
1346 struct at91_pinctrl *info;
1347 struct pinctrl_pin_desc *pdesc;
1348 int ret, i, j, k, ngpio_chips_enabled = 0;
1350 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1354 ret = at91_pinctrl_probe_dt(pdev, info);
1359 * We need all the GPIO drivers to probe FIRST, or we will not be able
1360 * to obtain references to the struct gpio_chip * for them, and we
1361 * need this to proceed.
1363 for (i = 0; i < gpio_banks; i++)
1365 ngpio_chips_enabled++;
1367 if (ngpio_chips_enabled < info->nactive_banks) {
1368 dev_warn(&pdev->dev,
1369 "All GPIO chips are not registered yet (%d/%d)\n",
1370 ngpio_chips_enabled, info->nactive_banks);
1371 devm_kfree(&pdev->dev, info);
1372 return -EPROBE_DEFER;
1375 at91_pinctrl_desc.name = dev_name(&pdev->dev);
1376 at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1377 at91_pinctrl_desc.pins = pdesc =
1378 devm_kcalloc(&pdev->dev,
1379 at91_pinctrl_desc.npins, sizeof(*pdesc),
1382 if (!at91_pinctrl_desc.pins)
1385 for (i = 0, k = 0; i < gpio_banks; i++) {
1386 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1388 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1393 platform_set_drvdata(pdev, info);
1394 info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc,
1397 if (IS_ERR(info->pctl)) {
1398 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1399 return PTR_ERR(info->pctl);
1402 /* We will handle a range of GPIO pins */
1403 for (i = 0; i < gpio_banks; i++)
1405 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1407 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1412 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1414 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1415 void __iomem *pio = at91_gpio->regbase;
1416 unsigned mask = 1 << offset;
1419 osr = readl_relaxed(pio + PIO_OSR);
1421 return GPIO_LINE_DIRECTION_OUT;
1423 return GPIO_LINE_DIRECTION_IN;
1426 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1428 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1429 void __iomem *pio = at91_gpio->regbase;
1430 unsigned mask = 1 << offset;
1432 writel_relaxed(mask, pio + PIO_ODR);
1436 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1438 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1439 void __iomem *pio = at91_gpio->regbase;
1440 unsigned mask = 1 << offset;
1443 pdsr = readl_relaxed(pio + PIO_PDSR);
1444 return (pdsr & mask) != 0;
1447 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1450 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1451 void __iomem *pio = at91_gpio->regbase;
1452 unsigned mask = 1 << offset;
1454 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1457 static void at91_gpio_set_multiple(struct gpio_chip *chip,
1458 unsigned long *mask, unsigned long *bits)
1460 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1461 void __iomem *pio = at91_gpio->regbase;
1463 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1464 /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1465 uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
1466 uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
1468 writel_relaxed(set_mask, pio + PIO_SODR);
1469 writel_relaxed(clear_mask, pio + PIO_CODR);
1472 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1475 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1476 void __iomem *pio = at91_gpio->regbase;
1477 unsigned mask = 1 << offset;
1479 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1480 writel_relaxed(mask, pio + PIO_OER);
1485 #ifdef CONFIG_DEBUG_FS
1486 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1490 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1491 void __iomem *pio = at91_gpio->regbase;
1492 const char *gpio_label;
1494 for_each_requested_gpio(chip, i, gpio_label) {
1495 unsigned mask = pin_to_mask(i);
1497 mode = at91_gpio->ops->get_periph(pio, mask);
1498 seq_printf(s, "[%s] GPIO%s%d: ",
1499 gpio_label, chip->label, i);
1500 if (mode == AT91_MUX_GPIO) {
1501 seq_printf(s, "[gpio] ");
1502 seq_printf(s, "%s ",
1503 readl_relaxed(pio + PIO_OSR) & mask ?
1504 "output" : "input");
1505 seq_printf(s, "%s\n",
1506 readl_relaxed(pio + PIO_PDSR) & mask ?
1509 seq_printf(s, "[periph %c]\n",
1515 #define at91_gpio_dbg_show NULL
1518 /* Several AIC controller irqs are dispatched through this GPIO handler.
1519 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1520 * at91_set_gpio_input() then maybe enable its glitch filter.
1521 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1523 * First implementation always triggers on rising and falling edges
1524 * whereas the newer PIO3 can be additionally configured to trigger on
1525 * level, edge with any polarity.
1527 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1528 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1529 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1532 static void gpio_irq_mask(struct irq_data *d)
1534 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1535 void __iomem *pio = at91_gpio->regbase;
1536 unsigned mask = 1 << d->hwirq;
1539 writel_relaxed(mask, pio + PIO_IDR);
1542 static void gpio_irq_unmask(struct irq_data *d)
1544 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1545 void __iomem *pio = at91_gpio->regbase;
1546 unsigned mask = 1 << d->hwirq;
1549 writel_relaxed(mask, pio + PIO_IER);
1552 static int gpio_irq_type(struct irq_data *d, unsigned type)
1556 case IRQ_TYPE_EDGE_BOTH:
1563 /* Alternate irq type for PIO3 support */
1564 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1566 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1567 void __iomem *pio = at91_gpio->regbase;
1568 unsigned mask = 1 << d->hwirq;
1571 case IRQ_TYPE_EDGE_RISING:
1572 irq_set_handler_locked(d, handle_simple_irq);
1573 writel_relaxed(mask, pio + PIO_ESR);
1574 writel_relaxed(mask, pio + PIO_REHLSR);
1576 case IRQ_TYPE_EDGE_FALLING:
1577 irq_set_handler_locked(d, handle_simple_irq);
1578 writel_relaxed(mask, pio + PIO_ESR);
1579 writel_relaxed(mask, pio + PIO_FELLSR);
1581 case IRQ_TYPE_LEVEL_LOW:
1582 irq_set_handler_locked(d, handle_level_irq);
1583 writel_relaxed(mask, pio + PIO_LSR);
1584 writel_relaxed(mask, pio + PIO_FELLSR);
1586 case IRQ_TYPE_LEVEL_HIGH:
1587 irq_set_handler_locked(d, handle_level_irq);
1588 writel_relaxed(mask, pio + PIO_LSR);
1589 writel_relaxed(mask, pio + PIO_REHLSR);
1591 case IRQ_TYPE_EDGE_BOTH:
1593 * disable additional interrupt modes:
1594 * fall back to default behavior
1596 irq_set_handler_locked(d, handle_simple_irq);
1597 writel_relaxed(mask, pio + PIO_AIMDR);
1601 pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq);
1605 /* enable additional interrupt modes */
1606 writel_relaxed(mask, pio + PIO_AIMER);
1611 static void gpio_irq_ack(struct irq_data *d)
1613 /* the interrupt is already cleared before by reading ISR */
1618 static u32 wakeups[MAX_GPIO_BANKS];
1619 static u32 backups[MAX_GPIO_BANKS];
1621 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1623 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1624 unsigned bank = at91_gpio->pioc_idx;
1625 unsigned mask = 1 << d->hwirq;
1627 if (unlikely(bank >= MAX_GPIO_BANKS))
1631 wakeups[bank] |= mask;
1633 wakeups[bank] &= ~mask;
1635 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1640 void at91_pinctrl_gpio_suspend(void)
1644 for (i = 0; i < gpio_banks; i++) {
1650 pio = gpio_chips[i]->regbase;
1652 backups[i] = readl_relaxed(pio + PIO_IMR);
1653 writel_relaxed(backups[i], pio + PIO_IDR);
1654 writel_relaxed(wakeups[i], pio + PIO_IER);
1657 clk_disable_unprepare(gpio_chips[i]->clock);
1659 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1664 void at91_pinctrl_gpio_resume(void)
1668 for (i = 0; i < gpio_banks; i++) {
1674 pio = gpio_chips[i]->regbase;
1677 clk_prepare_enable(gpio_chips[i]->clock);
1679 writel_relaxed(wakeups[i], pio + PIO_IDR);
1680 writel_relaxed(backups[i], pio + PIO_IER);
1685 #define gpio_irq_set_wake NULL
1686 #endif /* CONFIG_PM */
1688 static void gpio_irq_handler(struct irq_desc *desc)
1690 struct irq_chip *chip = irq_desc_get_chip(desc);
1691 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1692 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
1693 void __iomem *pio = at91_gpio->regbase;
1697 chained_irq_enter(chip, desc);
1699 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1700 * When there are none pending, we're finished unless we need
1701 * to process multiple banks (like ID_PIOCDE on sam9263).
1703 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1705 if (!at91_gpio->next)
1707 at91_gpio = at91_gpio->next;
1708 pio = at91_gpio->regbase;
1709 gpio_chip = &at91_gpio->chip;
1713 for_each_set_bit(n, &isr, BITS_PER_LONG) {
1714 generic_handle_irq(irq_find_mapping(
1715 gpio_chip->irq.domain, n));
1718 chained_irq_exit(chip, desc);
1719 /* now it may re-trigger */
1722 static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1723 struct at91_gpio_chip *at91_gpio)
1725 struct gpio_chip *gpiochip_prev = NULL;
1726 struct at91_gpio_chip *prev = NULL;
1727 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1728 struct irq_chip *gpio_irqchip;
1729 struct gpio_irq_chip *girq;
1732 gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip),
1737 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1739 gpio_irqchip->name = "GPIO";
1740 gpio_irqchip->irq_ack = gpio_irq_ack;
1741 gpio_irqchip->irq_disable = gpio_irq_mask;
1742 gpio_irqchip->irq_mask = gpio_irq_mask;
1743 gpio_irqchip->irq_unmask = gpio_irq_unmask;
1744 gpio_irqchip->irq_set_wake = gpio_irq_set_wake,
1745 gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
1747 /* Disable irqs of this PIO controller */
1748 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1751 * Let the generic code handle this edge IRQ, the the chained
1752 * handler will perform the actual work of handling the parent
1755 girq = &at91_gpio->chip.irq;
1756 girq->chip = gpio_irqchip;
1757 girq->default_type = IRQ_TYPE_NONE;
1758 girq->handler = handle_edge_irq;
1761 * The top level handler handles one bank of GPIOs, except
1762 * on some SoC it can handle up to three...
1763 * We only set up the handler for the first of the list.
1765 gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1766 if (!gpiochip_prev) {
1767 girq->parent_handler = gpio_irq_handler;
1768 girq->num_parents = 1;
1769 girq->parents = devm_kcalloc(&pdev->dev, 1,
1770 sizeof(*girq->parents),
1774 girq->parents[0] = at91_gpio->pioc_virq;
1778 prev = gpiochip_get_data(gpiochip_prev);
1779 /* we can only have 2 banks before */
1780 for (i = 0; i < 2; i++) {
1784 prev->next = at91_gpio;
1792 /* This structure is replicated for each GPIO block allocated at probe time */
1793 static const struct gpio_chip at91_gpio_template = {
1794 .request = gpiochip_generic_request,
1795 .free = gpiochip_generic_free,
1796 .get_direction = at91_gpio_get_direction,
1797 .direction_input = at91_gpio_direction_input,
1798 .get = at91_gpio_get,
1799 .direction_output = at91_gpio_direction_output,
1800 .set = at91_gpio_set,
1801 .set_multiple = at91_gpio_set_multiple,
1802 .dbg_show = at91_gpio_dbg_show,
1804 .ngpio = MAX_NB_GPIO_PER_BANK,
1807 static const struct of_device_id at91_gpio_of_match[] = {
1808 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1809 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1810 { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
1814 static int at91_gpio_probe(struct platform_device *pdev)
1816 struct device_node *np = pdev->dev.of_node;
1817 struct at91_gpio_chip *at91_chip = NULL;
1818 struct gpio_chip *chip;
1819 struct pinctrl_gpio_range *range;
1822 int alias_idx = of_alias_get_id(np, "gpio");
1826 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1827 if (gpio_chips[alias_idx]) {
1832 irq = platform_get_irq(pdev, 0);
1838 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1844 at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0);
1845 if (IS_ERR(at91_chip->regbase)) {
1846 ret = PTR_ERR(at91_chip->regbase);
1850 at91_chip->ops = (struct at91_pinctrl_mux_ops *)
1851 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1852 at91_chip->pioc_virq = irq;
1853 at91_chip->pioc_idx = alias_idx;
1855 at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
1856 if (IS_ERR(at91_chip->clock)) {
1857 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1858 ret = PTR_ERR(at91_chip->clock);
1862 ret = clk_prepare_enable(at91_chip->clock);
1864 dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n");
1865 goto clk_enable_err;
1868 at91_chip->chip = at91_gpio_template;
1870 chip = &at91_chip->chip;
1872 chip->label = dev_name(&pdev->dev);
1873 chip->parent = &pdev->dev;
1874 chip->owner = THIS_MODULE;
1875 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1877 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1878 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1879 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1880 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1882 chip->ngpio = ngpio;
1885 names = devm_kcalloc(&pdev->dev, chip->ngpio, sizeof(char *),
1890 goto clk_enable_err;
1893 for (i = 0; i < chip->ngpio; i++)
1894 names[i] = devm_kasprintf(&pdev->dev, GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1896 chip->names = (const char *const *)names;
1898 range = &at91_chip->range;
1899 range->name = chip->label;
1900 range->id = alias_idx;
1901 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1903 range->npins = chip->ngpio;
1906 ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1908 goto gpiochip_add_err;
1910 ret = gpiochip_add_data(chip, at91_chip);
1912 goto gpiochip_add_err;
1914 gpio_chips[alias_idx] = at91_chip;
1915 gpio_banks = max(gpio_banks, alias_idx + 1);
1917 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1923 clk_disable_unprepare(at91_chip->clock);
1925 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1930 static struct platform_driver at91_gpio_driver = {
1932 .name = "gpio-at91",
1933 .of_match_table = at91_gpio_of_match,
1935 .probe = at91_gpio_probe,
1938 static struct platform_driver at91_pinctrl_driver = {
1940 .name = "pinctrl-at91",
1941 .of_match_table = at91_pinctrl_of_match,
1943 .probe = at91_pinctrl_probe,
1946 static struct platform_driver * const drivers[] = {
1948 &at91_pinctrl_driver,
1951 static int __init at91_pinctrl_init(void)
1953 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1955 arch_initcall(at91_pinctrl_init);