1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
8 #define MAX_NR_DEVFNS 256
10 #define PCI_FIND_CAP_TTL 48
12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
14 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
16 /* Power stable to PERST# inactive from PCIe card Electromechanical Spec */
17 #define PCIE_T_PVPERL_MS 100
20 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
21 * Recommends 1ms to 10ms timeout to check L2 ready.
23 #define PCIE_PME_TO_L2_TIMEOUT_US 10000
25 extern const unsigned char pcie_link_speed[];
26 extern bool pci_early_dump;
28 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
29 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
30 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
32 /* Functions internal to the PCI core code */
34 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
35 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
36 void pci_cleanup_rom(struct pci_dev *dev);
38 extern const struct attribute_group pci_dev_smbios_attr_group;
42 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
43 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
45 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
46 enum pci_mmap_api mmap_api);
48 bool pci_reset_supported(struct pci_dev *dev);
49 void pci_init_reset_methods(struct pci_dev *dev);
50 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
51 int pci_bus_error_reset(struct pci_dev *dev);
53 struct pci_cap_saved_data {
60 struct pci_cap_saved_state {
61 struct hlist_node next;
62 struct pci_cap_saved_data cap;
65 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
66 void pci_free_cap_save_buffers(struct pci_dev *dev);
67 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
68 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
69 u16 cap, unsigned int size);
70 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
71 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
74 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
75 #define PCI_PM_D3HOT_WAIT 10 /* msec */
76 #define PCI_PM_D3COLD_WAIT 100 /* msec */
78 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
79 void pci_refresh_power_state(struct pci_dev *dev);
80 int pci_power_up(struct pci_dev *dev);
81 void pci_disable_enabled_device(struct pci_dev *dev);
82 int pci_finish_runtime_suspend(struct pci_dev *dev);
83 void pcie_clear_device_status(struct pci_dev *dev);
84 void pcie_clear_root_pme_status(struct pci_dev *dev);
85 bool pci_check_pme_status(struct pci_dev *dev);
86 void pci_pme_wakeup_bus(struct pci_bus *bus);
87 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
88 void pci_pme_restore(struct pci_dev *dev);
89 bool pci_dev_need_resume(struct pci_dev *dev);
90 void pci_dev_adjust_pme(struct pci_dev *dev);
91 void pci_dev_complete_resume(struct pci_dev *pci_dev);
92 void pci_config_pm_runtime_get(struct pci_dev *dev);
93 void pci_config_pm_runtime_put(struct pci_dev *dev);
94 void pci_pm_init(struct pci_dev *dev);
95 void pci_ea_init(struct pci_dev *dev);
96 void pci_msi_init(struct pci_dev *dev);
97 void pci_msix_init(struct pci_dev *dev);
98 bool pci_bridge_d3_possible(struct pci_dev *dev);
99 void pci_bridge_d3_update(struct pci_dev *dev);
100 void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
101 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
103 static inline void pci_wakeup_event(struct pci_dev *dev)
105 /* Wait 100 ms before the system can be put into a sleep state. */
106 pm_wakeup_event(&dev->dev, 100);
109 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
111 return !!(pci_dev->subordinate);
114 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
117 * Currently we allow normal PCI devices and PCI bridges transition
118 * into D3 if their bridge_d3 is set.
120 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
123 static inline bool pcie_downstream_port(const struct pci_dev *dev)
125 int type = pci_pcie_type(dev);
127 return type == PCI_EXP_TYPE_ROOT_PORT ||
128 type == PCI_EXP_TYPE_DOWNSTREAM ||
129 type == PCI_EXP_TYPE_PCIE_BRIDGE;
132 void pci_vpd_init(struct pci_dev *dev);
133 void pci_vpd_release(struct pci_dev *dev);
134 extern const struct attribute_group pci_dev_vpd_attr_group;
136 /* PCI Virtual Channel */
137 int pci_save_vc_state(struct pci_dev *dev);
138 void pci_restore_vc_state(struct pci_dev *dev);
139 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
141 /* PCI /proc functions */
142 #ifdef CONFIG_PROC_FS
143 int pci_proc_attach_device(struct pci_dev *dev);
144 int pci_proc_detach_device(struct pci_dev *dev);
145 int pci_proc_detach_bus(struct pci_bus *bus);
147 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
148 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
149 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
152 /* Functions for PCI Hotplug drivers to use */
153 int pci_hp_add_bridge(struct pci_dev *dev);
155 #ifdef HAVE_PCI_LEGACY
156 void pci_create_legacy_files(struct pci_bus *bus);
157 void pci_remove_legacy_files(struct pci_bus *bus);
159 static inline void pci_create_legacy_files(struct pci_bus *bus) { }
160 static inline void pci_remove_legacy_files(struct pci_bus *bus) { }
163 /* Lock for read/write access to pci device and bus lists */
164 extern struct rw_semaphore pci_bus_sem;
165 extern struct mutex pci_slot_mutex;
167 extern raw_spinlock_t pci_lock;
169 extern unsigned int pci_pm_d3hot_delay;
171 #ifdef CONFIG_PCI_MSI
172 void pci_no_msi(void);
174 static inline void pci_no_msi(void) { }
177 void pci_realloc_get_opt(char *);
179 static inline int pci_no_d1d2(struct pci_dev *dev)
181 unsigned int parent_dstates = 0;
184 parent_dstates = dev->bus->self->no_d1d2;
185 return (dev->no_d1d2 || parent_dstates);
188 extern const struct attribute_group *pci_dev_groups[];
189 extern const struct attribute_group *pcibus_groups[];
190 extern const struct device_type pci_dev_type;
191 extern const struct attribute_group *pci_bus_groups[];
193 extern unsigned long pci_hotplug_io_size;
194 extern unsigned long pci_hotplug_mmio_size;
195 extern unsigned long pci_hotplug_mmio_pref_size;
196 extern unsigned long pci_hotplug_bus_size;
199 * pci_match_one_device - Tell if a PCI device structure has a matching
200 * PCI device id structure
201 * @id: single PCI device id structure to match
202 * @dev: the PCI device structure to match against
204 * Returns the matching pci_device_id structure or %NULL if there is no match.
206 static inline const struct pci_device_id *
207 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
209 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
210 (id->device == PCI_ANY_ID || id->device == dev->device) &&
211 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
212 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
213 !((id->class ^ dev->class) & id->class_mask))
218 /* PCI slot sysfs helper code */
219 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
221 extern struct kset *pci_slots_kset;
223 struct pci_slot_attribute {
224 struct attribute attr;
225 ssize_t (*show)(struct pci_slot *, char *);
226 ssize_t (*store)(struct pci_slot *, const char *, size_t);
228 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
231 pci_bar_unknown, /* Standard PCI BAR probe */
232 pci_bar_io, /* An I/O port BAR */
233 pci_bar_mem32, /* A 32-bit memory BAR */
234 pci_bar_mem64, /* A 64-bit memory BAR */
237 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
238 void pci_put_host_bridge_device(struct device *dev);
240 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
241 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
243 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
245 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
247 int pci_setup_device(struct pci_dev *dev);
248 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
249 struct resource *res, unsigned int reg);
250 void pci_configure_ari(struct pci_dev *dev);
251 void __pci_bus_size_bridges(struct pci_bus *bus,
252 struct list_head *realloc_head);
253 void __pci_bus_assign_resources(const struct pci_bus *bus,
254 struct list_head *realloc_head,
255 struct list_head *fail_head);
256 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
258 const char *pci_resource_name(struct pci_dev *dev, unsigned int i);
260 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
261 void pci_disable_bridge_window(struct pci_dev *dev);
262 struct pci_bus *pci_bus_get(struct pci_bus *bus);
263 void pci_bus_put(struct pci_bus *bus);
265 /* PCIe link information from Link Capabilities 2 */
266 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
267 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
268 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
269 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
270 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
271 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
272 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
275 /* PCIe speed to Mb/s reduced by encoding overhead */
276 #define PCIE_SPEED2MBS_ENC(speed) \
277 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
278 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
279 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
280 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
281 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
282 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
285 const char *pci_speed_string(enum pci_bus_speed speed);
286 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
287 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
288 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
289 enum pcie_link_width *width);
290 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
291 void pcie_report_downtraining(struct pci_dev *dev);
292 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
294 /* Single Root I/O Virtualization */
296 int pos; /* Capability position */
297 int nres; /* Number of resources */
298 u32 cap; /* SR-IOV Capabilities */
299 u16 ctrl; /* SR-IOV Control */
300 u16 total_VFs; /* Total VFs associated with the PF */
301 u16 initial_VFs; /* Initial VFs associated with the PF */
302 u16 num_VFs; /* Number of VFs available */
303 u16 offset; /* First VF Routing ID offset */
304 u16 stride; /* Following VF stride */
305 u16 vf_device; /* VF device ID */
306 u32 pgsz; /* Page size for BAR alignment */
307 u8 link; /* Function Dependency Link */
308 u8 max_VF_buses; /* Max buses consumed by VFs */
309 u16 driver_max_VFs; /* Max num VFs driver supports */
310 struct pci_dev *dev; /* Lowest numbered PF */
311 struct pci_dev *self; /* This PF */
312 u32 class; /* VF device */
313 u8 hdr_type; /* VF header type */
314 u16 subsystem_vendor; /* VF subsystem vendor */
315 u16 subsystem_device; /* VF subsystem device */
316 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
317 bool drivers_autoprobe; /* Auto probing of VFs by driver */
320 #ifdef CONFIG_PCI_DOE
321 void pci_doe_init(struct pci_dev *pdev);
322 void pci_doe_destroy(struct pci_dev *pdev);
323 void pci_doe_disconnected(struct pci_dev *pdev);
325 static inline void pci_doe_init(struct pci_dev *pdev) { }
326 static inline void pci_doe_destroy(struct pci_dev *pdev) { }
327 static inline void pci_doe_disconnected(struct pci_dev *pdev) { }
331 * pci_dev_set_io_state - Set the new error state if possible.
333 * @dev: PCI device to set new error_state
334 * @new: the state we want dev to be in
336 * If the device is experiencing perm_failure, it has to remain in that state.
337 * Any other transition is allowed.
339 * Returns true if state has been changed to the requested state.
341 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
342 pci_channel_state_t new)
344 pci_channel_state_t old;
347 case pci_channel_io_perm_failure:
348 xchg(&dev->error_state, pci_channel_io_perm_failure);
350 case pci_channel_io_frozen:
351 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
352 pci_channel_io_frozen);
353 return old != pci_channel_io_perm_failure;
354 case pci_channel_io_normal:
355 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
356 pci_channel_io_normal);
357 return old != pci_channel_io_perm_failure;
363 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
365 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
366 pci_doe_disconnected(dev);
371 /* pci_dev priv_flags */
372 #define PCI_DEV_ADDED 0
373 #define PCI_DPC_RECOVERED 1
374 #define PCI_DPC_RECOVERING 2
376 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
378 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
381 static inline bool pci_dev_is_added(const struct pci_dev *dev)
383 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
386 #ifdef CONFIG_PCIEAER
387 #include <linux/aer.h>
389 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
391 struct aer_err_info {
392 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
397 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
398 unsigned int __pad1:5;
399 unsigned int multi_error_valid:1;
401 unsigned int first_error:5;
402 unsigned int __pad2:2;
403 unsigned int tlp_header_valid:1;
405 unsigned int status; /* COR/UNCOR Error Status */
406 unsigned int mask; /* COR/UNCOR Error Mask */
407 struct aer_header_log_regs tlp; /* TLP Header */
410 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
411 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
412 #endif /* CONFIG_PCIEAER */
414 #ifdef CONFIG_PCIEPORTBUS
415 /* Cached RCEC Endpoint Association */
423 #ifdef CONFIG_PCIE_DPC
424 void pci_save_dpc_state(struct pci_dev *dev);
425 void pci_restore_dpc_state(struct pci_dev *dev);
426 void pci_dpc_init(struct pci_dev *pdev);
427 void dpc_process_error(struct pci_dev *pdev);
428 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
429 bool pci_dpc_recovered(struct pci_dev *pdev);
431 static inline void pci_save_dpc_state(struct pci_dev *dev) { }
432 static inline void pci_restore_dpc_state(struct pci_dev *dev) { }
433 static inline void pci_dpc_init(struct pci_dev *pdev) { }
434 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
437 #ifdef CONFIG_PCIEPORTBUS
438 void pci_rcec_init(struct pci_dev *dev);
439 void pci_rcec_exit(struct pci_dev *dev);
440 void pcie_link_rcec(struct pci_dev *rcec);
441 void pcie_walk_rcec(struct pci_dev *rcec,
442 int (*cb)(struct pci_dev *, void *),
445 static inline void pci_rcec_init(struct pci_dev *dev) { }
446 static inline void pci_rcec_exit(struct pci_dev *dev) { }
447 static inline void pcie_link_rcec(struct pci_dev *rcec) { }
448 static inline void pcie_walk_rcec(struct pci_dev *rcec,
449 int (*cb)(struct pci_dev *, void *),
453 #ifdef CONFIG_PCI_ATS
454 /* Address Translation Service */
455 void pci_ats_init(struct pci_dev *dev);
456 void pci_restore_ats_state(struct pci_dev *dev);
458 static inline void pci_ats_init(struct pci_dev *d) { }
459 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
460 #endif /* CONFIG_PCI_ATS */
462 #ifdef CONFIG_PCI_PRI
463 void pci_pri_init(struct pci_dev *dev);
464 void pci_restore_pri_state(struct pci_dev *pdev);
466 static inline void pci_pri_init(struct pci_dev *dev) { }
467 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
470 #ifdef CONFIG_PCI_PASID
471 void pci_pasid_init(struct pci_dev *dev);
472 void pci_restore_pasid_state(struct pci_dev *pdev);
474 static inline void pci_pasid_init(struct pci_dev *dev) { }
475 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
478 #ifdef CONFIG_PCI_IOV
479 int pci_iov_init(struct pci_dev *dev);
480 void pci_iov_release(struct pci_dev *dev);
481 void pci_iov_remove(struct pci_dev *dev);
482 void pci_iov_update_resource(struct pci_dev *dev, int resno);
483 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
484 void pci_restore_iov_state(struct pci_dev *dev);
485 int pci_iov_bus_range(struct pci_bus *bus);
486 extern const struct attribute_group sriov_pf_dev_attr_group;
487 extern const struct attribute_group sriov_vf_dev_attr_group;
489 static inline int pci_iov_init(struct pci_dev *dev)
493 static inline void pci_iov_release(struct pci_dev *dev) { }
494 static inline void pci_iov_remove(struct pci_dev *dev) { }
495 static inline void pci_restore_iov_state(struct pci_dev *dev) { }
496 static inline int pci_iov_bus_range(struct pci_bus *bus)
501 #endif /* CONFIG_PCI_IOV */
503 #ifdef CONFIG_PCIE_PTM
504 void pci_ptm_init(struct pci_dev *dev);
505 void pci_save_ptm_state(struct pci_dev *dev);
506 void pci_restore_ptm_state(struct pci_dev *dev);
507 void pci_suspend_ptm(struct pci_dev *dev);
508 void pci_resume_ptm(struct pci_dev *dev);
510 static inline void pci_ptm_init(struct pci_dev *dev) { }
511 static inline void pci_save_ptm_state(struct pci_dev *dev) { }
512 static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
513 static inline void pci_suspend_ptm(struct pci_dev *dev) { }
514 static inline void pci_resume_ptm(struct pci_dev *dev) { }
517 unsigned long pci_cardbus_resource_alignment(struct resource *);
519 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
520 struct resource *res)
522 #ifdef CONFIG_PCI_IOV
523 int resno = res - dev->resource;
525 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
526 return pci_sriov_resource_alignment(dev, resno);
528 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
529 return pci_cardbus_resource_alignment(res);
530 return resource_alignment(res);
533 void pci_acs_init(struct pci_dev *dev);
534 #ifdef CONFIG_PCI_QUIRKS
535 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
536 int pci_dev_specific_enable_acs(struct pci_dev *dev);
537 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
538 bool pcie_failed_link_retrain(struct pci_dev *dev);
540 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
545 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
549 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
553 static inline bool pcie_failed_link_retrain(struct pci_dev *dev)
559 /* PCI error reporting and recovery */
560 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
561 pci_channel_state_t state,
562 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
564 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
565 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt);
566 #ifdef CONFIG_PCIEASPM
567 void pcie_aspm_init_link_state(struct pci_dev *pdev);
568 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
569 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);
570 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
572 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
573 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
574 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { }
575 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
578 #ifdef CONFIG_PCIE_ECRC
579 void pcie_set_ecrc_checking(struct pci_dev *dev);
580 void pcie_ecrc_get_policy(char *str);
582 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
583 static inline void pcie_ecrc_get_policy(char *str) { }
586 struct pci_dev_reset_methods {
589 int (*reset)(struct pci_dev *dev, bool probe);
592 struct pci_reset_fn_method {
593 int (*reset_fn)(struct pci_dev *pdev, bool probe);
597 #ifdef CONFIG_PCI_QUIRKS
598 int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
600 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
606 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
607 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
608 struct resource *res);
610 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
611 u16 segment, struct resource *res)
617 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
618 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
619 static inline u64 pci_rebar_size_to_bytes(int size)
621 return 1ULL << (size + 20);
627 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
628 int of_get_pci_domain_nr(struct device_node *node);
629 int of_pci_get_max_link_speed(struct device_node *node);
630 u32 of_pci_get_slot_power_limit(struct device_node *node,
631 u8 *slot_power_limit_value,
632 u8 *slot_power_limit_scale);
633 int pci_set_of_node(struct pci_dev *dev);
634 void pci_release_of_node(struct pci_dev *dev);
635 void pci_set_bus_of_node(struct pci_bus *bus);
636 void pci_release_bus_of_node(struct pci_bus *bus);
638 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
642 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
648 of_get_pci_domain_nr(struct device_node *node)
654 of_pci_get_max_link_speed(struct device_node *node)
660 of_pci_get_slot_power_limit(struct device_node *node,
661 u8 *slot_power_limit_value,
662 u8 *slot_power_limit_scale)
664 if (slot_power_limit_value)
665 *slot_power_limit_value = 0;
666 if (slot_power_limit_scale)
667 *slot_power_limit_scale = 0;
671 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }
672 static inline void pci_release_of_node(struct pci_dev *dev) { }
673 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
674 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
676 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
681 #endif /* CONFIG_OF */
685 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES
686 void of_pci_make_dev_node(struct pci_dev *pdev);
687 void of_pci_remove_node(struct pci_dev *pdev);
688 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
689 struct device_node *np);
691 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { }
692 static inline void of_pci_remove_node(struct pci_dev *pdev) { }
695 #ifdef CONFIG_PCIEAER
696 void pci_no_aer(void);
697 void pci_aer_init(struct pci_dev *dev);
698 void pci_aer_exit(struct pci_dev *dev);
699 extern const struct attribute_group aer_stats_attr_group;
700 void pci_aer_clear_fatal_status(struct pci_dev *dev);
701 int pci_aer_clear_status(struct pci_dev *dev);
702 int pci_aer_raw_clear_status(struct pci_dev *dev);
703 void pci_save_aer_state(struct pci_dev *dev);
704 void pci_restore_aer_state(struct pci_dev *dev);
706 static inline void pci_no_aer(void) { }
707 static inline void pci_aer_init(struct pci_dev *d) { }
708 static inline void pci_aer_exit(struct pci_dev *d) { }
709 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
710 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
711 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
712 static inline void pci_save_aer_state(struct pci_dev *dev) { }
713 static inline void pci_restore_aer_state(struct pci_dev *dev) { }
717 int pci_acpi_program_hp_params(struct pci_dev *dev);
718 extern const struct attribute_group pci_dev_acpi_attr_group;
719 void pci_set_acpi_fwnode(struct pci_dev *dev);
720 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
721 bool acpi_pci_power_manageable(struct pci_dev *dev);
722 bool acpi_pci_bridge_d3(struct pci_dev *dev);
723 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
724 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
725 void acpi_pci_refresh_power_state(struct pci_dev *dev);
726 int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
727 bool acpi_pci_need_resume(struct pci_dev *dev);
728 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
730 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
734 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { }
735 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
739 static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
743 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
747 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
751 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
755 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { }
756 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
760 static inline bool acpi_pci_need_resume(struct pci_dev *dev)
764 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
766 return PCI_POWER_ERROR;
770 #ifdef CONFIG_PCIEASPM
771 extern const struct attribute_group aspm_ctrl_attr_group;
774 extern const struct attribute_group pci_dev_reset_method_attr_group;
776 #ifdef CONFIG_X86_INTEL_MID
777 bool pci_use_mid_pm(void);
778 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
779 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
781 static inline bool pci_use_mid_pm(void)
785 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
789 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
796 * Config Address for PCI Configuration Mechanism #1
798 * See PCI Local Bus Specification, Revision 3.0,
799 * Section 3.2.2.3.2, Figure 3-2, p. 50.
802 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
803 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */
804 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
806 #define PCI_CONF1_BUS_MASK 0xff
807 #define PCI_CONF1_DEV_MASK 0x1f
808 #define PCI_CONF1_FUNC_MASK 0x7
809 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
811 #define PCI_CONF1_ENABLE BIT(31)
812 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
813 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
814 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
815 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
817 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
818 (PCI_CONF1_ENABLE | \
819 PCI_CONF1_BUS(bus) | \
820 PCI_CONF1_DEV(dev) | \
821 PCI_CONF1_FUNC(func) | \
825 * Extension of PCI Config Address for accessing extended PCIe registers
827 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
828 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
829 * are used for specifying additional 4 high bits of PCI Express register.
832 #define PCI_CONF1_EXT_REG_SHIFT 16
833 #define PCI_CONF1_EXT_REG_MASK 0xf00
834 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
836 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
837 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
838 PCI_CONF1_EXT_REG(reg))
840 #endif /* DRIVERS_PCI_H */