2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/debugfs.h>
45 #include "mlx5_core.h"
59 LONG_LIST_SIZE = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
60 MLX5_CMD_DATA_BLOCK_SIZE,
61 MED_LIST_SIZE = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
65 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
66 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
67 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
68 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
69 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
70 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
71 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
72 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
73 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
74 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
75 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
78 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
79 struct mlx5_cmd_msg *in,
80 struct mlx5_cmd_msg *out,
81 void *uout, int uout_size,
83 void *context, int page_queue)
85 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
86 struct mlx5_cmd_work_ent *ent;
88 ent = kzalloc(sizeof(*ent), alloc_flags);
90 return ERR_PTR(-ENOMEM);
95 ent->uout_size = uout_size;
97 ent->context = context;
99 ent->page_queue = page_queue;
104 static u8 alloc_token(struct mlx5_cmd *cmd)
108 spin_lock(&cmd->token_lock);
113 spin_unlock(&cmd->token_lock);
118 static int alloc_ent(struct mlx5_cmd *cmd)
123 spin_lock_irqsave(&cmd->alloc_lock, flags);
124 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
125 if (ret < cmd->max_reg_cmds)
126 clear_bit(ret, &cmd->bitmask);
127 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
129 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
132 static void free_ent(struct mlx5_cmd *cmd, int idx)
136 spin_lock_irqsave(&cmd->alloc_lock, flags);
137 set_bit(idx, &cmd->bitmask);
138 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
141 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
143 return cmd->cmd_buf + (idx << cmd->log_stride);
146 static u8 xor8_buf(void *buf, size_t offset, int len)
151 int end = len + offset;
153 for (i = offset; i < end; i++)
159 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
161 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
162 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
164 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
167 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
173 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
175 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
176 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
178 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
179 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
182 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
184 struct mlx5_cmd_mailbox *next = msg->next;
186 int blen = size - min_t(int, sizeof(msg->first.data), size);
187 int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
188 / MLX5_CMD_DATA_BLOCK_SIZE;
191 for (i = 0; i < n && next; i++) {
192 calc_block_sig(next->buf);
197 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
199 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
201 calc_chain_sig(ent->in);
202 calc_chain_sig(ent->out);
206 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
208 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
212 own = ent->lay->status_own;
213 if (!(own & CMD_OWNER_HW)) {
217 usleep_range(5000, 10000);
218 } while (time_before(jiffies, poll_end));
220 ent->ret = -ETIMEDOUT;
223 static void free_cmd(struct mlx5_cmd_work_ent *ent)
229 static int verify_signature(struct mlx5_cmd_work_ent *ent)
231 struct mlx5_cmd_mailbox *next = ent->out->next;
234 int size = ent->out->len;
235 int blen = size - min_t(int, sizeof(ent->out->first.data), size);
236 int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
237 / MLX5_CMD_DATA_BLOCK_SIZE;
240 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
244 for (i = 0; i < n && next; i++) {
245 err = verify_block_sig(next->buf);
255 static void dump_buf(void *buf, int size, int data_only, int offset)
260 for (i = 0; i < size; i += 16) {
261 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
262 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
271 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
272 u32 *synd, u8 *status)
278 case MLX5_CMD_OP_TEARDOWN_HCA:
279 case MLX5_CMD_OP_DISABLE_HCA:
280 case MLX5_CMD_OP_MANAGE_PAGES:
281 case MLX5_CMD_OP_DESTROY_MKEY:
282 case MLX5_CMD_OP_DESTROY_EQ:
283 case MLX5_CMD_OP_DESTROY_CQ:
284 case MLX5_CMD_OP_DESTROY_QP:
285 case MLX5_CMD_OP_DESTROY_PSV:
286 case MLX5_CMD_OP_DESTROY_SRQ:
287 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
288 case MLX5_CMD_OP_DESTROY_DCT:
289 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
290 case MLX5_CMD_OP_DEALLOC_PD:
291 case MLX5_CMD_OP_DEALLOC_UAR:
292 case MLX5_CMD_OP_DETACH_FROM_MCG:
293 case MLX5_CMD_OP_DEALLOC_XRCD:
294 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
295 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
296 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
297 case MLX5_CMD_OP_DESTROY_LAG:
298 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
299 case MLX5_CMD_OP_DESTROY_TIR:
300 case MLX5_CMD_OP_DESTROY_SQ:
301 case MLX5_CMD_OP_DESTROY_RQ:
302 case MLX5_CMD_OP_DESTROY_RMP:
303 case MLX5_CMD_OP_DESTROY_TIS:
304 case MLX5_CMD_OP_DESTROY_RQT:
305 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
306 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
307 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
308 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
309 case MLX5_CMD_OP_2ERR_QP:
310 case MLX5_CMD_OP_2RST_QP:
311 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
312 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
313 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
314 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
315 case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
316 return MLX5_CMD_STAT_OK;
318 case MLX5_CMD_OP_QUERY_HCA_CAP:
319 case MLX5_CMD_OP_QUERY_ADAPTER:
320 case MLX5_CMD_OP_INIT_HCA:
321 case MLX5_CMD_OP_ENABLE_HCA:
322 case MLX5_CMD_OP_QUERY_PAGES:
323 case MLX5_CMD_OP_SET_HCA_CAP:
324 case MLX5_CMD_OP_QUERY_ISSI:
325 case MLX5_CMD_OP_SET_ISSI:
326 case MLX5_CMD_OP_CREATE_MKEY:
327 case MLX5_CMD_OP_QUERY_MKEY:
328 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
329 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
330 case MLX5_CMD_OP_CREATE_EQ:
331 case MLX5_CMD_OP_QUERY_EQ:
332 case MLX5_CMD_OP_GEN_EQE:
333 case MLX5_CMD_OP_CREATE_CQ:
334 case MLX5_CMD_OP_QUERY_CQ:
335 case MLX5_CMD_OP_MODIFY_CQ:
336 case MLX5_CMD_OP_CREATE_QP:
337 case MLX5_CMD_OP_RST2INIT_QP:
338 case MLX5_CMD_OP_INIT2RTR_QP:
339 case MLX5_CMD_OP_RTR2RTS_QP:
340 case MLX5_CMD_OP_RTS2RTS_QP:
341 case MLX5_CMD_OP_SQERR2RTS_QP:
342 case MLX5_CMD_OP_QUERY_QP:
343 case MLX5_CMD_OP_SQD_RTS_QP:
344 case MLX5_CMD_OP_INIT2INIT_QP:
345 case MLX5_CMD_OP_CREATE_PSV:
346 case MLX5_CMD_OP_CREATE_SRQ:
347 case MLX5_CMD_OP_QUERY_SRQ:
348 case MLX5_CMD_OP_ARM_RQ:
349 case MLX5_CMD_OP_CREATE_XRC_SRQ:
350 case MLX5_CMD_OP_QUERY_XRC_SRQ:
351 case MLX5_CMD_OP_ARM_XRC_SRQ:
352 case MLX5_CMD_OP_CREATE_DCT:
353 case MLX5_CMD_OP_DRAIN_DCT:
354 case MLX5_CMD_OP_QUERY_DCT:
355 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
356 case MLX5_CMD_OP_QUERY_VPORT_STATE:
357 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
358 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
359 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
360 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
361 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
362 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
363 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
364 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
365 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
366 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
367 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
368 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
369 case MLX5_CMD_OP_QUERY_Q_COUNTER:
370 case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
371 case MLX5_CMD_OP_QUERY_RATE_LIMIT:
372 case MLX5_CMD_OP_ALLOC_PD:
373 case MLX5_CMD_OP_ALLOC_UAR:
374 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
375 case MLX5_CMD_OP_ACCESS_REG:
376 case MLX5_CMD_OP_ATTACH_TO_MCG:
377 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
378 case MLX5_CMD_OP_MAD_IFC:
379 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
380 case MLX5_CMD_OP_SET_MAD_DEMUX:
381 case MLX5_CMD_OP_NOP:
382 case MLX5_CMD_OP_ALLOC_XRCD:
383 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
384 case MLX5_CMD_OP_QUERY_CONG_STATUS:
385 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
386 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
387 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
388 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
389 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
390 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
391 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
392 case MLX5_CMD_OP_CREATE_LAG:
393 case MLX5_CMD_OP_MODIFY_LAG:
394 case MLX5_CMD_OP_QUERY_LAG:
395 case MLX5_CMD_OP_CREATE_VPORT_LAG:
396 case MLX5_CMD_OP_CREATE_TIR:
397 case MLX5_CMD_OP_MODIFY_TIR:
398 case MLX5_CMD_OP_QUERY_TIR:
399 case MLX5_CMD_OP_CREATE_SQ:
400 case MLX5_CMD_OP_MODIFY_SQ:
401 case MLX5_CMD_OP_QUERY_SQ:
402 case MLX5_CMD_OP_CREATE_RQ:
403 case MLX5_CMD_OP_MODIFY_RQ:
404 case MLX5_CMD_OP_QUERY_RQ:
405 case MLX5_CMD_OP_CREATE_RMP:
406 case MLX5_CMD_OP_MODIFY_RMP:
407 case MLX5_CMD_OP_QUERY_RMP:
408 case MLX5_CMD_OP_CREATE_TIS:
409 case MLX5_CMD_OP_MODIFY_TIS:
410 case MLX5_CMD_OP_QUERY_TIS:
411 case MLX5_CMD_OP_CREATE_RQT:
412 case MLX5_CMD_OP_MODIFY_RQT:
413 case MLX5_CMD_OP_QUERY_RQT:
415 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
416 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
417 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
418 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
420 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
421 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
422 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
423 case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
424 *status = MLX5_DRIVER_STATUS_ABORTED;
425 *synd = MLX5_DRIVER_SYND;
428 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
433 const char *mlx5_command_str(int command)
435 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
438 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
439 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
440 MLX5_COMMAND_STR_CASE(INIT_HCA);
441 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
442 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
443 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
444 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
445 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
446 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
447 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
448 MLX5_COMMAND_STR_CASE(SET_ISSI);
449 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
450 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
451 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
452 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
453 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
454 MLX5_COMMAND_STR_CASE(CREATE_EQ);
455 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
456 MLX5_COMMAND_STR_CASE(QUERY_EQ);
457 MLX5_COMMAND_STR_CASE(GEN_EQE);
458 MLX5_COMMAND_STR_CASE(CREATE_CQ);
459 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
460 MLX5_COMMAND_STR_CASE(QUERY_CQ);
461 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
462 MLX5_COMMAND_STR_CASE(CREATE_QP);
463 MLX5_COMMAND_STR_CASE(DESTROY_QP);
464 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
465 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
466 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
467 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
468 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
469 MLX5_COMMAND_STR_CASE(2ERR_QP);
470 MLX5_COMMAND_STR_CASE(2RST_QP);
471 MLX5_COMMAND_STR_CASE(QUERY_QP);
472 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
473 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
474 MLX5_COMMAND_STR_CASE(CREATE_PSV);
475 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
476 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
477 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
478 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
479 MLX5_COMMAND_STR_CASE(ARM_RQ);
480 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
481 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
482 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
483 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
484 MLX5_COMMAND_STR_CASE(CREATE_DCT);
485 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
486 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
487 MLX5_COMMAND_STR_CASE(QUERY_DCT);
488 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
489 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
490 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
491 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
492 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
493 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
494 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
495 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
496 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
497 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
498 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
499 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
500 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
501 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
502 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
503 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
504 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
505 MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
506 MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
507 MLX5_COMMAND_STR_CASE(ALLOC_PD);
508 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
509 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
510 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
511 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
512 MLX5_COMMAND_STR_CASE(ACCESS_REG);
513 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
514 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
515 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
516 MLX5_COMMAND_STR_CASE(MAD_IFC);
517 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
518 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
519 MLX5_COMMAND_STR_CASE(NOP);
520 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
521 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
522 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
523 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
524 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
525 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
526 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
527 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
528 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
529 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
530 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
531 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
532 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
533 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
534 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
535 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
536 MLX5_COMMAND_STR_CASE(CREATE_LAG);
537 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
538 MLX5_COMMAND_STR_CASE(QUERY_LAG);
539 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
540 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
541 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
542 MLX5_COMMAND_STR_CASE(CREATE_TIR);
543 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
544 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
545 MLX5_COMMAND_STR_CASE(QUERY_TIR);
546 MLX5_COMMAND_STR_CASE(CREATE_SQ);
547 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
548 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
549 MLX5_COMMAND_STR_CASE(QUERY_SQ);
550 MLX5_COMMAND_STR_CASE(CREATE_RQ);
551 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
552 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
553 MLX5_COMMAND_STR_CASE(QUERY_RQ);
554 MLX5_COMMAND_STR_CASE(CREATE_RMP);
555 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
556 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
557 MLX5_COMMAND_STR_CASE(QUERY_RMP);
558 MLX5_COMMAND_STR_CASE(CREATE_TIS);
559 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
560 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
561 MLX5_COMMAND_STR_CASE(QUERY_TIS);
562 MLX5_COMMAND_STR_CASE(CREATE_RQT);
563 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
564 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
565 MLX5_COMMAND_STR_CASE(QUERY_RQT);
566 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
567 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
568 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
569 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
570 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
571 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
572 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
573 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
574 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
575 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
576 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
577 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
578 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
579 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
580 MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
581 MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
582 default: return "unknown command opcode";
586 static const char *cmd_status_str(u8 status)
589 case MLX5_CMD_STAT_OK:
591 case MLX5_CMD_STAT_INT_ERR:
592 return "internal error";
593 case MLX5_CMD_STAT_BAD_OP_ERR:
594 return "bad operation";
595 case MLX5_CMD_STAT_BAD_PARAM_ERR:
596 return "bad parameter";
597 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
598 return "bad system state";
599 case MLX5_CMD_STAT_BAD_RES_ERR:
600 return "bad resource";
601 case MLX5_CMD_STAT_RES_BUSY:
602 return "resource busy";
603 case MLX5_CMD_STAT_LIM_ERR:
604 return "limits exceeded";
605 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
606 return "bad resource state";
607 case MLX5_CMD_STAT_IX_ERR:
609 case MLX5_CMD_STAT_NO_RES_ERR:
610 return "no resources";
611 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
612 return "bad input length";
613 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
614 return "bad output length";
615 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
616 return "bad QP state";
617 case MLX5_CMD_STAT_BAD_PKT_ERR:
618 return "bad packet (discarded)";
619 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
620 return "bad size too many outstanding CQEs";
622 return "unknown status";
626 static int cmd_status_to_err(u8 status)
629 case MLX5_CMD_STAT_OK: return 0;
630 case MLX5_CMD_STAT_INT_ERR: return -EIO;
631 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
632 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
633 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
634 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
635 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
636 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
637 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
638 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
639 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
640 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
641 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
642 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
643 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
644 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
645 default: return -EIO;
649 struct mlx5_ifc_mbox_out_bits {
651 u8 reserved_at_8[0x18];
655 u8 reserved_at_40[0x40];
658 struct mlx5_ifc_mbox_in_bits {
660 u8 reserved_at_10[0x10];
662 u8 reserved_at_20[0x10];
665 u8 reserved_at_40[0x40];
668 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
670 *status = MLX5_GET(mbox_out, out, status);
671 *syndrome = MLX5_GET(mbox_out, out, syndrome);
674 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
681 mlx5_cmd_mbox_status(out, &status, &syndrome);
685 opcode = MLX5_GET(mbox_in, in, opcode);
686 op_mod = MLX5_GET(mbox_in, in, op_mod);
689 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
690 mlx5_command_str(opcode),
692 cmd_status_str(status),
696 return cmd_status_to_err(status);
699 static void dump_command(struct mlx5_core_dev *dev,
700 struct mlx5_cmd_work_ent *ent, int input)
702 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
703 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
704 struct mlx5_cmd_mailbox *next = msg->next;
709 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
712 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
713 "dump command data %s(0x%x) %s\n",
714 mlx5_command_str(op), op,
715 input ? "INPUT" : "OUTPUT");
717 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
718 mlx5_command_str(op), op,
719 input ? "INPUT" : "OUTPUT");
723 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
724 offset += sizeof(ent->lay->in);
726 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
727 offset += sizeof(ent->lay->out);
730 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
731 offset += sizeof(*ent->lay);
734 while (next && offset < msg->len) {
736 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
737 dump_buf(next->buf, dump_len, 1, offset);
738 offset += MLX5_CMD_DATA_BLOCK_SIZE;
740 mlx5_core_dbg(dev, "command block:\n");
741 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
742 offset += sizeof(struct mlx5_cmd_prot_block);
751 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
753 return MLX5_GET(mbox_in, in->first.data, opcode);
756 static void cb_timeout_handler(struct work_struct *work)
758 struct delayed_work *dwork = container_of(work, struct delayed_work,
760 struct mlx5_cmd_work_ent *ent = container_of(dwork,
761 struct mlx5_cmd_work_ent,
763 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
766 ent->ret = -ETIMEDOUT;
767 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
768 mlx5_command_str(msg_to_opcode(ent->in)),
769 msg_to_opcode(ent->in));
770 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
773 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
774 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
775 struct mlx5_cmd_msg *msg);
777 static void cmd_work_handler(struct work_struct *work)
779 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
780 struct mlx5_cmd *cmd = ent->cmd;
781 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
782 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
783 struct mlx5_cmd_layout *lay;
784 struct semaphore *sem;
789 complete(&ent->handling);
790 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
792 if (!ent->page_queue) {
793 alloc_ret = alloc_ent(cmd);
796 ent->callback(-EAGAIN, ent->context);
797 mlx5_free_cmd_msg(dev, ent->out);
798 free_msg(dev, ent->in);
802 complete(&ent->done);
804 mlx5_core_err(dev, "failed to allocate command entry\n");
808 ent->idx = alloc_ret;
810 ent->idx = cmd->max_reg_cmds;
811 spin_lock_irqsave(&cmd->alloc_lock, flags);
812 clear_bit(ent->idx, &cmd->bitmask);
813 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
816 cmd->ent_arr[ent->idx] = ent;
817 lay = get_inst(cmd, ent->idx);
819 memset(lay, 0, sizeof(*lay));
820 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
821 ent->op = be32_to_cpu(lay->in[0]) >> 16;
823 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
824 lay->inlen = cpu_to_be32(ent->in->len);
826 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
827 lay->outlen = cpu_to_be32(ent->out->len);
828 lay->type = MLX5_PCI_CMD_XPORT;
829 lay->token = ent->token;
830 lay->status_own = CMD_OWNER_HW;
831 set_signature(ent, !cmd->checksum_disabled);
832 dump_command(dev, ent, 1);
833 ent->ts1 = ktime_get_ns();
834 cmd_mode = cmd->mode;
837 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
838 set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
840 /* Skip sending command to fw if internal error */
841 if (pci_channel_offline(dev->pdev) ||
842 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
846 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
847 MLX5_SET(mbox_out, ent->out, status, status);
848 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
850 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
851 /* no doorbell, no need to keep the entry */
852 free_ent(cmd, ent->idx);
858 /* ring doorbell after the descriptor is valid */
859 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
861 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
863 /* if not in polling don't use ent after this point */
864 if (cmd_mode == CMD_MODE_POLLING) {
866 /* make sure we read the descriptor after ownership is SW */
868 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
872 static const char *deliv_status_to_str(u8 status)
875 case MLX5_CMD_DELIVERY_STAT_OK:
877 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
878 return "signature error";
879 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
880 return "token error";
881 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
882 return "bad block number";
883 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
884 return "output pointer not aligned to block size";
885 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
886 return "input pointer not aligned to block size";
887 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
888 return "firmware internal error";
889 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
890 return "command input length error";
891 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
892 return "command ouput length error";
893 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
894 return "reserved fields not cleared";
895 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
896 return "bad command descriptor type";
898 return "unknown status code";
902 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
904 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
905 struct mlx5_cmd *cmd = &dev->cmd;
908 if (!wait_for_completion_timeout(&ent->handling, timeout) &&
909 cancel_work_sync(&ent->work)) {
910 ent->ret = -ECANCELED;
914 if (cmd->mode == CMD_MODE_POLLING) {
915 wait_for_completion(&ent->done);
916 } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
917 ent->ret = -ETIMEDOUT;
918 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
924 if (err == -ETIMEDOUT) {
925 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
926 mlx5_command_str(msg_to_opcode(ent->in)),
927 msg_to_opcode(ent->in));
928 } else if (err == -ECANCELED) {
929 mlx5_core_warn(dev, "%s(0x%x) canceled on out of queue timeout.\n",
930 mlx5_command_str(msg_to_opcode(ent->in)),
931 msg_to_opcode(ent->in));
933 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
934 err, deliv_status_to_str(ent->status), ent->status);
940 * 1. Callback functions may not sleep
941 * 2. page queue commands do not support asynchrous completion
943 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
944 struct mlx5_cmd_msg *out, void *uout, int uout_size,
945 mlx5_cmd_cbk_t callback,
946 void *context, int page_queue, u8 *status,
949 struct mlx5_cmd *cmd = &dev->cmd;
950 struct mlx5_cmd_work_ent *ent;
951 struct mlx5_cmd_stats *stats;
956 if (callback && page_queue)
959 ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
966 init_completion(&ent->handling);
968 init_completion(&ent->done);
970 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
971 INIT_WORK(&ent->work, cmd_work_handler);
973 cmd_work_handler(&ent->work);
974 } else if (!queue_work(cmd->wq, &ent->work)) {
975 mlx5_core_warn(dev, "failed to queue work\n");
983 err = wait_func(dev, ent);
984 if (err == -ETIMEDOUT)
986 if (err == -ECANCELED)
989 ds = ent->ts2 - ent->ts1;
990 op = MLX5_GET(mbox_in, in->first.data, opcode);
991 if (op < ARRAY_SIZE(cmd->stats)) {
992 stats = &cmd->stats[op];
993 spin_lock_irq(&stats->lock);
996 spin_unlock_irq(&stats->lock);
998 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
999 "fw exec time for %s is %lld nsec\n",
1000 mlx5_command_str(op), ds);
1001 *status = ent->status;
1009 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1010 size_t count, loff_t *pos)
1012 struct mlx5_core_dev *dev = filp->private_data;
1013 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1017 if (!dbg->in_msg || !dbg->out_msg)
1020 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
1023 lbuf[sizeof(lbuf) - 1] = 0;
1025 if (strcmp(lbuf, "go"))
1028 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1030 return err ? err : count;
1034 static const struct file_operations fops = {
1035 .owner = THIS_MODULE,
1036 .open = simple_open,
1040 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1043 struct mlx5_cmd_prot_block *block;
1044 struct mlx5_cmd_mailbox *next;
1050 copy = min_t(int, size, sizeof(to->first.data));
1051 memcpy(to->first.data, from, copy);
1062 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1064 memcpy(block->data, from, copy);
1067 block->token = token;
1074 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1076 struct mlx5_cmd_prot_block *block;
1077 struct mlx5_cmd_mailbox *next;
1083 copy = min_t(int, size, sizeof(from->first.data));
1084 memcpy(to, from->first.data, copy);
1095 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1098 memcpy(to, block->data, copy);
1107 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1110 struct mlx5_cmd_mailbox *mailbox;
1112 mailbox = kmalloc(sizeof(*mailbox), flags);
1114 return ERR_PTR(-ENOMEM);
1116 mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
1118 if (!mailbox->buf) {
1119 mlx5_core_dbg(dev, "failed allocation\n");
1121 return ERR_PTR(-ENOMEM);
1123 memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
1124 mailbox->next = NULL;
1129 static void free_cmd_box(struct mlx5_core_dev *dev,
1130 struct mlx5_cmd_mailbox *mailbox)
1132 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1136 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1137 gfp_t flags, int size,
1140 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1141 struct mlx5_cmd_prot_block *block;
1142 struct mlx5_cmd_msg *msg;
1148 msg = kzalloc(sizeof(*msg), flags);
1150 return ERR_PTR(-ENOMEM);
1152 blen = size - min_t(int, sizeof(msg->first.data), size);
1153 n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
1155 for (i = 0; i < n; i++) {
1156 tmp = alloc_cmd_box(dev, flags);
1158 mlx5_core_warn(dev, "failed allocating block\n");
1165 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1166 block->block_num = cpu_to_be32(n - i - 1);
1167 block->token = token;
1177 free_cmd_box(dev, head);
1182 return ERR_PTR(err);
1185 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1186 struct mlx5_cmd_msg *msg)
1188 struct mlx5_cmd_mailbox *head = msg->next;
1189 struct mlx5_cmd_mailbox *next;
1193 free_cmd_box(dev, head);
1199 static ssize_t data_write(struct file *filp, const char __user *buf,
1200 size_t count, loff_t *pos)
1202 struct mlx5_core_dev *dev = filp->private_data;
1203 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1212 ptr = memdup_user(buf, count);
1214 return PTR_ERR(ptr);
1223 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1226 struct mlx5_core_dev *dev = filp->private_data;
1227 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1236 copy = min_t(int, count, dbg->outlen);
1237 if (copy_to_user(buf, dbg->out_msg, copy))
1245 static const struct file_operations dfops = {
1246 .owner = THIS_MODULE,
1247 .open = simple_open,
1248 .write = data_write,
1252 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1255 struct mlx5_core_dev *dev = filp->private_data;
1256 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1263 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1267 if (copy_to_user(buf, &outlen, err))
1275 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1276 size_t count, loff_t *pos)
1278 struct mlx5_core_dev *dev = filp->private_data;
1279 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1280 char outlen_str[8] = {0};
1285 if (*pos != 0 || count > 6)
1288 kfree(dbg->out_msg);
1289 dbg->out_msg = NULL;
1292 if (copy_from_user(outlen_str, buf, count))
1295 err = sscanf(outlen_str, "%d", &outlen);
1299 ptr = kzalloc(outlen, GFP_KERNEL);
1304 dbg->outlen = outlen;
1311 static const struct file_operations olfops = {
1312 .owner = THIS_MODULE,
1313 .open = simple_open,
1314 .write = outlen_write,
1315 .read = outlen_read,
1318 static void set_wqname(struct mlx5_core_dev *dev)
1320 struct mlx5_cmd *cmd = &dev->cmd;
1322 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1323 dev_name(&dev->pdev->dev));
1326 static void clean_debug_files(struct mlx5_core_dev *dev)
1328 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1330 if (!mlx5_debugfs_root)
1333 mlx5_cmdif_debugfs_cleanup(dev);
1334 debugfs_remove_recursive(dbg->dbg_root);
1337 static int create_debugfs_files(struct mlx5_core_dev *dev)
1339 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1342 if (!mlx5_debugfs_root)
1345 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1349 dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1354 dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1359 dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1361 if (!dbg->dbg_outlen)
1364 dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1366 if (!dbg->dbg_status)
1369 dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1373 mlx5_cmdif_debugfs_init(dev);
1378 clean_debug_files(dev);
1382 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1384 struct mlx5_cmd *cmd = &dev->cmd;
1387 for (i = 0; i < cmd->max_reg_cmds; i++)
1389 down(&cmd->pages_sem);
1393 up(&cmd->pages_sem);
1394 for (i = 0; i < cmd->max_reg_cmds; i++)
1398 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1400 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1403 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1405 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1408 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1410 unsigned long flags;
1413 spin_lock_irqsave(&msg->cache->lock, flags);
1414 list_add_tail(&msg->list, &msg->cache->head);
1415 spin_unlock_irqrestore(&msg->cache->lock, flags);
1417 mlx5_free_cmd_msg(dev, msg);
1421 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1423 struct mlx5_cmd *cmd = &dev->cmd;
1424 struct mlx5_cmd_work_ent *ent;
1425 mlx5_cmd_cbk_t callback;
1430 struct mlx5_cmd_stats *stats;
1431 unsigned long flags;
1432 unsigned long vector;
1434 /* there can be at most 32 command queues */
1435 vector = vec & 0xffffffff;
1436 for (i = 0; i < (1 << cmd->log_sz); i++) {
1437 if (test_bit(i, &vector)) {
1438 struct semaphore *sem;
1440 ent = cmd->ent_arr[i];
1442 /* if we already completed the command, ignore it */
1443 if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1445 /* only real completion can free the cmd slot */
1447 mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1449 free_ent(cmd, ent->idx);
1456 cancel_delayed_work(&ent->cb_timeout_work);
1457 if (ent->page_queue)
1458 sem = &cmd->pages_sem;
1461 ent->ts2 = ktime_get_ns();
1462 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1463 dump_command(dev, ent, 0);
1465 if (!cmd->checksum_disabled)
1466 ent->ret = verify_signature(ent);
1469 if (vec & MLX5_TRIGGERED_CMD_COMP)
1470 ent->status = MLX5_DRIVER_STATUS_ABORTED;
1472 ent->status = ent->lay->status_own >> 1;
1474 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1475 ent->ret, deliv_status_to_str(ent->status), ent->status);
1478 /* only real completion will free the entry slot */
1480 free_ent(cmd, ent->idx);
1482 if (ent->callback) {
1483 ds = ent->ts2 - ent->ts1;
1484 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1485 stats = &cmd->stats[ent->op];
1486 spin_lock_irqsave(&stats->lock, flags);
1489 spin_unlock_irqrestore(&stats->lock, flags);
1492 callback = ent->callback;
1493 context = ent->context;
1496 err = mlx5_copy_from_msg(ent->uout,
1500 err = err ? err : mlx5_cmd_check(dev,
1501 ent->in->first.data,
1505 mlx5_free_cmd_msg(dev, ent->out);
1506 free_msg(dev, ent->in);
1508 err = err ? err : ent->status;
1511 callback(err, context);
1513 complete(&ent->done);
1519 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1521 static int status_to_err(u8 status)
1523 return status ? -1 : 0; /* TBD more meaningful codes */
1526 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1529 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1530 struct mlx5_cmd *cmd = &dev->cmd;
1531 struct cache_ent *ent = NULL;
1533 if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1534 ent = &cmd->cache.large;
1535 else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1536 ent = &cmd->cache.med;
1539 spin_lock_irq(&ent->lock);
1540 if (!list_empty(&ent->head)) {
1541 msg = list_entry(ent->head.next, typeof(*msg), list);
1542 /* For cached lists, we must explicitly state what is
1546 list_del(&msg->list);
1548 spin_unlock_irq(&ent->lock);
1552 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1557 static int is_manage_pages(void *in)
1559 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1562 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1563 int out_size, mlx5_cmd_cbk_t callback, void *context)
1565 struct mlx5_cmd_msg *inb;
1566 struct mlx5_cmd_msg *outb;
1574 if (pci_channel_offline(dev->pdev) ||
1575 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1576 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1578 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1579 MLX5_SET(mbox_out, out, status, status);
1580 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1584 pages_queue = is_manage_pages(in);
1585 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1587 inb = alloc_msg(dev, in_size, gfp);
1593 token = alloc_token(&dev->cmd);
1595 err = mlx5_copy_to_msg(inb, in, in_size, token);
1597 mlx5_core_warn(dev, "err %d\n", err);
1601 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1603 err = PTR_ERR(outb);
1607 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1608 pages_queue, &status, token);
1612 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1614 err = status_to_err(status);
1619 err = mlx5_copy_from_msg(out, outb, out_size);
1623 mlx5_free_cmd_msg(dev, outb);
1631 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1636 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1637 return err ? : mlx5_cmd_check(dev, in, out);
1639 EXPORT_SYMBOL(mlx5_cmd_exec);
1641 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1642 void *out, int out_size, mlx5_cmd_cbk_t callback,
1645 return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1647 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1649 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1651 struct mlx5_cmd *cmd = &dev->cmd;
1652 struct mlx5_cmd_msg *msg;
1653 struct mlx5_cmd_msg *n;
1655 list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1656 list_del(&msg->list);
1657 mlx5_free_cmd_msg(dev, msg);
1660 list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1661 list_del(&msg->list);
1662 mlx5_free_cmd_msg(dev, msg);
1666 static int create_msg_cache(struct mlx5_core_dev *dev)
1668 struct mlx5_cmd *cmd = &dev->cmd;
1669 struct mlx5_cmd_msg *msg;
1673 spin_lock_init(&cmd->cache.large.lock);
1674 INIT_LIST_HEAD(&cmd->cache.large.head);
1675 spin_lock_init(&cmd->cache.med.lock);
1676 INIT_LIST_HEAD(&cmd->cache.med.head);
1678 for (i = 0; i < NUM_LONG_LISTS; i++) {
1679 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE, 0);
1684 msg->cache = &cmd->cache.large;
1685 list_add_tail(&msg->list, &cmd->cache.large.head);
1688 for (i = 0; i < NUM_MED_LISTS; i++) {
1689 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE, 0);
1694 msg->cache = &cmd->cache.med;
1695 list_add_tail(&msg->list, &cmd->cache.med.head);
1701 destroy_msg_cache(dev);
1705 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1707 struct device *ddev = &dev->pdev->dev;
1709 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1710 &cmd->alloc_dma, GFP_KERNEL);
1711 if (!cmd->cmd_alloc_buf)
1714 /* make sure it is aligned to 4K */
1715 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1716 cmd->cmd_buf = cmd->cmd_alloc_buf;
1717 cmd->dma = cmd->alloc_dma;
1718 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1722 dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1724 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1725 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1726 &cmd->alloc_dma, GFP_KERNEL);
1727 if (!cmd->cmd_alloc_buf)
1730 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1731 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1732 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1736 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1738 struct device *ddev = &dev->pdev->dev;
1740 dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1744 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1746 int size = sizeof(struct mlx5_cmd_prot_block);
1747 int align = roundup_pow_of_two(size);
1748 struct mlx5_cmd *cmd = &dev->cmd;
1754 memset(cmd, 0, sizeof(*cmd));
1755 cmd_if_rev = cmdif_rev(dev);
1756 if (cmd_if_rev != CMD_IF_REV) {
1757 dev_err(&dev->pdev->dev,
1758 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1759 CMD_IF_REV, cmd_if_rev);
1763 cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1767 err = alloc_cmd_page(dev, cmd);
1771 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1772 cmd->log_sz = cmd_l >> 4 & 0xf;
1773 cmd->log_stride = cmd_l & 0xf;
1774 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1775 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1781 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1782 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1787 cmd->checksum_disabled = 1;
1788 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1789 cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1791 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1792 if (cmd->cmdif_rev > CMD_IF_REV) {
1793 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1794 CMD_IF_REV, cmd->cmdif_rev);
1799 spin_lock_init(&cmd->alloc_lock);
1800 spin_lock_init(&cmd->token_lock);
1801 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1802 spin_lock_init(&cmd->stats[i].lock);
1804 sema_init(&cmd->sem, cmd->max_reg_cmds);
1805 sema_init(&cmd->pages_sem, 1);
1807 cmd_h = (u32)((u64)(cmd->dma) >> 32);
1808 cmd_l = (u32)(cmd->dma);
1809 if (cmd_l & 0xfff) {
1810 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1815 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1816 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1818 /* Make sure firmware sees the complete address before we proceed */
1821 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1823 cmd->mode = CMD_MODE_POLLING;
1825 err = create_msg_cache(dev);
1827 dev_err(&dev->pdev->dev, "failed to create command cache\n");
1832 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1834 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1839 err = create_debugfs_files(dev);
1848 destroy_workqueue(cmd->wq);
1851 destroy_msg_cache(dev);
1854 free_cmd_page(dev, cmd);
1857 pci_pool_destroy(cmd->pool);
1861 EXPORT_SYMBOL(mlx5_cmd_init);
1863 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1865 struct mlx5_cmd *cmd = &dev->cmd;
1867 clean_debug_files(dev);
1868 destroy_workqueue(cmd->wq);
1869 destroy_msg_cache(dev);
1870 free_cmd_page(dev, cmd);
1871 pci_pool_destroy(cmd->pool);
1873 EXPORT_SYMBOL(mlx5_cmd_cleanup);