1 // SPDX-License-Identifier: GPL-2.0
5 // Support for Samsung S5PV210 and Exynos HW acceleration.
7 // Copyright (C) 2011 NetUP Inc. All rights reserved.
8 // Copyright (c) 2017 Samsung Electronics Co., Ltd. All rights reserved.
10 // Hash part based on omap-sham.c driver.
12 #include <linux/clk.h>
13 #include <linux/crypto.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/scatterlist.h>
26 #include <crypto/ctr.h>
27 #include <crypto/aes.h>
28 #include <crypto/algapi.h>
29 #include <crypto/scatterwalk.h>
31 #include <crypto/hash.h>
32 #include <crypto/md5.h>
33 #include <crypto/sha.h>
34 #include <crypto/internal/hash.h>
36 #define _SBF(s, v) ((v) << (s))
38 /* Feed control registers */
39 #define SSS_REG_FCINTSTAT 0x0000
40 #define SSS_FCINTSTAT_HPARTINT BIT(7)
41 #define SSS_FCINTSTAT_HDONEINT BIT(5)
42 #define SSS_FCINTSTAT_BRDMAINT BIT(3)
43 #define SSS_FCINTSTAT_BTDMAINT BIT(2)
44 #define SSS_FCINTSTAT_HRDMAINT BIT(1)
45 #define SSS_FCINTSTAT_PKDMAINT BIT(0)
47 #define SSS_REG_FCINTENSET 0x0004
48 #define SSS_FCINTENSET_HPARTINTENSET BIT(7)
49 #define SSS_FCINTENSET_HDONEINTENSET BIT(5)
50 #define SSS_FCINTENSET_BRDMAINTENSET BIT(3)
51 #define SSS_FCINTENSET_BTDMAINTENSET BIT(2)
52 #define SSS_FCINTENSET_HRDMAINTENSET BIT(1)
53 #define SSS_FCINTENSET_PKDMAINTENSET BIT(0)
55 #define SSS_REG_FCINTENCLR 0x0008
56 #define SSS_FCINTENCLR_HPARTINTENCLR BIT(7)
57 #define SSS_FCINTENCLR_HDONEINTENCLR BIT(5)
58 #define SSS_FCINTENCLR_BRDMAINTENCLR BIT(3)
59 #define SSS_FCINTENCLR_BTDMAINTENCLR BIT(2)
60 #define SSS_FCINTENCLR_HRDMAINTENCLR BIT(1)
61 #define SSS_FCINTENCLR_PKDMAINTENCLR BIT(0)
63 #define SSS_REG_FCINTPEND 0x000C
64 #define SSS_FCINTPEND_HPARTINTP BIT(7)
65 #define SSS_FCINTPEND_HDONEINTP BIT(5)
66 #define SSS_FCINTPEND_BRDMAINTP BIT(3)
67 #define SSS_FCINTPEND_BTDMAINTP BIT(2)
68 #define SSS_FCINTPEND_HRDMAINTP BIT(1)
69 #define SSS_FCINTPEND_PKDMAINTP BIT(0)
71 #define SSS_REG_FCFIFOSTAT 0x0010
72 #define SSS_FCFIFOSTAT_BRFIFOFUL BIT(7)
73 #define SSS_FCFIFOSTAT_BRFIFOEMP BIT(6)
74 #define SSS_FCFIFOSTAT_BTFIFOFUL BIT(5)
75 #define SSS_FCFIFOSTAT_BTFIFOEMP BIT(4)
76 #define SSS_FCFIFOSTAT_HRFIFOFUL BIT(3)
77 #define SSS_FCFIFOSTAT_HRFIFOEMP BIT(2)
78 #define SSS_FCFIFOSTAT_PKFIFOFUL BIT(1)
79 #define SSS_FCFIFOSTAT_PKFIFOEMP BIT(0)
81 #define SSS_REG_FCFIFOCTRL 0x0014
82 #define SSS_FCFIFOCTRL_DESSEL BIT(2)
83 #define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00)
84 #define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01)
85 #define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02)
86 #define SSS_HASHIN_MASK _SBF(0, 0x03)
88 #define SSS_REG_FCBRDMAS 0x0020
89 #define SSS_REG_FCBRDMAL 0x0024
90 #define SSS_REG_FCBRDMAC 0x0028
91 #define SSS_FCBRDMAC_BYTESWAP BIT(1)
92 #define SSS_FCBRDMAC_FLUSH BIT(0)
94 #define SSS_REG_FCBTDMAS 0x0030
95 #define SSS_REG_FCBTDMAL 0x0034
96 #define SSS_REG_FCBTDMAC 0x0038
97 #define SSS_FCBTDMAC_BYTESWAP BIT(1)
98 #define SSS_FCBTDMAC_FLUSH BIT(0)
100 #define SSS_REG_FCHRDMAS 0x0040
101 #define SSS_REG_FCHRDMAL 0x0044
102 #define SSS_REG_FCHRDMAC 0x0048
103 #define SSS_FCHRDMAC_BYTESWAP BIT(1)
104 #define SSS_FCHRDMAC_FLUSH BIT(0)
106 #define SSS_REG_FCPKDMAS 0x0050
107 #define SSS_REG_FCPKDMAL 0x0054
108 #define SSS_REG_FCPKDMAC 0x0058
109 #define SSS_FCPKDMAC_BYTESWAP BIT(3)
110 #define SSS_FCPKDMAC_DESCEND BIT(2)
111 #define SSS_FCPKDMAC_TRANSMIT BIT(1)
112 #define SSS_FCPKDMAC_FLUSH BIT(0)
114 #define SSS_REG_FCPKDMAO 0x005C
117 #define SSS_REG_AES_CONTROL 0x00
118 #define SSS_AES_BYTESWAP_DI BIT(11)
119 #define SSS_AES_BYTESWAP_DO BIT(10)
120 #define SSS_AES_BYTESWAP_IV BIT(9)
121 #define SSS_AES_BYTESWAP_CNT BIT(8)
122 #define SSS_AES_BYTESWAP_KEY BIT(7)
123 #define SSS_AES_KEY_CHANGE_MODE BIT(6)
124 #define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00)
125 #define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01)
126 #define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02)
127 #define SSS_AES_FIFO_MODE BIT(3)
128 #define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00)
129 #define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01)
130 #define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
131 #define SSS_AES_MODE_DECRYPT BIT(0)
133 #define SSS_REG_AES_STATUS 0x04
134 #define SSS_AES_BUSY BIT(2)
135 #define SSS_AES_INPUT_READY BIT(1)
136 #define SSS_AES_OUTPUT_READY BIT(0)
138 #define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2))
139 #define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2))
140 #define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2))
141 #define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2))
142 #define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2))
144 #define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
145 #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
146 #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
148 #define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg)
149 #define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
150 SSS_AES_REG(dev, reg))
152 /* HW engine modes */
153 #define FLAGS_AES_DECRYPT BIT(0)
154 #define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
155 #define FLAGS_AES_CBC _SBF(1, 0x01)
156 #define FLAGS_AES_CTR _SBF(1, 0x02)
158 #define AES_KEY_LEN 16
159 #define CRYPTO_QUEUE_LEN 1
162 #define SSS_REG_HASH_CTRL 0x00
164 #define SSS_HASH_USER_IV_EN BIT(5)
165 #define SSS_HASH_INIT_BIT BIT(4)
166 #define SSS_HASH_ENGINE_SHA1 _SBF(1, 0x00)
167 #define SSS_HASH_ENGINE_MD5 _SBF(1, 0x01)
168 #define SSS_HASH_ENGINE_SHA256 _SBF(1, 0x02)
170 #define SSS_HASH_ENGINE_MASK _SBF(1, 0x03)
172 #define SSS_REG_HASH_CTRL_PAUSE 0x04
174 #define SSS_HASH_PAUSE BIT(0)
176 #define SSS_REG_HASH_CTRL_FIFO 0x08
178 #define SSS_HASH_FIFO_MODE_DMA BIT(0)
179 #define SSS_HASH_FIFO_MODE_CPU 0
181 #define SSS_REG_HASH_CTRL_SWAP 0x0C
183 #define SSS_HASH_BYTESWAP_DI BIT(3)
184 #define SSS_HASH_BYTESWAP_DO BIT(2)
185 #define SSS_HASH_BYTESWAP_IV BIT(1)
186 #define SSS_HASH_BYTESWAP_KEY BIT(0)
188 #define SSS_REG_HASH_STATUS 0x10
190 #define SSS_HASH_STATUS_MSG_DONE BIT(6)
191 #define SSS_HASH_STATUS_PARTIAL_DONE BIT(4)
192 #define SSS_HASH_STATUS_BUFFER_READY BIT(0)
194 #define SSS_REG_HASH_MSG_SIZE_LOW 0x20
195 #define SSS_REG_HASH_MSG_SIZE_HIGH 0x24
197 #define SSS_REG_HASH_PRE_MSG_SIZE_LOW 0x28
198 #define SSS_REG_HASH_PRE_MSG_SIZE_HIGH 0x2C
200 #define SSS_REG_HASH_IV(s) (0xB0 + ((s) << 2))
201 #define SSS_REG_HASH_OUT(s) (0x100 + ((s) << 2))
203 #define HASH_BLOCK_SIZE 64
204 #define HASH_REG_SIZEOF 4
205 #define HASH_MD5_MAX_REG (MD5_DIGEST_SIZE / HASH_REG_SIZEOF)
206 #define HASH_SHA1_MAX_REG (SHA1_DIGEST_SIZE / HASH_REG_SIZEOF)
207 #define HASH_SHA256_MAX_REG (SHA256_DIGEST_SIZE / HASH_REG_SIZEOF)
210 * HASH bit numbers, used by device, setting in dev->hash_flags with
211 * functions set_bit(), clear_bit() or tested with test_bit() or BIT(),
212 * to keep HASH state BUSY or FREE, or to signal state from irq_handler
213 * to hash_tasklet. SGS keep track of allocated memory for scatterlist
215 #define HASH_FLAGS_BUSY 0
216 #define HASH_FLAGS_FINAL 1
217 #define HASH_FLAGS_DMA_ACTIVE 2
218 #define HASH_FLAGS_OUTPUT_READY 3
219 #define HASH_FLAGS_DMA_READY 4
220 #define HASH_FLAGS_SGS_COPIED 5
221 #define HASH_FLAGS_SGS_ALLOCED 6
223 /* HASH HW constants */
224 #define BUFLEN HASH_BLOCK_SIZE
226 #define SSS_HASH_DMA_LEN_ALIGN 8
227 #define SSS_HASH_DMA_ALIGN_MASK (SSS_HASH_DMA_LEN_ALIGN - 1)
229 #define SSS_HASH_QUEUE_LENGTH 10
232 * struct samsung_aes_variant - platform specific SSS driver data
233 * @aes_offset: AES register offset from SSS module's base.
234 * @hash_offset: HASH register offset from SSS module's base.
235 * @clk_names: names of clocks needed to run SSS IP
237 * Specifies platform specific configuration of SSS module.
238 * Note: A structure for driver specific platform data is used for future
239 * expansion of its usage.
241 struct samsung_aes_variant {
242 unsigned int aes_offset;
243 unsigned int hash_offset;
244 const char *clk_names[2];
247 struct s5p_aes_reqctx {
252 struct s5p_aes_dev *dev;
254 u8 aes_key[AES_MAX_KEY_SIZE];
255 u8 nonce[CTR_RFC3686_NONCE_SIZE];
260 * struct s5p_aes_dev - Crypto device state container
261 * @dev: Associated device
262 * @clk: Clock for accessing hardware
263 * @pclk: APB bus clock necessary to access the hardware
264 * @ioaddr: Mapped IO memory region
265 * @aes_ioaddr: Per-varian offset for AES block IO memory
266 * @irq_fc: Feed control interrupt line
267 * @req: Crypto request currently handled by the device
268 * @ctx: Configuration for currently handled crypto request
269 * @sg_src: Scatter list with source data for currently handled block
270 * in device. This is DMA-mapped into device.
271 * @sg_dst: Scatter list with destination data for currently handled block
272 * in device. This is DMA-mapped into device.
273 * @sg_src_cpy: In case of unaligned access, copied scatter list
275 * @sg_dst_cpy: In case of unaligned access, copied scatter list
276 * with destination data.
277 * @tasklet: New request scheduling jib
278 * @queue: Crypto queue
279 * @busy: Indicates whether the device is currently handling some request
280 * thus it uses some of the fields from this state, like:
281 * req, ctx, sg_src/dst (and copies). This essentially
282 * protects against concurrent access to these fields.
283 * @lock: Lock for protecting both access to device hardware registers
284 * and fields related to current request (including the busy field).
285 * @res: Resources for hash.
286 * @io_hash_base: Per-variant offset for HASH block IO memory.
287 * @hash_lock: Lock for protecting hash_req, hash_queue and hash_flags
289 * @hash_flags: Flags for current HASH op.
290 * @hash_queue: Async hash queue.
291 * @hash_tasklet: New HASH request scheduling job.
292 * @xmit_buf: Buffer for current HASH request transfer into SSS block.
293 * @hash_req: Current request sending to SSS HASH block.
294 * @hash_sg_iter: Scatterlist transferred through DMA into SSS HASH block.
295 * @hash_sg_cnt: Counter for hash_sg_iter.
297 * @use_hash: true if HASH algs enabled
303 void __iomem *ioaddr;
304 void __iomem *aes_ioaddr;
307 struct skcipher_request *req;
308 struct s5p_aes_ctx *ctx;
309 struct scatterlist *sg_src;
310 struct scatterlist *sg_dst;
312 struct scatterlist *sg_src_cpy;
313 struct scatterlist *sg_dst_cpy;
315 struct tasklet_struct tasklet;
316 struct crypto_queue queue;
320 struct resource *res;
321 void __iomem *io_hash_base;
323 spinlock_t hash_lock; /* protect hash_ vars */
324 unsigned long hash_flags;
325 struct crypto_queue hash_queue;
326 struct tasklet_struct hash_tasklet;
329 struct ahash_request *hash_req;
330 struct scatterlist *hash_sg_iter;
331 unsigned int hash_sg_cnt;
337 * struct s5p_hash_reqctx - HASH request context
338 * @dd: Associated device
339 * @op_update: Current request operation (OP_UPDATE or OP_FINAL)
340 * @digcnt: Number of bytes processed by HW (without buffer[] ones)
341 * @digest: Digest message or IV for partial result
342 * @nregs: Number of HW registers for digest or IV read/write
343 * @engine: Bits for selecting type of HASH in SSS block
344 * @sg: sg for DMA transfer
345 * @sg_len: Length of sg for DMA transfer
346 * @sgl: sg for joining buffer and req->src scatterlist
347 * @skip: Skip offset in req->src for current op
348 * @total: Total number of bytes for current request
349 * @finup: Keep state for finup or final.
350 * @error: Keep track of error.
351 * @bufcnt: Number of bytes holded in buffer[]
352 * @buffer: For byte(s) from end of req->src in UPDATE op
354 struct s5p_hash_reqctx {
355 struct s5p_aes_dev *dd;
359 u8 digest[SHA256_DIGEST_SIZE];
361 unsigned int nregs; /* digest_size / sizeof(reg) */
364 struct scatterlist *sg;
366 struct scatterlist sgl[2];
377 * struct s5p_hash_ctx - HASH transformation context
378 * @dd: Associated device
379 * @flags: Bits for algorithm HASH.
380 * @fallback: Software transformation for zero message or size < BUFLEN.
382 struct s5p_hash_ctx {
383 struct s5p_aes_dev *dd;
385 struct crypto_shash *fallback;
388 static const struct samsung_aes_variant s5p_aes_data = {
389 .aes_offset = 0x4000,
390 .hash_offset = 0x6000,
391 .clk_names = { "secss", },
394 static const struct samsung_aes_variant exynos_aes_data = {
396 .hash_offset = 0x400,
397 .clk_names = { "secss", },
400 static const struct samsung_aes_variant exynos5433_slim_aes_data = {
402 .hash_offset = 0x800,
403 .clk_names = { "pclk", "aclk", },
406 static const struct of_device_id s5p_sss_dt_match[] = {
408 .compatible = "samsung,s5pv210-secss",
409 .data = &s5p_aes_data,
412 .compatible = "samsung,exynos4210-secss",
413 .data = &exynos_aes_data,
416 .compatible = "samsung,exynos5433-slim-sss",
417 .data = &exynos5433_slim_aes_data,
421 MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
423 static inline const struct samsung_aes_variant *find_s5p_sss_version
424 (const struct platform_device *pdev)
426 if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) {
427 const struct of_device_id *match;
429 match = of_match_node(s5p_sss_dt_match,
431 return (const struct samsung_aes_variant *)match->data;
433 return (const struct samsung_aes_variant *)
434 platform_get_device_id(pdev)->driver_data;
437 static struct s5p_aes_dev *s5p_dev;
439 static void s5p_set_dma_indata(struct s5p_aes_dev *dev,
440 const struct scatterlist *sg)
442 SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
443 SSS_WRITE(dev, FCBRDMAL, sg_dma_len(sg));
446 static void s5p_set_dma_outdata(struct s5p_aes_dev *dev,
447 const struct scatterlist *sg)
449 SSS_WRITE(dev, FCBTDMAS, sg_dma_address(sg));
450 SSS_WRITE(dev, FCBTDMAL, sg_dma_len(sg));
453 static void s5p_free_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist **sg)
460 len = ALIGN(dev->req->cryptlen, AES_BLOCK_SIZE);
461 free_pages((unsigned long)sg_virt(*sg), get_order(len));
467 static void s5p_sg_copy_buf(void *buf, struct scatterlist *sg,
468 unsigned int nbytes, int out)
470 struct scatter_walk walk;
475 scatterwalk_start(&walk, sg);
476 scatterwalk_copychunks(buf, &walk, nbytes, out);
477 scatterwalk_done(&walk, out, 0);
480 static void s5p_sg_done(struct s5p_aes_dev *dev)
482 struct skcipher_request *req = dev->req;
483 struct s5p_aes_reqctx *reqctx = skcipher_request_ctx(req);
485 if (dev->sg_dst_cpy) {
487 "Copying %d bytes of output data back to original place\n",
489 s5p_sg_copy_buf(sg_virt(dev->sg_dst_cpy), dev->req->dst,
490 dev->req->cryptlen, 1);
492 s5p_free_sg_cpy(dev, &dev->sg_src_cpy);
493 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy);
494 if (reqctx->mode & FLAGS_AES_CBC)
495 memcpy_fromio(req->iv, dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), AES_BLOCK_SIZE);
497 else if (reqctx->mode & FLAGS_AES_CTR)
498 memcpy_fromio(req->iv, dev->aes_ioaddr + SSS_REG_AES_CNT_DATA(0), AES_BLOCK_SIZE);
501 /* Calls the completion. Cannot be called with dev->lock hold. */
502 static void s5p_aes_complete(struct skcipher_request *req, int err)
504 req->base.complete(&req->base, err);
507 static void s5p_unset_outdata(struct s5p_aes_dev *dev)
509 dma_unmap_sg(dev->dev, dev->sg_dst, 1, DMA_FROM_DEVICE);
512 static void s5p_unset_indata(struct s5p_aes_dev *dev)
514 dma_unmap_sg(dev->dev, dev->sg_src, 1, DMA_TO_DEVICE);
517 static int s5p_make_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist *src,
518 struct scatterlist **dst)
523 *dst = kmalloc(sizeof(**dst), GFP_ATOMIC);
527 len = ALIGN(dev->req->cryptlen, AES_BLOCK_SIZE);
528 pages = (void *)__get_free_pages(GFP_ATOMIC, get_order(len));
535 s5p_sg_copy_buf(pages, src, dev->req->cryptlen, 0);
537 sg_init_table(*dst, 1);
538 sg_set_buf(*dst, pages, len);
543 static int s5p_set_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg)
548 if (!dma_map_sg(dev->dev, sg, 1, DMA_FROM_DEVICE))
556 static int s5p_set_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
561 if (!dma_map_sg(dev->dev, sg, 1, DMA_TO_DEVICE))
570 * Returns -ERRNO on error (mapping of new data failed).
571 * On success returns:
572 * - 0 if there is no more data,
573 * - 1 if new transmitting (output) data is ready and its address+length
574 * have to be written to device (by calling s5p_set_dma_outdata()).
576 static int s5p_aes_tx(struct s5p_aes_dev *dev)
580 s5p_unset_outdata(dev);
582 if (!sg_is_last(dev->sg_dst)) {
583 ret = s5p_set_outdata(dev, sg_next(dev->sg_dst));
592 * Returns -ERRNO on error (mapping of new data failed).
593 * On success returns:
594 * - 0 if there is no more data,
595 * - 1 if new receiving (input) data is ready and its address+length
596 * have to be written to device (by calling s5p_set_dma_indata()).
598 static int s5p_aes_rx(struct s5p_aes_dev *dev/*, bool *set_dma*/)
602 s5p_unset_indata(dev);
604 if (!sg_is_last(dev->sg_src)) {
605 ret = s5p_set_indata(dev, sg_next(dev->sg_src));
613 static inline u32 s5p_hash_read(struct s5p_aes_dev *dd, u32 offset)
615 return __raw_readl(dd->io_hash_base + offset);
618 static inline void s5p_hash_write(struct s5p_aes_dev *dd,
619 u32 offset, u32 value)
621 __raw_writel(value, dd->io_hash_base + offset);
625 * s5p_set_dma_hashdata() - start DMA with sg
627 * @sg: scatterlist ready to DMA transmit
629 static void s5p_set_dma_hashdata(struct s5p_aes_dev *dev,
630 const struct scatterlist *sg)
633 SSS_WRITE(dev, FCHRDMAS, sg_dma_address(sg));
634 SSS_WRITE(dev, FCHRDMAL, sg_dma_len(sg)); /* DMA starts */
638 * s5p_hash_rx() - get next hash_sg_iter
642 * 2 if there is no more data and it is UPDATE op
643 * 1 if new receiving (input) data is ready and can be written to device
644 * 0 if there is no more data and it is FINAL op
646 static int s5p_hash_rx(struct s5p_aes_dev *dev)
648 if (dev->hash_sg_cnt > 0) {
649 dev->hash_sg_iter = sg_next(dev->hash_sg_iter);
653 set_bit(HASH_FLAGS_DMA_READY, &dev->hash_flags);
654 if (test_bit(HASH_FLAGS_FINAL, &dev->hash_flags))
660 static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id)
662 struct platform_device *pdev = dev_id;
663 struct s5p_aes_dev *dev = platform_get_drvdata(pdev);
664 struct skcipher_request *req;
674 spin_lock_irqsave(&dev->lock, flags);
677 * Handle rx or tx interrupt. If there is still data (scatterlist did not
678 * reach end), then map next scatterlist entry.
679 * In case of such mapping error, s5p_aes_complete() should be called.
681 * If there is no more data in tx scatter list, call s5p_aes_complete()
682 * and schedule new tasklet.
684 * Handle hx interrupt. If there is still data map next entry.
686 status = SSS_READ(dev, FCINTSTAT);
687 if (status & SSS_FCINTSTAT_BRDMAINT)
688 err_dma_rx = s5p_aes_rx(dev);
690 if (status & SSS_FCINTSTAT_BTDMAINT) {
691 if (sg_is_last(dev->sg_dst))
693 err_dma_tx = s5p_aes_tx(dev);
696 if (status & SSS_FCINTSTAT_HRDMAINT)
697 err_dma_hx = s5p_hash_rx(dev);
699 st_bits = status & (SSS_FCINTSTAT_BRDMAINT | SSS_FCINTSTAT_BTDMAINT |
700 SSS_FCINTSTAT_HRDMAINT);
702 SSS_WRITE(dev, FCINTPEND, st_bits);
704 /* clear HASH irq bits */
705 if (status & (SSS_FCINTSTAT_HDONEINT | SSS_FCINTSTAT_HPARTINT)) {
706 /* cannot have both HPART and HDONE */
707 if (status & SSS_FCINTSTAT_HPARTINT)
708 st_bits = SSS_HASH_STATUS_PARTIAL_DONE;
710 if (status & SSS_FCINTSTAT_HDONEINT)
711 st_bits = SSS_HASH_STATUS_MSG_DONE;
713 set_bit(HASH_FLAGS_OUTPUT_READY, &dev->hash_flags);
714 s5p_hash_write(dev, SSS_REG_HASH_STATUS, st_bits);
716 /* when DONE or PART, do not handle HASH DMA */
720 if (err_dma_rx < 0) {
724 if (err_dma_tx < 0) {
732 s5p_set_dma_hashdata(dev, dev->hash_sg_iter);
734 spin_unlock_irqrestore(&dev->lock, flags);
736 s5p_aes_complete(dev->req, 0);
737 /* Device is still busy */
738 tasklet_schedule(&dev->tasklet);
741 * Writing length of DMA block (either receiving or
742 * transmitting) will start the operation immediately, so this
743 * should be done at the end (even after clearing pending
744 * interrupts to not miss the interrupt).
747 s5p_set_dma_outdata(dev, dev->sg_dst);
749 s5p_set_dma_indata(dev, dev->sg_src);
751 s5p_set_dma_hashdata(dev, dev->hash_sg_iter);
753 spin_unlock_irqrestore(&dev->lock, flags);
763 s5p_set_dma_hashdata(dev, dev->hash_sg_iter);
765 spin_unlock_irqrestore(&dev->lock, flags);
766 s5p_aes_complete(req, err);
770 * Note about else if:
771 * when hash_sg_iter reaches end and its UPDATE op,
772 * issue SSS_HASH_PAUSE and wait for HPART irq
775 tasklet_schedule(&dev->hash_tasklet);
776 else if (err_dma_hx == 2)
777 s5p_hash_write(dev, SSS_REG_HASH_CTRL_PAUSE,
784 * s5p_hash_read_msg() - read message or IV from HW
785 * @req: AHASH request
787 static void s5p_hash_read_msg(struct ahash_request *req)
789 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
790 struct s5p_aes_dev *dd = ctx->dd;
791 u32 *hash = (u32 *)ctx->digest;
794 for (i = 0; i < ctx->nregs; i++)
795 hash[i] = s5p_hash_read(dd, SSS_REG_HASH_OUT(i));
799 * s5p_hash_write_ctx_iv() - write IV for next partial/finup op.
801 * @ctx: request context
803 static void s5p_hash_write_ctx_iv(struct s5p_aes_dev *dd,
804 const struct s5p_hash_reqctx *ctx)
806 const u32 *hash = (const u32 *)ctx->digest;
809 for (i = 0; i < ctx->nregs; i++)
810 s5p_hash_write(dd, SSS_REG_HASH_IV(i), hash[i]);
814 * s5p_hash_write_iv() - write IV for next partial/finup op.
815 * @req: AHASH request
817 static void s5p_hash_write_iv(struct ahash_request *req)
819 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
821 s5p_hash_write_ctx_iv(ctx->dd, ctx);
825 * s5p_hash_copy_result() - copy digest into req->result
826 * @req: AHASH request
828 static void s5p_hash_copy_result(struct ahash_request *req)
830 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
835 memcpy(req->result, ctx->digest, ctx->nregs * HASH_REG_SIZEOF);
839 * s5p_hash_dma_flush() - flush HASH DMA
842 static void s5p_hash_dma_flush(struct s5p_aes_dev *dev)
844 SSS_WRITE(dev, FCHRDMAC, SSS_FCHRDMAC_FLUSH);
848 * s5p_hash_dma_enable() - enable DMA mode for HASH
851 * enable DMA mode for HASH
853 static void s5p_hash_dma_enable(struct s5p_aes_dev *dev)
855 s5p_hash_write(dev, SSS_REG_HASH_CTRL_FIFO, SSS_HASH_FIFO_MODE_DMA);
859 * s5p_hash_irq_disable() - disable irq HASH signals
861 * @flags: bitfield with irq's to be disabled
863 static void s5p_hash_irq_disable(struct s5p_aes_dev *dev, u32 flags)
865 SSS_WRITE(dev, FCINTENCLR, flags);
869 * s5p_hash_irq_enable() - enable irq signals
871 * @flags: bitfield with irq's to be enabled
873 static void s5p_hash_irq_enable(struct s5p_aes_dev *dev, int flags)
875 SSS_WRITE(dev, FCINTENSET, flags);
879 * s5p_hash_set_flow() - set flow inside SecSS AES/DES with/without HASH
881 * @hashflow: HASH stream flow with/without crypto AES/DES
883 static void s5p_hash_set_flow(struct s5p_aes_dev *dev, u32 hashflow)
888 spin_lock_irqsave(&dev->lock, flags);
890 flow = SSS_READ(dev, FCFIFOCTRL);
891 flow &= ~SSS_HASHIN_MASK;
893 SSS_WRITE(dev, FCFIFOCTRL, flow);
895 spin_unlock_irqrestore(&dev->lock, flags);
899 * s5p_ahash_dma_init() - enable DMA and set HASH flow inside SecSS
901 * @hashflow: HASH stream flow with/without AES/DES
903 * flush HASH DMA and enable DMA, set HASH stream flow inside SecSS HW,
904 * enable HASH irq's HRDMA, HDONE, HPART
906 static void s5p_ahash_dma_init(struct s5p_aes_dev *dev, u32 hashflow)
908 s5p_hash_irq_disable(dev, SSS_FCINTENCLR_HRDMAINTENCLR |
909 SSS_FCINTENCLR_HDONEINTENCLR |
910 SSS_FCINTENCLR_HPARTINTENCLR);
911 s5p_hash_dma_flush(dev);
913 s5p_hash_dma_enable(dev);
914 s5p_hash_set_flow(dev, hashflow & SSS_HASHIN_MASK);
915 s5p_hash_irq_enable(dev, SSS_FCINTENSET_HRDMAINTENSET |
916 SSS_FCINTENSET_HDONEINTENSET |
917 SSS_FCINTENSET_HPARTINTENSET);
921 * s5p_hash_write_ctrl() - prepare HASH block in SecSS for processing
923 * @length: length for request
924 * @final: true if final op
926 * Prepare SSS HASH block for processing bytes in DMA mode. If it is called
927 * after previous updates, fill up IV words. For final, calculate and set
928 * lengths for HASH so SecSS can finalize hash. For partial, set SSS HASH
929 * length as 2^63 so it will be never reached and set to zero prelow and
932 * This function does not start DMA transfer.
934 static void s5p_hash_write_ctrl(struct s5p_aes_dev *dd, size_t length,
937 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req);
938 u32 prelow, prehigh, low, high;
939 u32 configflags, swapflags;
942 configflags = ctx->engine | SSS_HASH_INIT_BIT;
944 if (likely(ctx->digcnt)) {
945 s5p_hash_write_ctx_iv(dd, ctx);
946 configflags |= SSS_HASH_USER_IV_EN;
950 /* number of bytes for last part */
953 /* total number of bits prev hashed */
954 tmplen = ctx->digcnt * 8;
955 prelow = (u32)tmplen;
956 prehigh = (u32)(tmplen >> 32);
964 swapflags = SSS_HASH_BYTESWAP_DI | SSS_HASH_BYTESWAP_DO |
965 SSS_HASH_BYTESWAP_IV | SSS_HASH_BYTESWAP_KEY;
967 s5p_hash_write(dd, SSS_REG_HASH_MSG_SIZE_LOW, low);
968 s5p_hash_write(dd, SSS_REG_HASH_MSG_SIZE_HIGH, high);
969 s5p_hash_write(dd, SSS_REG_HASH_PRE_MSG_SIZE_LOW, prelow);
970 s5p_hash_write(dd, SSS_REG_HASH_PRE_MSG_SIZE_HIGH, prehigh);
972 s5p_hash_write(dd, SSS_REG_HASH_CTRL_SWAP, swapflags);
973 s5p_hash_write(dd, SSS_REG_HASH_CTRL, configflags);
977 * s5p_hash_xmit_dma() - start DMA hash processing
979 * @length: length for request
980 * @final: true if final op
982 * Update digcnt here, as it is needed for finup/final op.
984 static int s5p_hash_xmit_dma(struct s5p_aes_dev *dd, size_t length,
987 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req);
990 cnt = dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
992 dev_err(dd->dev, "dma_map_sg error\n");
997 set_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags);
998 dd->hash_sg_iter = ctx->sg;
999 dd->hash_sg_cnt = cnt;
1000 s5p_hash_write_ctrl(dd, length, final);
1001 ctx->digcnt += length;
1002 ctx->total -= length;
1004 /* catch last interrupt */
1006 set_bit(HASH_FLAGS_FINAL, &dd->hash_flags);
1008 s5p_set_dma_hashdata(dd, dd->hash_sg_iter); /* DMA starts */
1010 return -EINPROGRESS;
1014 * s5p_hash_copy_sgs() - copy request's bytes into new buffer
1015 * @ctx: request context
1016 * @sg: source scatterlist request
1017 * @new_len: number of bytes to process from sg
1019 * Allocate new buffer, copy data for HASH into it. If there was xmit_buf
1020 * filled, copy it first, then copy data from sg into it. Prepare one sgl[0]
1021 * with allocated buffer.
1023 * Set bit in dd->hash_flag so we can free it after irq ends processing.
1025 static int s5p_hash_copy_sgs(struct s5p_hash_reqctx *ctx,
1026 struct scatterlist *sg, unsigned int new_len)
1028 unsigned int pages, len;
1031 len = new_len + ctx->bufcnt;
1032 pages = get_order(len);
1034 buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
1036 dev_err(ctx->dd->dev, "alloc pages for unaligned case.\n");
1042 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
1044 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->skip,
1046 sg_init_table(ctx->sgl, 1);
1047 sg_set_buf(ctx->sgl, buf, len);
1052 set_bit(HASH_FLAGS_SGS_COPIED, &ctx->dd->hash_flags);
1058 * s5p_hash_copy_sg_lists() - copy sg list and make fixes in copy
1059 * @ctx: request context
1060 * @sg: source scatterlist request
1061 * @new_len: number of bytes to process from sg
1063 * Allocate new scatterlist table, copy data for HASH into it. If there was
1064 * xmit_buf filled, prepare it first, then copy page, length and offset from
1065 * source sg into it, adjusting begin and/or end for skip offset and
1068 * Resulting sg table will be assigned to ctx->sg. Set flag so we can free
1069 * it after irq ends processing.
1071 static int s5p_hash_copy_sg_lists(struct s5p_hash_reqctx *ctx,
1072 struct scatterlist *sg, unsigned int new_len)
1074 unsigned int skip = ctx->skip, n = sg_nents(sg);
1075 struct scatterlist *tmp;
1081 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
1087 sg_init_table(ctx->sg, n);
1094 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
1099 while (sg && skip >= sg->length) {
1104 while (sg && new_len) {
1105 len = sg->length - skip;
1110 sg_set_page(tmp, sg_page(sg), len, sg->offset + skip);
1120 set_bit(HASH_FLAGS_SGS_ALLOCED, &ctx->dd->hash_flags);
1126 * s5p_hash_prepare_sgs() - prepare sg for processing
1127 * @ctx: request context
1128 * @sg: source scatterlist request
1129 * @new_len: number of bytes to process from sg
1130 * @final: final flag
1132 * Check two conditions: (1) if buffers in sg have len aligned data, and (2)
1133 * sg table have good aligned elements (list_ok). If one of this checks fails,
1134 * then either (1) allocates new buffer for data with s5p_hash_copy_sgs, copy
1135 * data into this buffer and prepare request in sgl, or (2) allocates new sg
1136 * table and prepare sg elements.
1138 * For digest or finup all conditions can be good, and we may not need any
1141 static int s5p_hash_prepare_sgs(struct s5p_hash_reqctx *ctx,
1142 struct scatterlist *sg,
1143 unsigned int new_len, bool final)
1145 unsigned int skip = ctx->skip, nbytes = new_len, n = 0;
1146 bool aligned = true, list_ok = true;
1147 struct scatterlist *sg_tmp = sg;
1149 if (!sg || !sg->length || !new_len)
1155 while (nbytes > 0 && sg_tmp) {
1157 if (skip >= sg_tmp->length) {
1158 skip -= sg_tmp->length;
1159 if (!sg_tmp->length) {
1164 if (!IS_ALIGNED(sg_tmp->length - skip, BUFLEN)) {
1169 if (nbytes < sg_tmp->length - skip) {
1174 nbytes -= sg_tmp->length - skip;
1178 sg_tmp = sg_next(sg_tmp);
1182 return s5p_hash_copy_sgs(ctx, sg, new_len);
1184 return s5p_hash_copy_sg_lists(ctx, sg, new_len);
1187 * Have aligned data from previous operation and/or current
1188 * Note: will enter here only if (digest or finup) and aligned
1192 sg_init_table(ctx->sgl, 2);
1193 sg_set_buf(ctx->sgl, ctx->dd->xmit_buf, ctx->bufcnt);
1194 sg_chain(ctx->sgl, 2, sg);
1206 * s5p_hash_prepare_request() - prepare request for processing
1207 * @req: AHASH request
1208 * @update: true if UPDATE op
1210 * Note 1: we can have update flag _and_ final flag at the same time.
1211 * Note 2: we enter here when digcnt > BUFLEN (=HASH_BLOCK_SIZE) or
1212 * either req->nbytes or ctx->bufcnt + req->nbytes is > BUFLEN or
1215 static int s5p_hash_prepare_request(struct ahash_request *req, bool update)
1217 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1218 bool final = ctx->finup;
1219 int xmit_len, hash_later, nbytes;
1223 nbytes = req->nbytes;
1227 ctx->total = nbytes + ctx->bufcnt;
1231 if (nbytes && (!IS_ALIGNED(ctx->bufcnt, BUFLEN))) {
1232 /* bytes left from previous request, so fill up to BUFLEN */
1233 int len = BUFLEN - ctx->bufcnt % BUFLEN;
1238 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1248 memcpy(ctx->dd->xmit_buf, ctx->buffer, ctx->bufcnt);
1250 xmit_len = ctx->total;
1254 if (IS_ALIGNED(xmit_len, BUFLEN))
1257 xmit_len -= xmit_len & (BUFLEN - 1);
1259 hash_later = ctx->total - xmit_len;
1260 /* copy hash_later bytes from end of req->src */
1261 /* previous bytes are in xmit_buf, so no overwrite */
1262 scatterwalk_map_and_copy(ctx->buffer, req->src,
1263 req->nbytes - hash_later,
1267 if (xmit_len > BUFLEN) {
1268 ret = s5p_hash_prepare_sgs(ctx, req->src, nbytes - hash_later,
1273 /* have buffered data only */
1274 if (unlikely(!ctx->bufcnt)) {
1275 /* first update didn't fill up buffer */
1276 scatterwalk_map_and_copy(ctx->dd->xmit_buf, req->src,
1280 sg_init_table(ctx->sgl, 1);
1281 sg_set_buf(ctx->sgl, ctx->dd->xmit_buf, xmit_len);
1287 ctx->bufcnt = hash_later;
1289 ctx->total = xmit_len;
1295 * s5p_hash_update_dma_stop() - unmap DMA
1298 * Unmap scatterlist ctx->sg.
1300 static void s5p_hash_update_dma_stop(struct s5p_aes_dev *dd)
1302 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req);
1304 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
1305 clear_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags);
1309 * s5p_hash_finish() - copy calculated digest to crypto layer
1310 * @req: AHASH request
1312 static void s5p_hash_finish(struct ahash_request *req)
1314 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1315 struct s5p_aes_dev *dd = ctx->dd;
1318 s5p_hash_copy_result(req);
1320 dev_dbg(dd->dev, "hash_finish digcnt: %lld\n", ctx->digcnt);
1324 * s5p_hash_finish_req() - finish request
1325 * @req: AHASH request
1328 static void s5p_hash_finish_req(struct ahash_request *req, int err)
1330 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1331 struct s5p_aes_dev *dd = ctx->dd;
1332 unsigned long flags;
1334 if (test_bit(HASH_FLAGS_SGS_COPIED, &dd->hash_flags))
1335 free_pages((unsigned long)sg_virt(ctx->sg),
1336 get_order(ctx->sg->length));
1338 if (test_bit(HASH_FLAGS_SGS_ALLOCED, &dd->hash_flags))
1342 dd->hash_flags &= ~(BIT(HASH_FLAGS_SGS_ALLOCED) |
1343 BIT(HASH_FLAGS_SGS_COPIED));
1345 if (!err && !ctx->error) {
1346 s5p_hash_read_msg(req);
1347 if (test_bit(HASH_FLAGS_FINAL, &dd->hash_flags))
1348 s5p_hash_finish(req);
1353 spin_lock_irqsave(&dd->hash_lock, flags);
1354 dd->hash_flags &= ~(BIT(HASH_FLAGS_BUSY) | BIT(HASH_FLAGS_FINAL) |
1355 BIT(HASH_FLAGS_DMA_READY) |
1356 BIT(HASH_FLAGS_OUTPUT_READY));
1357 spin_unlock_irqrestore(&dd->hash_lock, flags);
1359 if (req->base.complete)
1360 req->base.complete(&req->base, err);
1364 * s5p_hash_handle_queue() - handle hash queue
1365 * @dd: device s5p_aes_dev
1366 * @req: AHASH request
1368 * If req!=NULL enqueue it on dd->queue, if FLAGS_BUSY is not set on the
1369 * device then processes the first request from the dd->queue
1371 * Returns: see s5p_hash_final below.
1373 static int s5p_hash_handle_queue(struct s5p_aes_dev *dd,
1374 struct ahash_request *req)
1376 struct crypto_async_request *async_req, *backlog;
1377 struct s5p_hash_reqctx *ctx;
1378 unsigned long flags;
1379 int err = 0, ret = 0;
1382 spin_lock_irqsave(&dd->hash_lock, flags);
1384 ret = ahash_enqueue_request(&dd->hash_queue, req);
1386 if (test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) {
1387 spin_unlock_irqrestore(&dd->hash_lock, flags);
1391 backlog = crypto_get_backlog(&dd->hash_queue);
1392 async_req = crypto_dequeue_request(&dd->hash_queue);
1394 set_bit(HASH_FLAGS_BUSY, &dd->hash_flags);
1396 spin_unlock_irqrestore(&dd->hash_lock, flags);
1402 backlog->complete(backlog, -EINPROGRESS);
1404 req = ahash_request_cast(async_req);
1406 ctx = ahash_request_ctx(req);
1408 err = s5p_hash_prepare_request(req, ctx->op_update);
1409 if (err || !ctx->total)
1412 dev_dbg(dd->dev, "handling new req, op_update: %u, nbytes: %d\n",
1413 ctx->op_update, req->nbytes);
1415 s5p_ahash_dma_init(dd, SSS_HASHIN_INDEPENDENT);
1417 s5p_hash_write_iv(req); /* restore hash IV */
1419 if (ctx->op_update) { /* HASH_OP_UPDATE */
1420 err = s5p_hash_xmit_dma(dd, ctx->total, ctx->finup);
1421 if (err != -EINPROGRESS && ctx->finup && !ctx->error)
1422 /* no final() after finup() */
1423 err = s5p_hash_xmit_dma(dd, ctx->total, true);
1424 } else { /* HASH_OP_FINAL */
1425 err = s5p_hash_xmit_dma(dd, ctx->total, true);
1428 if (err != -EINPROGRESS) {
1429 /* hash_tasklet_cb will not finish it, so do it here */
1430 s5p_hash_finish_req(req, err);
1434 * Execute next request immediately if there is anything
1444 * s5p_hash_tasklet_cb() - hash tasklet
1445 * @data: ptr to s5p_aes_dev
1447 static void s5p_hash_tasklet_cb(unsigned long data)
1449 struct s5p_aes_dev *dd = (struct s5p_aes_dev *)data;
1451 if (!test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) {
1452 s5p_hash_handle_queue(dd, NULL);
1456 if (test_bit(HASH_FLAGS_DMA_READY, &dd->hash_flags)) {
1457 if (test_and_clear_bit(HASH_FLAGS_DMA_ACTIVE,
1459 s5p_hash_update_dma_stop(dd);
1462 if (test_and_clear_bit(HASH_FLAGS_OUTPUT_READY,
1464 /* hash or semi-hash ready */
1465 clear_bit(HASH_FLAGS_DMA_READY, &dd->hash_flags);
1473 /* finish curent request */
1474 s5p_hash_finish_req(dd->hash_req, 0);
1476 /* If we are not busy, process next req */
1477 if (!test_bit(HASH_FLAGS_BUSY, &dd->hash_flags))
1478 s5p_hash_handle_queue(dd, NULL);
1482 * s5p_hash_enqueue() - enqueue request
1483 * @req: AHASH request
1484 * @op: operation UPDATE (true) or FINAL (false)
1486 * Returns: see s5p_hash_final below.
1488 static int s5p_hash_enqueue(struct ahash_request *req, bool op)
1490 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1491 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1493 ctx->op_update = op;
1495 return s5p_hash_handle_queue(tctx->dd, req);
1499 * s5p_hash_update() - process the hash input data
1500 * @req: AHASH request
1502 * If request will fit in buffer, copy it and return immediately
1503 * else enqueue it with OP_UPDATE.
1505 * Returns: see s5p_hash_final below.
1507 static int s5p_hash_update(struct ahash_request *req)
1509 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1514 if (ctx->bufcnt + req->nbytes <= BUFLEN) {
1515 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1517 ctx->bufcnt += req->nbytes;
1521 return s5p_hash_enqueue(req, true); /* HASH_OP_UPDATE */
1525 * s5p_hash_final() - close up hash and calculate digest
1526 * @req: AHASH request
1528 * Note: in final req->src do not have any data, and req->nbytes can be
1531 * If there were no input data processed yet and the buffered hash data is
1532 * less than BUFLEN (64) then calculate the final hash immediately by using
1533 * SW algorithm fallback.
1535 * Otherwise enqueues the current AHASH request with OP_FINAL operation op
1536 * and finalize hash message in HW. Note that if digcnt!=0 then there were
1537 * previous update op, so there are always some buffered bytes in ctx->buffer,
1538 * which means that ctx->bufcnt!=0
1541 * 0 if the request has been processed immediately,
1542 * -EINPROGRESS if the operation has been queued for later execution or is set
1543 * to processing by HW,
1544 * -EBUSY if queue is full and request should be resubmitted later,
1545 * other negative values denotes an error.
1547 static int s5p_hash_final(struct ahash_request *req)
1549 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1553 return -EINVAL; /* uncompleted hash is not needed */
1555 if (!ctx->digcnt && ctx->bufcnt < BUFLEN) {
1556 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1558 return crypto_shash_tfm_digest(tctx->fallback, ctx->buffer,
1559 ctx->bufcnt, req->result);
1562 return s5p_hash_enqueue(req, false); /* HASH_OP_FINAL */
1566 * s5p_hash_finup() - process last req->src and calculate digest
1567 * @req: AHASH request containing the last update data
1569 * Return values: see s5p_hash_final above.
1571 static int s5p_hash_finup(struct ahash_request *req)
1573 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1578 err1 = s5p_hash_update(req);
1579 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1583 * final() has to be always called to cleanup resources even if
1584 * update() failed, except EINPROGRESS or calculate digest for small
1587 err2 = s5p_hash_final(req);
1589 return err1 ?: err2;
1593 * s5p_hash_init() - initialize AHASH request contex
1594 * @req: AHASH request
1596 * Init async hash request context.
1598 static int s5p_hash_init(struct ahash_request *req)
1600 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1601 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1602 struct s5p_hash_ctx *tctx = crypto_ahash_ctx(tfm);
1612 dev_dbg(tctx->dd->dev, "init: digest size: %d\n",
1613 crypto_ahash_digestsize(tfm));
1615 switch (crypto_ahash_digestsize(tfm)) {
1616 case MD5_DIGEST_SIZE:
1617 ctx->engine = SSS_HASH_ENGINE_MD5;
1618 ctx->nregs = HASH_MD5_MAX_REG;
1620 case SHA1_DIGEST_SIZE:
1621 ctx->engine = SSS_HASH_ENGINE_SHA1;
1622 ctx->nregs = HASH_SHA1_MAX_REG;
1624 case SHA256_DIGEST_SIZE:
1625 ctx->engine = SSS_HASH_ENGINE_SHA256;
1626 ctx->nregs = HASH_SHA256_MAX_REG;
1637 * s5p_hash_digest - calculate digest from req->src
1638 * @req: AHASH request
1640 * Return values: see s5p_hash_final above.
1642 static int s5p_hash_digest(struct ahash_request *req)
1644 return s5p_hash_init(req) ?: s5p_hash_finup(req);
1648 * s5p_hash_cra_init_alg - init crypto alg transformation
1649 * @tfm: crypto transformation
1651 static int s5p_hash_cra_init_alg(struct crypto_tfm *tfm)
1653 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(tfm);
1654 const char *alg_name = crypto_tfm_alg_name(tfm);
1657 /* Allocate a fallback and abort if it failed. */
1658 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1659 CRYPTO_ALG_NEED_FALLBACK);
1660 if (IS_ERR(tctx->fallback)) {
1661 pr_err("fallback alloc fails for '%s'\n", alg_name);
1662 return PTR_ERR(tctx->fallback);
1665 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1666 sizeof(struct s5p_hash_reqctx) + BUFLEN);
1672 * s5p_hash_cra_init - init crypto tfm
1673 * @tfm: crypto transformation
1675 static int s5p_hash_cra_init(struct crypto_tfm *tfm)
1677 return s5p_hash_cra_init_alg(tfm);
1681 * s5p_hash_cra_exit - exit crypto tfm
1682 * @tfm: crypto transformation
1684 * free allocated fallback
1686 static void s5p_hash_cra_exit(struct crypto_tfm *tfm)
1688 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(tfm);
1690 crypto_free_shash(tctx->fallback);
1691 tctx->fallback = NULL;
1695 * s5p_hash_export - export hash state
1696 * @req: AHASH request
1697 * @out: buffer for exported state
1699 static int s5p_hash_export(struct ahash_request *req, void *out)
1701 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1703 memcpy(out, ctx, sizeof(*ctx) + ctx->bufcnt);
1709 * s5p_hash_import - import hash state
1710 * @req: AHASH request
1711 * @in: buffer with state to be imported from
1713 static int s5p_hash_import(struct ahash_request *req, const void *in)
1715 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1716 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1717 struct s5p_hash_ctx *tctx = crypto_ahash_ctx(tfm);
1718 const struct s5p_hash_reqctx *ctx_in = in;
1720 memcpy(ctx, in, sizeof(*ctx) + BUFLEN);
1721 if (ctx_in->bufcnt > BUFLEN) {
1732 static struct ahash_alg algs_sha1_md5_sha256[] = {
1734 .init = s5p_hash_init,
1735 .update = s5p_hash_update,
1736 .final = s5p_hash_final,
1737 .finup = s5p_hash_finup,
1738 .digest = s5p_hash_digest,
1739 .export = s5p_hash_export,
1740 .import = s5p_hash_import,
1741 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN,
1742 .halg.digestsize = SHA1_DIGEST_SIZE,
1745 .cra_driver_name = "exynos-sha1",
1746 .cra_priority = 100,
1747 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1749 CRYPTO_ALG_NEED_FALLBACK,
1750 .cra_blocksize = HASH_BLOCK_SIZE,
1751 .cra_ctxsize = sizeof(struct s5p_hash_ctx),
1752 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK,
1753 .cra_module = THIS_MODULE,
1754 .cra_init = s5p_hash_cra_init,
1755 .cra_exit = s5p_hash_cra_exit,
1759 .init = s5p_hash_init,
1760 .update = s5p_hash_update,
1761 .final = s5p_hash_final,
1762 .finup = s5p_hash_finup,
1763 .digest = s5p_hash_digest,
1764 .export = s5p_hash_export,
1765 .import = s5p_hash_import,
1766 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN,
1767 .halg.digestsize = MD5_DIGEST_SIZE,
1770 .cra_driver_name = "exynos-md5",
1771 .cra_priority = 100,
1772 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1774 CRYPTO_ALG_NEED_FALLBACK,
1775 .cra_blocksize = HASH_BLOCK_SIZE,
1776 .cra_ctxsize = sizeof(struct s5p_hash_ctx),
1777 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK,
1778 .cra_module = THIS_MODULE,
1779 .cra_init = s5p_hash_cra_init,
1780 .cra_exit = s5p_hash_cra_exit,
1784 .init = s5p_hash_init,
1785 .update = s5p_hash_update,
1786 .final = s5p_hash_final,
1787 .finup = s5p_hash_finup,
1788 .digest = s5p_hash_digest,
1789 .export = s5p_hash_export,
1790 .import = s5p_hash_import,
1791 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN,
1792 .halg.digestsize = SHA256_DIGEST_SIZE,
1794 .cra_name = "sha256",
1795 .cra_driver_name = "exynos-sha256",
1796 .cra_priority = 100,
1797 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1799 CRYPTO_ALG_NEED_FALLBACK,
1800 .cra_blocksize = HASH_BLOCK_SIZE,
1801 .cra_ctxsize = sizeof(struct s5p_hash_ctx),
1802 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK,
1803 .cra_module = THIS_MODULE,
1804 .cra_init = s5p_hash_cra_init,
1805 .cra_exit = s5p_hash_cra_exit,
1811 static void s5p_set_aes(struct s5p_aes_dev *dev,
1812 const u8 *key, const u8 *iv, const u8 *ctr,
1813 unsigned int keylen)
1815 void __iomem *keystart;
1818 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv,
1822 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_CNT_DATA(0), ctr,
1825 if (keylen == AES_KEYSIZE_256)
1826 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0);
1827 else if (keylen == AES_KEYSIZE_192)
1828 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2);
1830 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4);
1832 memcpy_toio(keystart, key, keylen);
1835 static bool s5p_is_sg_aligned(struct scatterlist *sg)
1838 if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE))
1846 static int s5p_set_indata_start(struct s5p_aes_dev *dev,
1847 struct skcipher_request *req)
1849 struct scatterlist *sg;
1852 dev->sg_src_cpy = NULL;
1854 if (!s5p_is_sg_aligned(sg)) {
1856 "At least one unaligned source scatter list, making a copy\n");
1857 err = s5p_make_sg_cpy(dev, sg, &dev->sg_src_cpy);
1861 sg = dev->sg_src_cpy;
1864 err = s5p_set_indata(dev, sg);
1866 s5p_free_sg_cpy(dev, &dev->sg_src_cpy);
1873 static int s5p_set_outdata_start(struct s5p_aes_dev *dev,
1874 struct skcipher_request *req)
1876 struct scatterlist *sg;
1879 dev->sg_dst_cpy = NULL;
1881 if (!s5p_is_sg_aligned(sg)) {
1883 "At least one unaligned dest scatter list, making a copy\n");
1884 err = s5p_make_sg_cpy(dev, sg, &dev->sg_dst_cpy);
1888 sg = dev->sg_dst_cpy;
1891 err = s5p_set_outdata(dev, sg);
1893 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy);
1900 static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
1902 struct skcipher_request *req = dev->req;
1904 unsigned long flags;
1908 /* This sets bit [13:12] to 00, which selects 128-bit counter */
1909 aes_control = SSS_AES_KEY_CHANGE_MODE;
1910 if (mode & FLAGS_AES_DECRYPT)
1911 aes_control |= SSS_AES_MODE_DECRYPT;
1913 if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC) {
1914 aes_control |= SSS_AES_CHAIN_MODE_CBC;
1917 } else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR) {
1918 aes_control |= SSS_AES_CHAIN_MODE_CTR;
1922 iv = NULL; /* AES_ECB */
1926 if (dev->ctx->keylen == AES_KEYSIZE_192)
1927 aes_control |= SSS_AES_KEY_SIZE_192;
1928 else if (dev->ctx->keylen == AES_KEYSIZE_256)
1929 aes_control |= SSS_AES_KEY_SIZE_256;
1931 aes_control |= SSS_AES_FIFO_MODE;
1933 /* as a variant it is possible to use byte swapping on DMA side */
1934 aes_control |= SSS_AES_BYTESWAP_DI
1935 | SSS_AES_BYTESWAP_DO
1936 | SSS_AES_BYTESWAP_IV
1937 | SSS_AES_BYTESWAP_KEY
1938 | SSS_AES_BYTESWAP_CNT;
1940 spin_lock_irqsave(&dev->lock, flags);
1942 SSS_WRITE(dev, FCINTENCLR,
1943 SSS_FCINTENCLR_BTDMAINTENCLR | SSS_FCINTENCLR_BRDMAINTENCLR);
1944 SSS_WRITE(dev, FCFIFOCTRL, 0x00);
1946 err = s5p_set_indata_start(dev, req);
1950 err = s5p_set_outdata_start(dev, req);
1954 SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
1955 s5p_set_aes(dev, dev->ctx->aes_key, iv, ctr, dev->ctx->keylen);
1957 s5p_set_dma_indata(dev, dev->sg_src);
1958 s5p_set_dma_outdata(dev, dev->sg_dst);
1960 SSS_WRITE(dev, FCINTENSET,
1961 SSS_FCINTENSET_BTDMAINTENSET | SSS_FCINTENSET_BRDMAINTENSET);
1963 spin_unlock_irqrestore(&dev->lock, flags);
1968 s5p_unset_indata(dev);
1973 spin_unlock_irqrestore(&dev->lock, flags);
1974 s5p_aes_complete(req, err);
1977 static void s5p_tasklet_cb(unsigned long data)
1979 struct s5p_aes_dev *dev = (struct s5p_aes_dev *)data;
1980 struct crypto_async_request *async_req, *backlog;
1981 struct s5p_aes_reqctx *reqctx;
1982 unsigned long flags;
1984 spin_lock_irqsave(&dev->lock, flags);
1985 backlog = crypto_get_backlog(&dev->queue);
1986 async_req = crypto_dequeue_request(&dev->queue);
1990 spin_unlock_irqrestore(&dev->lock, flags);
1993 spin_unlock_irqrestore(&dev->lock, flags);
1996 backlog->complete(backlog, -EINPROGRESS);
1998 dev->req = skcipher_request_cast(async_req);
1999 dev->ctx = crypto_tfm_ctx(dev->req->base.tfm);
2000 reqctx = skcipher_request_ctx(dev->req);
2002 s5p_aes_crypt_start(dev, reqctx->mode);
2005 static int s5p_aes_handle_req(struct s5p_aes_dev *dev,
2006 struct skcipher_request *req)
2008 unsigned long flags;
2011 spin_lock_irqsave(&dev->lock, flags);
2012 err = crypto_enqueue_request(&dev->queue, &req->base);
2014 spin_unlock_irqrestore(&dev->lock, flags);
2019 spin_unlock_irqrestore(&dev->lock, flags);
2021 tasklet_schedule(&dev->tasklet);
2026 static int s5p_aes_crypt(struct skcipher_request *req, unsigned long mode)
2028 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
2029 struct s5p_aes_reqctx *reqctx = skcipher_request_ctx(req);
2030 struct s5p_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
2031 struct s5p_aes_dev *dev = ctx->dev;
2036 if (!IS_ALIGNED(req->cryptlen, AES_BLOCK_SIZE) &&
2037 ((mode & FLAGS_AES_MODE_MASK) != FLAGS_AES_CTR)) {
2038 dev_dbg(dev->dev, "request size is not exact amount of AES blocks\n");
2042 reqctx->mode = mode;
2044 return s5p_aes_handle_req(dev, req);
2047 static int s5p_aes_setkey(struct crypto_skcipher *cipher,
2048 const u8 *key, unsigned int keylen)
2050 struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher);
2051 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm);
2053 if (keylen != AES_KEYSIZE_128 &&
2054 keylen != AES_KEYSIZE_192 &&
2055 keylen != AES_KEYSIZE_256)
2058 memcpy(ctx->aes_key, key, keylen);
2059 ctx->keylen = keylen;
2064 static int s5p_aes_ecb_encrypt(struct skcipher_request *req)
2066 return s5p_aes_crypt(req, 0);
2069 static int s5p_aes_ecb_decrypt(struct skcipher_request *req)
2071 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT);
2074 static int s5p_aes_cbc_encrypt(struct skcipher_request *req)
2076 return s5p_aes_crypt(req, FLAGS_AES_CBC);
2079 static int s5p_aes_cbc_decrypt(struct skcipher_request *req)
2081 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT | FLAGS_AES_CBC);
2084 static int s5p_aes_ctr_crypt(struct skcipher_request *req)
2086 return s5p_aes_crypt(req, FLAGS_AES_CTR);
2089 static int s5p_aes_init_tfm(struct crypto_skcipher *tfm)
2091 struct s5p_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
2094 crypto_skcipher_set_reqsize(tfm, sizeof(struct s5p_aes_reqctx));
2099 static struct skcipher_alg algs[] = {
2101 .base.cra_name = "ecb(aes)",
2102 .base.cra_driver_name = "ecb-aes-s5p",
2103 .base.cra_priority = 100,
2104 .base.cra_flags = CRYPTO_ALG_ASYNC |
2105 CRYPTO_ALG_KERN_DRIVER_ONLY,
2106 .base.cra_blocksize = AES_BLOCK_SIZE,
2107 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx),
2108 .base.cra_alignmask = 0x0f,
2109 .base.cra_module = THIS_MODULE,
2111 .min_keysize = AES_MIN_KEY_SIZE,
2112 .max_keysize = AES_MAX_KEY_SIZE,
2113 .setkey = s5p_aes_setkey,
2114 .encrypt = s5p_aes_ecb_encrypt,
2115 .decrypt = s5p_aes_ecb_decrypt,
2116 .init = s5p_aes_init_tfm,
2119 .base.cra_name = "cbc(aes)",
2120 .base.cra_driver_name = "cbc-aes-s5p",
2121 .base.cra_priority = 100,
2122 .base.cra_flags = CRYPTO_ALG_ASYNC |
2123 CRYPTO_ALG_KERN_DRIVER_ONLY,
2124 .base.cra_blocksize = AES_BLOCK_SIZE,
2125 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx),
2126 .base.cra_alignmask = 0x0f,
2127 .base.cra_module = THIS_MODULE,
2129 .min_keysize = AES_MIN_KEY_SIZE,
2130 .max_keysize = AES_MAX_KEY_SIZE,
2131 .ivsize = AES_BLOCK_SIZE,
2132 .setkey = s5p_aes_setkey,
2133 .encrypt = s5p_aes_cbc_encrypt,
2134 .decrypt = s5p_aes_cbc_decrypt,
2135 .init = s5p_aes_init_tfm,
2138 .base.cra_name = "ctr(aes)",
2139 .base.cra_driver_name = "ctr-aes-s5p",
2140 .base.cra_priority = 100,
2141 .base.cra_flags = CRYPTO_ALG_ASYNC |
2142 CRYPTO_ALG_KERN_DRIVER_ONLY,
2143 .base.cra_blocksize = 1,
2144 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx),
2145 .base.cra_alignmask = 0x0f,
2146 .base.cra_module = THIS_MODULE,
2148 .min_keysize = AES_MIN_KEY_SIZE,
2149 .max_keysize = AES_MAX_KEY_SIZE,
2150 .ivsize = AES_BLOCK_SIZE,
2151 .setkey = s5p_aes_setkey,
2152 .encrypt = s5p_aes_ctr_crypt,
2153 .decrypt = s5p_aes_ctr_crypt,
2154 .init = s5p_aes_init_tfm,
2158 static int s5p_aes_probe(struct platform_device *pdev)
2160 struct device *dev = &pdev->dev;
2161 int i, j, err = -ENODEV;
2162 const struct samsung_aes_variant *variant;
2163 struct s5p_aes_dev *pdata;
2164 struct resource *res;
2165 unsigned int hash_i;
2170 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2174 variant = find_s5p_sss_version(pdev);
2175 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2180 * Note: HASH and PRNG uses the same registers in secss, avoid
2181 * overwrite each other. This will drop HASH when CONFIG_EXYNOS_RNG
2182 * is enabled in config. We need larger size for HASH registers in
2183 * secss, current describe only AES/DES
2185 if (IS_ENABLED(CONFIG_CRYPTO_DEV_EXYNOS_HASH)) {
2186 if (variant == &exynos_aes_data) {
2188 pdata->use_hash = true;
2193 pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
2194 if (IS_ERR(pdata->ioaddr)) {
2195 if (!pdata->use_hash)
2196 return PTR_ERR(pdata->ioaddr);
2197 /* try AES without HASH */
2199 pdata->use_hash = false;
2200 pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
2201 if (IS_ERR(pdata->ioaddr))
2202 return PTR_ERR(pdata->ioaddr);
2205 pdata->clk = devm_clk_get(dev, variant->clk_names[0]);
2206 if (IS_ERR(pdata->clk))
2207 return dev_err_probe(dev, PTR_ERR(pdata->clk),
2208 "failed to find secss clock %s\n",
2209 variant->clk_names[0]);
2211 err = clk_prepare_enable(pdata->clk);
2213 dev_err(dev, "Enabling clock %s failed, err %d\n",
2214 variant->clk_names[0], err);
2218 if (variant->clk_names[1]) {
2219 pdata->pclk = devm_clk_get(dev, variant->clk_names[1]);
2220 if (IS_ERR(pdata->pclk)) {
2221 err = dev_err_probe(dev, PTR_ERR(pdata->pclk),
2222 "failed to find clock %s\n",
2223 variant->clk_names[1]);
2227 err = clk_prepare_enable(pdata->pclk);
2229 dev_err(dev, "Enabling clock %s failed, err %d\n",
2230 variant->clk_names[0], err);
2237 spin_lock_init(&pdata->lock);
2238 spin_lock_init(&pdata->hash_lock);
2240 pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset;
2241 pdata->io_hash_base = pdata->ioaddr + variant->hash_offset;
2243 pdata->irq_fc = platform_get_irq(pdev, 0);
2244 if (pdata->irq_fc < 0) {
2245 err = pdata->irq_fc;
2246 dev_warn(dev, "feed control interrupt is not available.\n");
2249 err = devm_request_threaded_irq(dev, pdata->irq_fc, NULL,
2250 s5p_aes_interrupt, IRQF_ONESHOT,
2253 dev_warn(dev, "feed control interrupt is not available.\n");
2257 pdata->busy = false;
2259 platform_set_drvdata(pdev, pdata);
2262 tasklet_init(&pdata->tasklet, s5p_tasklet_cb, (unsigned long)pdata);
2263 crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN);
2265 for (i = 0; i < ARRAY_SIZE(algs); i++) {
2266 err = crypto_register_skcipher(&algs[i]);
2271 if (pdata->use_hash) {
2272 tasklet_init(&pdata->hash_tasklet, s5p_hash_tasklet_cb,
2273 (unsigned long)pdata);
2274 crypto_init_queue(&pdata->hash_queue, SSS_HASH_QUEUE_LENGTH);
2276 for (hash_i = 0; hash_i < ARRAY_SIZE(algs_sha1_md5_sha256);
2278 struct ahash_alg *alg;
2280 alg = &algs_sha1_md5_sha256[hash_i];
2281 err = crypto_register_ahash(alg);
2283 dev_err(dev, "can't register '%s': %d\n",
2284 alg->halg.base.cra_driver_name, err);
2290 dev_info(dev, "s5p-sss driver registered\n");
2295 for (j = hash_i - 1; j >= 0; j--)
2296 crypto_unregister_ahash(&algs_sha1_md5_sha256[j]);
2298 tasklet_kill(&pdata->hash_tasklet);
2302 if (i < ARRAY_SIZE(algs))
2303 dev_err(dev, "can't register '%s': %d\n", algs[i].base.cra_name,
2306 for (j = 0; j < i; j++)
2307 crypto_unregister_skcipher(&algs[j]);
2309 tasklet_kill(&pdata->tasklet);
2312 clk_disable_unprepare(pdata->pclk);
2315 clk_disable_unprepare(pdata->clk);
2321 static int s5p_aes_remove(struct platform_device *pdev)
2323 struct s5p_aes_dev *pdata = platform_get_drvdata(pdev);
2329 for (i = 0; i < ARRAY_SIZE(algs); i++)
2330 crypto_unregister_skcipher(&algs[i]);
2332 tasklet_kill(&pdata->tasklet);
2333 if (pdata->use_hash) {
2334 for (i = ARRAY_SIZE(algs_sha1_md5_sha256) - 1; i >= 0; i--)
2335 crypto_unregister_ahash(&algs_sha1_md5_sha256[i]);
2337 pdata->res->end -= 0x300;
2338 tasklet_kill(&pdata->hash_tasklet);
2339 pdata->use_hash = false;
2342 clk_disable_unprepare(pdata->pclk);
2344 clk_disable_unprepare(pdata->clk);
2350 static struct platform_driver s5p_aes_crypto = {
2351 .probe = s5p_aes_probe,
2352 .remove = s5p_aes_remove,
2354 .name = "s5p-secss",
2355 .of_match_table = s5p_sss_dt_match,
2359 module_platform_driver(s5p_aes_crypto);
2361 MODULE_DESCRIPTION("S5PV210 AES hw acceleration support.");
2362 MODULE_LICENSE("GPL v2");
2363 MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy@gmail.com>");
2364 MODULE_AUTHOR("Kamil Konieczny <k.konieczny@partner.samsung.com>");