1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pata-legacy.c - Legacy port PATA/SATA controller driver.
4 * Copyright 2005/2006 Red Hat, all rights reserved.
6 * An ATA driver for the legacy ATA ports.
9 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
11 * Promise 20230/20620:
12 * http://www.ryston.cz/petr/vlb/pdc20230b.html
13 * http://www.ryston.cz/petr/vlb/pdc20230c.html
14 * http://www.ryston.cz/petr/vlb/pdc20630.html
16 * http://www.ryston.cz/petr/vlb/qd6500.html
17 * http://www.ryston.cz/petr/vlb/qd6580.html
19 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c
20 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
21 * Samuel Thibault <samuel.thibault@ens-lyon.org>
23 * Unsupported but docs exist:
24 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
26 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
27 * on PC class systems. There are three hybrid devices that are exceptions
28 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
29 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
31 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
32 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
34 * Support for the Winbond 83759A when operating in advanced mode.
35 * Multichip mode is not currently supported.
37 * Use the autospeed and pio_mask options with:
38 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
39 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
40 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
41 * Winbond W83759A, Promise PDC20230-B
43 * For now use autospeed and pio_mask as above with the W83759A. This may
47 #include <linux/async.h>
48 #include <linux/kernel.h>
49 #include <linux/module.h>
50 #include <linux/pci.h>
51 #include <linux/init.h>
52 #include <linux/blkdev.h>
53 #include <linux/delay.h>
54 #include <scsi/scsi_host.h>
55 #include <linux/ata.h>
56 #include <linux/libata.h>
57 #include <linux/platform_device.h>
59 #define DRV_NAME "pata_legacy"
60 #define DRV_VERSION "0.6.5"
65 module_param(all, int, 0444);
66 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
78 QDI6580DP = 9, /* Dual channel mode is different */
90 struct platform_device *platform_dev;
99 unsigned long private;
102 struct legacy_controller {
104 struct ata_port_operations *ops;
105 unsigned int pio_mask;
108 int (*setup)(struct platform_device *, struct legacy_probe *probe,
109 struct legacy_data *data);
112 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
114 static struct legacy_probe probe_list[NR_HOST];
115 static struct legacy_data legacy_data[NR_HOST];
116 static struct ata_host *legacy_host[NR_HOST];
117 static int nr_legacy_host;
120 static int probe_all; /* Set to check all ISA port ranges */
121 static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */
122 static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
123 static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
124 static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */
125 static int autospeed; /* Chip present which snoops speed changes */
126 static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */
127 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
129 /* Set to probe QDI controllers */
130 #ifdef CONFIG_PATA_QDI_MODULE
136 #ifdef CONFIG_PATA_WINBOND_VLB_MODULE
137 static int winbond = 1; /* Set to probe Winbond controllers,
138 give I/O port if non standard */
140 static int winbond; /* Set to probe Winbond controllers,
141 give I/O port if non standard */
145 * legacy_probe_add - Add interface to probe list
146 * @port: Controller port
148 * @type: Controller type
149 * @private: Controller specific info
151 * Add an entry into the probe list for ATA controllers. This is used
152 * to add the default ISA slots and then to build up the table
153 * further according to other ISA/VLB/Weird device scans
155 * An I/O port list is used to keep ordering stable and sane, as we
156 * don't have any good way to talk about ordering otherwise
159 static int legacy_probe_add(unsigned long port, unsigned int irq,
160 enum controller type, unsigned long private)
162 struct legacy_probe *lp = &probe_list[0];
164 struct legacy_probe *free = NULL;
166 for (i = 0; i < NR_HOST; i++) {
167 if (lp->port == 0 && free == NULL)
169 /* Matching port, or the correct slot for ordering */
170 if (lp->port == port || legacy_port[i] == port) {
177 printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
180 /* Fill in the entry for later probing */
184 free->private = private;
190 * legacy_set_mode - mode setting
192 * @unused: Device that failed when error is returned
194 * Use a non standard set_mode function. We don't want to be tuned.
196 * The BIOS configured everything. Our job is not to fiddle. Just use
197 * whatever PIO the hardware is using and leave it at that. When we
198 * get some kind of nice user driven API for control then we can
199 * expand on this as per hdparm in the base kernel.
202 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
204 struct ata_device *dev;
206 ata_for_each_dev(dev, link, ENABLED) {
207 ata_dev_info(dev, "configured for PIO\n");
208 dev->pio_mode = XFER_PIO_0;
209 dev->xfer_mode = XFER_PIO_0;
210 dev->xfer_shift = ATA_SHIFT_PIO;
211 dev->flags |= ATA_DFLAG_PIO;
216 static struct scsi_host_template legacy_sht = {
217 ATA_PIO_SHT(DRV_NAME),
220 static const struct ata_port_operations legacy_base_port_ops = {
221 .inherits = &ata_sff_port_ops,
222 .cable_detect = ata_cable_40wire,
226 * These ops are used if the user indicates the hardware
227 * snoops the commands to decide on the mode and handles the
228 * mode selection "magically" itself. Several legacy controllers
229 * do this. The mode range can be set if it is not 0x1F by setting
233 static struct ata_port_operations simple_port_ops = {
234 .inherits = &legacy_base_port_ops,
235 .sff_data_xfer = ata_sff_data_xfer32,
238 static struct ata_port_operations legacy_port_ops = {
239 .inherits = &legacy_base_port_ops,
240 .sff_data_xfer = ata_sff_data_xfer32,
241 .set_mode = legacy_set_mode,
245 * Promise 20230C and 20620 support
247 * This controller supports PIO0 to PIO2. We set PIO timings
248 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
249 * support is weird being DMA to controller and PIO'd to the host
253 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
256 int pio = adev->pio_mode - XFER_PIO_0;
260 /* Safe as UP only. Force I/Os to occur together */
262 local_irq_save(flags);
264 /* Unlock the control interface */
267 outb(inb(0x1F2) | 0x80, 0x1F2);
274 while ((inb(0x1F2) & 0x80) && --tries);
276 local_irq_restore(flags);
278 outb(inb(0x1F4) & 0x07, 0x1F4);
281 rt &= ~(0x07 << (3 * !adev->devno));
283 rt |= (1 + 3 * pio) << (3 * !adev->devno);
287 outb(inb(0x1F2) | 0x01, 0x1F2);
293 static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc,
294 unsigned char *buf, unsigned int buflen, int rw)
296 struct ata_device *dev = qc->dev;
297 struct ata_port *ap = dev->link->ap;
298 int slop = buflen & 3;
300 /* 32bit I/O capable *and* we need to write a whole number of dwords */
301 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)
302 && (ap->pflags & ATA_PFLAG_PIO32)) {
305 local_irq_save(flags);
307 /* Perform the 32bit I/O synchronization sequence */
308 ioread8(ap->ioaddr.nsect_addr);
309 ioread8(ap->ioaddr.nsect_addr);
310 ioread8(ap->ioaddr.nsect_addr);
314 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
316 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
318 if (unlikely(slop)) {
322 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
323 memcpy(buf + buflen - slop, &pad, slop);
325 memcpy(&pad, buf + buflen - slop, slop);
326 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
330 local_irq_restore(flags);
332 buflen = ata_sff_data_xfer32(qc, buf, buflen, rw);
337 static struct ata_port_operations pdc20230_port_ops = {
338 .inherits = &legacy_base_port_ops,
339 .set_piomode = pdc20230_set_piomode,
340 .sff_data_xfer = pdc_data_xfer_vlb,
344 * Holtek 6560A support
346 * This controller supports PIO0 to PIO2 (no IORDY even though higher
347 * timings can be loaded).
350 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
355 /* Get the timing data in cycles. For now play safe at 50Mhz */
356 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
358 active = clamp_val(t.active, 2, 15);
359 recover = clamp_val(t.recover, 4, 15);
366 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
367 ioread8(ap->ioaddr.status_addr);
370 static struct ata_port_operations ht6560a_port_ops = {
371 .inherits = &legacy_base_port_ops,
372 .set_piomode = ht6560a_set_piomode,
376 * Holtek 6560B support
378 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
379 * setting unless we see an ATAPI device in which case we force it off.
381 * FIXME: need to implement 2nd channel support.
384 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
389 /* Get the timing data in cycles. For now play safe at 50Mhz */
390 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
392 active = clamp_val(t.active, 2, 15);
393 recover = clamp_val(t.recover, 2, 16) & 0x0F;
400 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
402 if (adev->class != ATA_DEV_ATA) {
403 u8 rconf = inb(0x3E6);
409 ioread8(ap->ioaddr.status_addr);
412 static struct ata_port_operations ht6560b_port_ops = {
413 .inherits = &legacy_base_port_ops,
414 .set_piomode = ht6560b_set_piomode,
418 * Opti core chipset helpers
422 * opti_syscfg - read OPTI chipset configuration
423 * @reg: Configuration register to read
425 * Returns the value of an OPTI system board configuration register.
428 static u8 opti_syscfg(u8 reg)
433 /* Uniprocessor chipset and must force cycles adjancent */
434 local_irq_save(flags);
437 local_irq_restore(flags);
444 * This controller supports PIO0 to PIO3.
447 static void opti82c611a_set_piomode(struct ata_port *ap,
448 struct ata_device *adev)
450 u8 active, recover, setup;
452 struct ata_device *pair = ata_dev_pair(adev);
454 int khz[4] = { 50000, 40000, 33000, 25000 };
457 /* Enter configuration mode */
458 ioread16(ap->ioaddr.error_addr);
459 ioread16(ap->ioaddr.error_addr);
460 iowrite8(3, ap->ioaddr.nsect_addr);
462 /* Read VLB clock strapping */
463 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
465 /* Get the timing data in cycles */
466 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
468 /* Setup timing is shared */
470 struct ata_timing tp;
471 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
473 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
476 active = clamp_val(t.active, 2, 17) - 2;
477 recover = clamp_val(t.recover, 1, 16) - 1;
478 setup = clamp_val(t.setup, 1, 4) - 1;
480 /* Select the right timing bank for write timing */
481 rc = ioread8(ap->ioaddr.lbal_addr);
483 rc |= (adev->devno << 7);
484 iowrite8(rc, ap->ioaddr.lbal_addr);
486 /* Write the timings */
487 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
489 /* Select the right bank for read timings, also
490 load the shared timings for address */
491 rc = ioread8(ap->ioaddr.device_addr);
493 rc |= adev->devno; /* Index select */
494 rc |= (setup << 4) | 0x04;
495 iowrite8(rc, ap->ioaddr.device_addr);
497 /* Load the read timings */
498 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
500 /* Ensure the timing register mode is right */
501 rc = ioread8(ap->ioaddr.lbal_addr);
504 iowrite8(rc, ap->ioaddr.lbal_addr);
506 /* Exit command mode */
507 iowrite8(0x83, ap->ioaddr.nsect_addr);
511 static struct ata_port_operations opti82c611a_port_ops = {
512 .inherits = &legacy_base_port_ops,
513 .set_piomode = opti82c611a_set_piomode,
519 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
520 * version is dual channel but doesn't have a lot of unique registers.
523 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
525 u8 active, recover, setup;
527 struct ata_device *pair = ata_dev_pair(adev);
529 int khz[4] = { 50000, 40000, 33000, 25000 };
534 sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */
536 /* Enter configuration mode */
537 ioread16(ap->ioaddr.error_addr);
538 ioread16(ap->ioaddr.error_addr);
539 iowrite8(3, ap->ioaddr.nsect_addr);
541 /* Read VLB clock strapping */
542 clock = 1000000000 / khz[sysclk];
544 /* Get the timing data in cycles */
545 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
547 /* Setup timing is shared */
549 struct ata_timing tp;
550 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
552 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
555 active = clamp_val(t.active, 2, 17) - 2;
556 recover = clamp_val(t.recover, 1, 16) - 1;
557 setup = clamp_val(t.setup, 1, 4) - 1;
559 /* Select the right timing bank for write timing */
560 rc = ioread8(ap->ioaddr.lbal_addr);
562 rc |= (adev->devno << 7);
563 iowrite8(rc, ap->ioaddr.lbal_addr);
565 /* Write the timings */
566 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
568 /* Select the right bank for read timings, also
569 load the shared timings for address */
570 rc = ioread8(ap->ioaddr.device_addr);
572 rc |= adev->devno; /* Index select */
573 rc |= (setup << 4) | 0x04;
574 iowrite8(rc, ap->ioaddr.device_addr);
576 /* Load the read timings */
577 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
579 /* Ensure the timing register mode is right */
580 rc = ioread8(ap->ioaddr.lbal_addr);
583 iowrite8(rc, ap->ioaddr.lbal_addr);
585 /* Exit command mode */
586 iowrite8(0x83, ap->ioaddr.nsect_addr);
588 /* We need to know this for quad device on the MVB */
589 ap->host->private_data = ap;
593 * opt82c465mv_qc_issue - command issue
594 * @qc: command pending
596 * Called when the libata layer is about to issue a command. We wrap
597 * this interface so that we can load the correct ATA timings. The
598 * MVB has a single set of timing registers and these are shared
599 * across channels. As there are two registers we really ought to
600 * track the last two used values as a sort of register window. For
601 * now we just reload on a channel switch. On the single channel
602 * setup this condition never fires so we do nothing extra.
604 * FIXME: dual channel needs ->serialize support
607 static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)
609 struct ata_port *ap = qc->ap;
610 struct ata_device *adev = qc->dev;
612 /* If timings are set and for the wrong channel (2nd test is
613 due to a libata shortcoming and will eventually go I hope) */
614 if (ap->host->private_data != ap->host
615 && ap->host->private_data != NULL)
616 opti82c46x_set_piomode(ap, adev);
618 return ata_sff_qc_issue(qc);
621 static struct ata_port_operations opti82c46x_port_ops = {
622 .inherits = &legacy_base_port_ops,
623 .set_piomode = opti82c46x_set_piomode,
624 .qc_issue = opti82c46x_qc_issue,
628 * qdi65x0_set_piomode - PIO setup for QDI65x0
632 * In single channel mode the 6580 has one clock per device and we can
633 * avoid the requirement to clock switch. We also have to load the timing
634 * into the right clock according to whether we are master or slave.
636 * In dual channel mode the 6580 has one clock per channel and we have
637 * to software clockswitch in qc_issue.
640 static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev)
643 struct legacy_data *ld_qdi = ap->host->private_data;
644 int active, recovery;
647 /* Get the timing data in cycles */
648 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
651 active = 8 - clamp_val(t.active, 1, 8);
652 recovery = 18 - clamp_val(t.recover, 3, 18);
654 active = 9 - clamp_val(t.active, 2, 9);
655 recovery = 15 - clamp_val(t.recover, 0, 15);
657 timing = (recovery << 4) | active | 0x08;
658 ld_qdi->clock[adev->devno] = timing;
660 if (ld_qdi->type == QDI6580)
661 outb(timing, ld_qdi->timing + 2 * adev->devno);
663 outb(timing, ld_qdi->timing + 2 * ap->port_no);
666 if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA)
667 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
671 * qdi_qc_issue - command issue
672 * @qc: command pending
674 * Called when the libata layer is about to issue a command. We wrap
675 * this interface so that we can load the correct ATA timings.
678 static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
680 struct ata_port *ap = qc->ap;
681 struct ata_device *adev = qc->dev;
682 struct legacy_data *ld_qdi = ap->host->private_data;
684 if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
685 if (adev->pio_mode) {
686 ld_qdi->last = ld_qdi->clock[adev->devno];
687 outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
691 return ata_sff_qc_issue(qc);
694 static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc,
696 unsigned int buflen, int rw)
698 struct ata_device *adev = qc->dev;
699 struct ata_port *ap = adev->link->ap;
700 int slop = buflen & 3;
702 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)
703 && (ap->pflags & ATA_PFLAG_PIO32)) {
705 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
707 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
709 if (unlikely(slop)) {
713 memcpy(&pad, buf + buflen - slop, slop);
714 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
716 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
717 memcpy(buf + buflen - slop, &pad, slop);
720 return (buflen + 3) & ~3;
722 return ata_sff_data_xfer(qc, buf, buflen, rw);
725 static int qdi_port(struct platform_device *dev,
726 struct legacy_probe *lp, struct legacy_data *ld)
728 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
730 ld->timing = lp->private;
734 static struct ata_port_operations qdi6500_port_ops = {
735 .inherits = &legacy_base_port_ops,
736 .set_piomode = qdi65x0_set_piomode,
737 .qc_issue = qdi_qc_issue,
738 .sff_data_xfer = vlb32_data_xfer,
741 static struct ata_port_operations qdi6580_port_ops = {
742 .inherits = &legacy_base_port_ops,
743 .set_piomode = qdi65x0_set_piomode,
744 .sff_data_xfer = vlb32_data_xfer,
747 static struct ata_port_operations qdi6580dp_port_ops = {
748 .inherits = &legacy_base_port_ops,
749 .set_piomode = qdi65x0_set_piomode,
750 .qc_issue = qdi_qc_issue,
751 .sff_data_xfer = vlb32_data_xfer,
754 static DEFINE_SPINLOCK(winbond_lock);
756 static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
759 spin_lock_irqsave(&winbond_lock, flags);
760 outb(reg, port + 0x01);
761 outb(val, port + 0x02);
762 spin_unlock_irqrestore(&winbond_lock, flags);
765 static u8 winbond_readcfg(unsigned long port, u8 reg)
770 spin_lock_irqsave(&winbond_lock, flags);
771 outb(reg, port + 0x01);
772 val = inb(port + 0x02);
773 spin_unlock_irqrestore(&winbond_lock, flags);
778 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
781 struct legacy_data *ld_winbond = ap->host->private_data;
782 int active, recovery;
784 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
786 reg = winbond_readcfg(ld_winbond->timing, 0x81);
788 /* Get the timing data in cycles */
789 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
790 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
792 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
794 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
795 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
796 timing = (active << 4) | recovery;
797 winbond_writecfg(ld_winbond->timing, timing, reg);
799 /* Load the setup timing */
802 if (adev->class != ATA_DEV_ATA)
803 reg |= 0x08; /* FIFO off */
804 if (!ata_pio_need_iordy(adev))
805 reg |= 0x02; /* IORDY off */
806 reg |= (clamp_val(t.setup, 0, 3) << 6);
807 winbond_writecfg(ld_winbond->timing, timing + 1, reg);
810 static int winbond_port(struct platform_device *dev,
811 struct legacy_probe *lp, struct legacy_data *ld)
813 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
815 ld->timing = lp->private;
819 static struct ata_port_operations winbond_port_ops = {
820 .inherits = &legacy_base_port_ops,
821 .set_piomode = winbond_set_piomode,
822 .sff_data_xfer = vlb32_data_xfer,
825 static struct legacy_controller controllers[] = {
826 {"BIOS", &legacy_port_ops, ATA_PIO4,
827 ATA_FLAG_NO_IORDY, 0, NULL },
828 {"Snooping", &simple_port_ops, ATA_PIO4,
830 {"PDC20230", &pdc20230_port_ops, ATA_PIO2,
832 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL },
833 {"HT6560A", &ht6560a_port_ops, ATA_PIO2,
834 ATA_FLAG_NO_IORDY, 0, NULL },
835 {"HT6560B", &ht6560b_port_ops, ATA_PIO4,
836 ATA_FLAG_NO_IORDY, 0, NULL },
837 {"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3,
839 {"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3,
841 {"QDI6500", &qdi6500_port_ops, ATA_PIO2,
843 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
844 {"QDI6580", &qdi6580_port_ops, ATA_PIO4,
845 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
846 {"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4,
847 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
848 {"W83759A", &winbond_port_ops, ATA_PIO4,
849 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,
854 * probe_chip_type - Discover controller
855 * @probe: Probe entry to check
857 * Probe an ATA port and identify the type of controller. We don't
858 * check if the controller appears to be driveless at this point.
861 static __init int probe_chip_type(struct legacy_probe *probe)
863 int mask = 1 << probe->slot;
865 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
866 u8 reg = winbond_readcfg(winbond, 0x81);
867 reg |= 0x80; /* jumpered mode off */
868 winbond_writecfg(winbond, 0x81, reg);
869 reg = winbond_readcfg(winbond, 0x83);
870 reg |= 0xF0; /* local control */
871 winbond_writecfg(winbond, 0x83, reg);
872 reg = winbond_readcfg(winbond, 0x85);
873 reg |= 0xF0; /* programmable timing */
874 winbond_writecfg(winbond, 0x85, reg);
876 reg = winbond_readcfg(winbond, 0x81);
881 if (probe->port == 0x1F0) {
883 local_irq_save(flags);
885 outb(inb(0x1F2) | 0x80, 0x1F2);
893 if ((inb(0x1F2) & 0x80) == 0) {
894 /* PDC20230c or 20630 ? */
895 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"
899 local_irq_restore(flags);
905 if (inb(0x1F2) == 0x00)
906 printk(KERN_INFO "PDC20230-B VLB ATA "
907 "controller detected.\n");
908 local_irq_restore(flags);
917 if (opti82c611a & mask)
919 if (opti82c46x & mask)
921 if (autospeed & mask)
928 * legacy_init_one - attach a legacy interface
931 * Register an ISA bus IDE interface. Such interfaces are PIO and we
932 * assume do not support IRQ sharing.
935 static __init int legacy_init_one(struct legacy_probe *probe)
937 struct legacy_controller *controller = &controllers[probe->type];
938 int pio_modes = controller->pio_mask;
939 unsigned long io = probe->port;
940 u32 mask = (1 << probe->slot);
941 struct ata_port_operations *ops = controller->ops;
942 struct legacy_data *ld = &legacy_data[probe->slot];
943 struct ata_host *host = NULL;
945 struct platform_device *pdev;
946 struct ata_device *dev;
947 void __iomem *io_addr, *ctrl_addr;
948 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
951 iordy |= controller->flags;
953 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
955 return PTR_ERR(pdev);
958 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
959 devm_request_region(&pdev->dev, io + 0x0206, 1,
960 "pata_legacy") == NULL)
964 io_addr = devm_ioport_map(&pdev->dev, io, 8);
965 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
966 if (!io_addr || !ctrl_addr)
968 ld->type = probe->type;
969 if (controller->setup)
970 if (controller->setup(pdev, probe, ld) < 0)
972 host = ata_host_alloc(&pdev->dev, 1);
978 ap->pio_mask = pio_modes;
979 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
980 ap->pflags |= controller->pflags;
981 ap->ioaddr.cmd_addr = io_addr;
982 ap->ioaddr.altstatus_addr = ctrl_addr;
983 ap->ioaddr.ctl_addr = ctrl_addr;
984 ata_sff_std_ports(&ap->ioaddr);
985 ap->host->private_data = ld;
987 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
989 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,
993 async_synchronize_full();
994 ld->platform_dev = pdev;
996 /* Nothing found means we drop the port as its probably not there */
999 ata_for_each_dev(dev, &ap->link, ALL) {
1000 if (!ata_dev_absent(dev)) {
1001 legacy_host[probe->slot] = host;
1002 ld->platform_dev = pdev;
1006 ata_host_detach(host);
1008 platform_device_unregister(pdev);
1013 * legacy_check_special_cases - ATA special cases
1014 * @p: PCI device to check
1015 * @master: set this if we find an ATA master
1016 * @master: set this if we find an ATA secondary
1018 * A small number of vendors implemented early PCI ATA interfaces
1019 * on bridge logic without the ATA interface being PCI visible.
1020 * Where we have a matching PCI driver we must skip the relevant
1021 * device here. If we don't know about it then the legacy driver
1022 * is the right driver anyway.
1025 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
1028 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
1029 if (p->vendor == 0x1078 && p->device == 0x0000) {
1030 *primary = *secondary = 1;
1033 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
1034 if (p->vendor == 0x1078 && p->device == 0x0002) {
1035 *primary = *secondary = 1;
1038 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
1039 if (p->vendor == 0x8086 && p->device == 0x1234) {
1041 pci_read_config_word(p, 0x6C, &r);
1043 /* ATA port enabled */
1053 static __init void probe_opti_vlb(void)
1055 /* If an OPTI 82C46X is present find out where the channels are */
1056 static const char *optis[4] = {
1061 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
1063 opti82c46x = 3; /* Assume master and slave first */
1064 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
1067 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
1068 ctrl = opti_syscfg(0xAC);
1069 /* Check enabled and this port is the 465MV port. On the
1070 MVB we may have two channels */
1073 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1074 legacy_probe_add(0x170, 15, OPTI46X, 0);
1077 legacy_probe_add(0x170, 15, OPTI46X, 0);
1079 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1081 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1084 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
1086 static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
1087 /* Check card type */
1088 if ((r & 0xF0) == 0xC0) {
1089 /* QD6500: single channel */
1093 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1096 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
1097 /* QD6580: dual channel */
1098 if (!request_region(port + 2 , 2, "pata_qdi")) {
1099 release_region(port, 2);
1102 res = inb(port + 3);
1103 /* Single channel mode ? */
1105 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1107 else { /* Dual channel mode */
1108 legacy_probe_add(0x1F0, 14, QDI6580DP, port);
1109 /* port + 0x02, r & 0x04 */
1110 legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
1112 release_region(port + 2, 2);
1116 static __init void probe_qdi_vlb(void)
1118 unsigned long flags;
1119 static const unsigned long qd_port[2] = { 0x30, 0xB0 };
1123 * Check each possible QD65xx base address
1126 for (i = 0; i < 2; i++) {
1127 unsigned long port = qd_port[i];
1131 if (request_region(port, 2, "pata_qdi")) {
1132 /* Check for a card */
1133 local_irq_save(flags);
1134 /* I have no h/w that needs this delay but it
1135 is present in the historic code */
1144 local_irq_restore(flags);
1148 release_region(port, 2);
1151 /* Passes the presence test */
1154 /* Check port agrees with port set */
1155 if ((r & 2) >> 1 == i)
1156 qdi65_identify_port(r, res, port);
1157 release_region(port, 2);
1163 * legacy_init - attach legacy interfaces
1165 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
1166 * Right now we do not scan the ide0 and ide1 address but should do so
1167 * for non PCI systems or systems with no PCI IDE legacy mode devices.
1168 * If you fix that note there are special cases to consider like VLB
1169 * drivers and CS5510/20.
1172 static __init int legacy_init(void)
1178 int pci_present = 0;
1179 struct legacy_probe *pl = &probe_list[0];
1182 struct pci_dev *p = NULL;
1184 for_each_pci_dev(p) {
1186 /* Check for any overlap of the system ATA mappings. Native
1187 mode controllers stuck on these addresses or some devices
1188 in 'raid' mode won't be found by the storage class test */
1189 for (r = 0; r < 6; r++) {
1190 if (pci_resource_start(p, r) == 0x1f0)
1192 if (pci_resource_start(p, r) == 0x170)
1195 /* Check for special cases */
1196 legacy_check_special_cases(p, &primary, &secondary);
1198 /* If PCI bus is present then don't probe for tertiary
1204 winbond = 0x130; /* Default port, alt is 1B0 */
1206 if (primary == 0 || all)
1207 legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
1208 if (secondary == 0 || all)
1209 legacy_probe_add(0x170, 15, UNKNOWN, 0);
1211 if (probe_all || !pci_present) {
1212 /* ISA/VLB extra ports */
1213 legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
1214 legacy_probe_add(0x168, 10, UNKNOWN, 0);
1215 legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
1216 legacy_probe_add(0x160, 12, UNKNOWN, 0);
1224 for (i = 0; i < NR_HOST; i++, pl++) {
1227 if (pl->type == UNKNOWN)
1228 pl->type = probe_chip_type(pl);
1230 if (legacy_init_one(pl) == 0)
1238 static __exit void legacy_exit(void)
1242 for (i = 0; i < nr_legacy_host; i++) {
1243 struct legacy_data *ld = &legacy_data[i];
1244 ata_host_detach(legacy_host[i]);
1245 platform_device_unregister(ld->platform_dev);
1249 MODULE_AUTHOR("Alan Cox");
1250 MODULE_DESCRIPTION("low-level driver for legacy ATA");
1251 MODULE_LICENSE("GPL");
1252 MODULE_VERSION(DRV_VERSION);
1253 MODULE_ALIAS("pata_qdi");
1254 MODULE_ALIAS("pata_winbond");
1256 module_param(probe_all, int, 0);
1257 module_param(autospeed, int, 0);
1258 module_param(ht6560a, int, 0);
1259 module_param(ht6560b, int, 0);
1260 module_param(opti82c611a, int, 0);
1261 module_param(opti82c46x, int, 0);
1262 module_param(qdi, int, 0);
1263 module_param(winbond, int, 0);
1264 module_param(pio_mask, int, 0);
1265 module_param(iordy_mask, int, 0);
1267 module_init(legacy_init);
1268 module_exit(legacy_exit);