1 // SPDX-License-Identifier: GPL-2.0-only
3 * copyright (c) 2013 Freescale Semiconductor, Inc.
4 * Freescale IMX AHCI SATA platform driver
6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/property.h>
13 #include <linux/regmap.h>
14 #include <linux/ahci_platform.h>
15 #include <linux/gpio/consumer.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
19 #include <linux/libata.h>
20 #include <linux/hwmon.h>
21 #include <linux/hwmon-sysfs.h>
22 #include <linux/thermal.h>
25 #define DRV_NAME "ahci-imx"
28 /* Timer 1-ms Register */
29 IMX_TIMER1MS = 0x00e0,
30 /* Port0 PHY Control Register */
32 IMX_P0PHYCR_TEST_PDDQ = 1 << 20,
33 IMX_P0PHYCR_CR_READ = 1 << 19,
34 IMX_P0PHYCR_CR_WRITE = 1 << 18,
35 IMX_P0PHYCR_CR_CAP_DATA = 1 << 17,
36 IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16,
37 /* Port0 PHY Status Register */
39 IMX_P0PHYSR_CR_ACK = 1 << 18,
40 IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0,
41 /* Lane0 Output Status Register */
42 IMX_LANE0_OUT_STAT = 0x2003,
43 IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1,
44 /* Clock Reset Register */
45 IMX_CLOCK_RESET = 0x7f3f,
46 IMX_CLOCK_RESET_RESET = 1 << 0,
47 /* IMX8QM HSIO AHCI definitions */
48 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET = 0x03,
49 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET = 0x09,
50 IMX8QM_SATA_PHY_IMPED_RATIO_85OHM = 0x6c,
51 IMX8QM_LPCG_PHYX2_OFFSET = 0x00000,
52 IMX8QM_CSR_PHYX2_OFFSET = 0x90000,
53 IMX8QM_CSR_PHYX1_OFFSET = 0xa0000,
54 IMX8QM_CSR_PHYX_STTS0_OFFSET = 0x4,
55 IMX8QM_CSR_PCIEA_OFFSET = 0xb0000,
56 IMX8QM_CSR_PCIEB_OFFSET = 0xc0000,
57 IMX8QM_CSR_SATA_OFFSET = 0xd0000,
58 IMX8QM_CSR_PCIE_CTRL2_OFFSET = 0x8,
59 IMX8QM_CSR_MISC_OFFSET = 0xe0000,
61 IMX8QM_LPCG_PHYX2_PCLK0_MASK = (0x3 << 16),
62 IMX8QM_LPCG_PHYX2_PCLK1_MASK = (0x3 << 20),
63 IMX8QM_PHY_APB_RSTN_0 = BIT(0),
64 IMX8QM_PHY_MODE_SATA = BIT(19),
65 IMX8QM_PHY_MODE_MASK = (0xf << 17),
66 IMX8QM_PHY_PIPE_RSTN_0 = BIT(24),
67 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0 = BIT(25),
68 IMX8QM_PHY_PIPE_RSTN_1 = BIT(26),
69 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1 = BIT(27),
70 IMX8QM_STTS0_LANE0_TX_PLL_LOCK = BIT(4),
71 IMX8QM_MISC_IOB_RXENA = BIT(0),
72 IMX8QM_MISC_IOB_TXENA = BIT(1),
73 IMX8QM_MISC_PHYX1_EPCS_SEL = BIT(12),
74 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 = BIT(24),
75 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 = BIT(25),
76 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 = BIT(28),
77 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0 = BIT(29),
78 IMX8QM_SATA_CTRL_RESET_N = BIT(12),
79 IMX8QM_SATA_CTRL_EPCS_PHYRESET_N = BIT(7),
80 IMX8QM_CTRL_BUTTON_RST_N = BIT(21),
81 IMX8QM_CTRL_POWER_UP_RST_N = BIT(23),
82 IMX8QM_CTRL_LTSSM_ENABLE = BIT(4),
92 struct imx_ahci_priv {
93 struct platform_device *ahci_pdev;
94 enum ahci_imx_type type;
96 struct clk *sata_ref_clk;
98 struct clk *epcs_tx_clk;
99 struct clk *epcs_rx_clk;
100 struct clk *phy_apbclk;
101 struct clk *phy_pclk0;
102 struct clk *phy_pclk1;
103 void __iomem *phy_base;
104 struct gpio_desc *clkreq_gpiod;
112 static int ahci_imx_hotplug;
113 module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
114 MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
116 static void ahci_imx_host_stop(struct ata_host *host);
118 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
124 /* Assert or deassert the bit */
125 crval = readl(mmio + IMX_P0PHYCR);
130 writel(crval, mmio + IMX_P0PHYCR);
132 /* Wait for the cr_ack signal */
134 srval = readl(mmio + IMX_P0PHYSR);
135 if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
137 usleep_range(100, 200);
140 return timeout ? 0 : -ETIMEDOUT;
143 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
148 /* Supply the address on cr_data_in */
149 writel(crval, mmio + IMX_P0PHYCR);
151 /* Assert the cr_cap_addr signal */
152 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
156 /* Deassert cr_cap_addr */
157 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
164 static int imx_phy_reg_write(u16 val, void __iomem *mmio)
169 /* Supply the data on cr_data_in */
170 writel(crval, mmio + IMX_P0PHYCR);
172 /* Assert the cr_cap_data signal */
173 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
177 /* Deassert cr_cap_data */
178 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
182 if (val & IMX_CLOCK_RESET_RESET) {
184 * In case we're resetting the phy, it's unable to acknowledge,
185 * so we return immediately here.
187 crval |= IMX_P0PHYCR_CR_WRITE;
188 writel(crval, mmio + IMX_P0PHYCR);
192 /* Assert the cr_write signal */
193 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
197 /* Deassert cr_write */
198 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
206 static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
210 /* Assert the cr_read signal */
211 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
215 /* Capture the data from cr_data_out[] */
216 *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
218 /* Deassert cr_read */
219 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
226 static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
228 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
229 void __iomem *mmio = hpriv->mmio;
234 if (imxpriv->type == AHCI_IMX6QP) {
235 /* 6qp adds the sata reset mechanism, use it for 6qp sata */
236 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
237 IMX6Q_GPR5_SATA_SW_PD, 0);
239 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
240 IMX6Q_GPR5_SATA_SW_RST, 0);
242 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
243 IMX6Q_GPR5_SATA_SW_RST,
244 IMX6Q_GPR5_SATA_SW_RST);
248 /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
249 ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
252 ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
256 /* Wait for PHY RX_PLL to be stable */
258 usleep_range(100, 200);
259 ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
262 ret = imx_phy_reg_read(&val, mmio);
265 if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
269 return timeout ? 0 : -ETIMEDOUT;
273 /* SATA PHY Register */
274 SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT = 0x0001,
275 SATA_PHY_CR_CLOCK_DAC_CTL = 0x0008,
276 SATA_PHY_CR_CLOCK_RTUNE_CTL = 0x0009,
277 SATA_PHY_CR_CLOCK_ADC_OUT = 0x000A,
278 SATA_PHY_CR_CLOCK_MPLL_TST = 0x0017,
281 static int read_adc_sum(void *dev, u16 rtune_ctl_reg, void __iomem * mmio)
283 u16 adc_out_reg, read_sum;
284 u32 index, read_attempt;
285 const u32 attempt_limit = 200;
287 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
288 imx_phy_reg_write(rtune_ctl_reg, mmio);
294 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_ADC_OUT, mmio);
296 imx_phy_reg_read(&adc_out_reg, mmio);
298 if (adc_out_reg & 0x400)
302 if (read_attempt > attempt_limit) {
303 dev_err(dev, "Read REG more than %d times!\n",
313 imx_phy_reg_read(&adc_out_reg, mmio);
314 if (adc_out_reg & 0x400) {
315 read_sum = read_sum + (adc_out_reg & 0x3FF);
319 if (read_attempt > attempt_limit) {
320 dev_err(dev, "Read REG more than %d times!\n",
326 /* Use the U32 to make 1000 precision */
327 return (read_sum * 1000) / 80;
330 /* SATA AHCI temperature monitor */
331 static int __sata_ahci_read_temperature(void *dev, int *temp)
333 u16 mpll_test_reg, rtune_ctl_reg, dac_ctl_reg, read_sum;
334 u32 str1, str2, str3, str4;
336 struct ahci_host_priv *hpriv = dev_get_drvdata(dev);
337 void __iomem *mmio = hpriv->mmio;
339 /* check rd-wr to reg */
341 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio);
342 imx_phy_reg_write(read_sum, mmio);
343 imx_phy_reg_read(&read_sum, mmio);
344 if ((read_sum & 0xffff) != 0)
345 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
347 imx_phy_reg_write(0x5A5A, mmio);
348 imx_phy_reg_read(&read_sum, mmio);
349 if ((read_sum & 0xffff) != 0x5A5A)
350 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
352 imx_phy_reg_write(0x1234, mmio);
353 imx_phy_reg_read(&read_sum, mmio);
354 if ((read_sum & 0xffff) != 0x1234)
355 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
357 /* start temperature test */
358 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
359 imx_phy_reg_read(&mpll_test_reg, mmio);
360 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
361 imx_phy_reg_read(&rtune_ctl_reg, mmio);
362 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
363 imx_phy_reg_read(&dac_ctl_reg, mmio);
365 /* mpll_tst.meas_iv ([12:2]) */
366 str1 = (mpll_test_reg >> 2) & 0x7FF;
367 /* rtune_ctl.mode ([1:0]) */
368 str2 = (rtune_ctl_reg) & 0x3;
369 /* dac_ctl.dac_mode ([14:12]) */
370 str3 = (dac_ctl_reg >> 12) & 0x7;
371 /* rtune_ctl.sel_atbp ([4]) */
372 str4 = (rtune_ctl_reg >> 4);
374 /* Calculate the m1 */
375 /* mpll_tst.meas_iv */
376 mpll_test_reg = (mpll_test_reg & 0xE03) | (512) << 2;
378 rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (1);
379 /* dac_ctl.dac_mode */
380 dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (4) << 12;
381 /* rtune_ctl.sel_atbp */
382 rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (0) << 4;
383 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
384 imx_phy_reg_write(mpll_test_reg, mmio);
385 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
386 imx_phy_reg_write(dac_ctl_reg, mmio);
387 m1 = read_adc_sum(dev, rtune_ctl_reg, mmio);
389 /* Calculate the m2 */
390 /* rtune_ctl.sel_atbp */
391 rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (1) << 4;
392 m2 = read_adc_sum(dev, rtune_ctl_reg, mmio);
394 /* restore the status */
395 /* mpll_tst.meas_iv */
396 mpll_test_reg = (mpll_test_reg & 0xE03) | (str1) << 2;
398 rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (str2);
399 /* dac_ctl.dac_mode */
400 dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (str3) << 12;
401 /* rtune_ctl.sel_atbp */
402 rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (str4) << 4;
404 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
405 imx_phy_reg_write(mpll_test_reg, mmio);
406 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
407 imx_phy_reg_write(dac_ctl_reg, mmio);
408 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
409 imx_phy_reg_write(rtune_ctl_reg, mmio);
411 /* Compute temperature */
414 a = (m2 - m1) / (m2/1000);
415 *temp = ((-559) * a * a) / 1000 + (1379) * a + (-458000);
420 static int sata_ahci_read_temperature(struct thermal_zone_device *tz, int *temp)
422 return __sata_ahci_read_temperature(thermal_zone_device_priv(tz), temp);
425 static ssize_t sata_ahci_show_temp(struct device *dev,
426 struct device_attribute *da,
429 unsigned int temp = 0;
432 err = __sata_ahci_read_temperature(dev, &temp);
436 return sprintf(buf, "%u\n", temp);
439 static const struct thermal_zone_device_ops fsl_sata_ahci_of_thermal_ops = {
440 .get_temp = sata_ahci_read_temperature,
443 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, sata_ahci_show_temp, NULL, 0);
445 static struct attribute *fsl_sata_ahci_attrs[] = {
446 &sensor_dev_attr_temp1_input.dev_attr.attr,
449 ATTRIBUTE_GROUPS(fsl_sata_ahci);
451 static int imx8_sata_enable(struct ahci_host_priv *hpriv)
455 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
456 struct device *dev = &imxpriv->ahci_pdev->dev;
458 /* configure the hsio for sata */
459 ret = clk_prepare_enable(imxpriv->phy_pclk0);
461 dev_err(dev, "can't enable phy_pclk0.\n");
464 ret = clk_prepare_enable(imxpriv->phy_pclk1);
466 dev_err(dev, "can't enable phy_pclk1.\n");
467 goto disable_phy_pclk0;
469 ret = clk_prepare_enable(imxpriv->epcs_tx_clk);
471 dev_err(dev, "can't enable epcs_tx_clk.\n");
472 goto disable_phy_pclk1;
474 ret = clk_prepare_enable(imxpriv->epcs_rx_clk);
476 dev_err(dev, "can't enable epcs_rx_clk.\n");
477 goto disable_epcs_tx_clk;
479 ret = clk_prepare_enable(imxpriv->phy_apbclk);
481 dev_err(dev, "can't enable phy_apbclk.\n");
482 goto disable_epcs_rx_clk;
484 /* Configure PHYx2 PIPE_RSTN */
485 regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET +
486 IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val);
487 if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
488 /* The link of the PCIEA of HSIO is down */
489 regmap_update_bits(imxpriv->gpr,
490 IMX8QM_CSR_PHYX2_OFFSET,
491 IMX8QM_PHY_PIPE_RSTN_0 |
492 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0,
493 IMX8QM_PHY_PIPE_RSTN_0 |
494 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0);
496 regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET +
497 IMX8QM_CSR_PCIE_CTRL2_OFFSET, ®);
498 if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
499 /* The link of the PCIEB of HSIO is down */
500 regmap_update_bits(imxpriv->gpr,
501 IMX8QM_CSR_PHYX2_OFFSET,
502 IMX8QM_PHY_PIPE_RSTN_1 |
503 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1,
504 IMX8QM_PHY_PIPE_RSTN_1 |
505 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1);
507 if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
508 /* The links of both PCIA and PCIEB of HSIO are down */
509 regmap_update_bits(imxpriv->gpr,
510 IMX8QM_LPCG_PHYX2_OFFSET,
511 IMX8QM_LPCG_PHYX2_PCLK0_MASK |
512 IMX8QM_LPCG_PHYX2_PCLK1_MASK,
516 /* set PWR_RST and BT_RST of csr_pciea */
517 val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET;
518 regmap_update_bits(imxpriv->gpr,
520 IMX8QM_CTRL_BUTTON_RST_N,
521 IMX8QM_CTRL_BUTTON_RST_N);
522 regmap_update_bits(imxpriv->gpr,
524 IMX8QM_CTRL_POWER_UP_RST_N,
525 IMX8QM_CTRL_POWER_UP_RST_N);
527 /* PHYX1_MODE to SATA */
528 regmap_update_bits(imxpriv->gpr,
529 IMX8QM_CSR_PHYX1_OFFSET,
530 IMX8QM_PHY_MODE_MASK,
531 IMX8QM_PHY_MODE_SATA);
534 * BIT0 RXENA 1, BIT1 TXENA 0
535 * BIT12 PHY_X1_EPCS_SEL 1.
537 regmap_update_bits(imxpriv->gpr,
538 IMX8QM_CSR_MISC_OFFSET,
539 IMX8QM_MISC_IOB_RXENA,
540 IMX8QM_MISC_IOB_RXENA);
541 regmap_update_bits(imxpriv->gpr,
542 IMX8QM_CSR_MISC_OFFSET,
543 IMX8QM_MISC_IOB_TXENA,
545 regmap_update_bits(imxpriv->gpr,
546 IMX8QM_CSR_MISC_OFFSET,
547 IMX8QM_MISC_PHYX1_EPCS_SEL,
548 IMX8QM_MISC_PHYX1_EPCS_SEL);
550 * It is possible, for PCIe and SATA are sharing
551 * the same clock source, HPLL or external oscillator.
552 * When PCIe is in low power modes (L1.X or L2 etc),
553 * the clock source can be turned off. In this case,
554 * if this clock source is required to be toggling by
555 * SATA, then SATA functions will be abnormal.
556 * Set the override here to avoid it.
558 regmap_update_bits(imxpriv->gpr,
559 IMX8QM_CSR_MISC_OFFSET,
560 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
561 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
562 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
563 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0,
564 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
565 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
566 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
567 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0);
569 /* clear PHY RST, then set it */
570 regmap_update_bits(imxpriv->gpr,
571 IMX8QM_CSR_SATA_OFFSET,
572 IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
575 regmap_update_bits(imxpriv->gpr,
576 IMX8QM_CSR_SATA_OFFSET,
577 IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
578 IMX8QM_SATA_CTRL_EPCS_PHYRESET_N);
580 /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
581 regmap_update_bits(imxpriv->gpr,
582 IMX8QM_CSR_SATA_OFFSET,
583 IMX8QM_SATA_CTRL_RESET_N,
584 IMX8QM_SATA_CTRL_RESET_N);
586 regmap_update_bits(imxpriv->gpr,
587 IMX8QM_CSR_SATA_OFFSET,
588 IMX8QM_SATA_CTRL_RESET_N,
590 regmap_update_bits(imxpriv->gpr,
591 IMX8QM_CSR_SATA_OFFSET,
592 IMX8QM_SATA_CTRL_RESET_N,
593 IMX8QM_SATA_CTRL_RESET_N);
596 regmap_update_bits(imxpriv->gpr,
597 IMX8QM_CSR_PHYX1_OFFSET,
598 IMX8QM_PHY_APB_RSTN_0,
599 IMX8QM_PHY_APB_RSTN_0);
601 for (i = 0; i < 100; i++) {
602 reg = IMX8QM_CSR_PHYX1_OFFSET +
603 IMX8QM_CSR_PHYX_STTS0_OFFSET;
604 regmap_read(imxpriv->gpr, reg, &val);
605 val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
606 if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK)
611 if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) {
612 dev_err(dev, "TX PLL of the PHY is not locked\n");
615 writeb(imxpriv->imped_ratio, imxpriv->phy_base +
616 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
617 writeb(imxpriv->imped_ratio, imxpriv->phy_base +
618 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
619 reg = readb(imxpriv->phy_base +
620 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
621 if (unlikely(reg != imxpriv->imped_ratio))
622 dev_info(dev, "Can't set PHY RX impedance ratio.\n");
623 reg = readb(imxpriv->phy_base +
624 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
625 if (unlikely(reg != imxpriv->imped_ratio))
626 dev_info(dev, "Can't set PHY TX impedance ratio.\n");
627 usleep_range(50, 100);
630 * To reduce the power consumption, gate off
633 clk_disable_unprepare(imxpriv->phy_apbclk);
634 clk_disable_unprepare(imxpriv->phy_pclk1);
635 clk_disable_unprepare(imxpriv->phy_pclk0);
639 clk_disable_unprepare(imxpriv->phy_apbclk);
641 clk_disable_unprepare(imxpriv->epcs_rx_clk);
643 clk_disable_unprepare(imxpriv->epcs_tx_clk);
645 clk_disable_unprepare(imxpriv->phy_pclk1);
647 clk_disable_unprepare(imxpriv->phy_pclk0);
652 static int imx_sata_enable(struct ahci_host_priv *hpriv)
654 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
655 struct device *dev = &imxpriv->ahci_pdev->dev;
658 if (imxpriv->no_device)
661 ret = ahci_platform_enable_regulators(hpriv);
665 ret = clk_prepare_enable(imxpriv->sata_ref_clk);
667 goto disable_regulator;
669 if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
671 * set PHY Paremeters, two steps to configure the GPR13,
672 * one write for rest of parameters, mask of first write
673 * is 0x07ffffff, and the other one write for setting
676 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
677 IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
678 IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
679 IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
680 IMX6Q_GPR13_SATA_SPD_MODE_MASK |
681 IMX6Q_GPR13_SATA_MPLL_SS_EN |
682 IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
683 IMX6Q_GPR13_SATA_TX_BOOST_MASK |
684 IMX6Q_GPR13_SATA_TX_LVL_MASK |
685 IMX6Q_GPR13_SATA_MPLL_CLK_EN |
686 IMX6Q_GPR13_SATA_TX_EDGE_RATE,
687 imxpriv->phy_params);
688 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
689 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
690 IMX6Q_GPR13_SATA_MPLL_CLK_EN);
692 usleep_range(100, 200);
694 ret = imx_sata_phy_reset(hpriv);
696 dev_err(dev, "failed to reset phy: %d\n", ret);
699 } else if (imxpriv->type == AHCI_IMX8QM) {
700 ret = imx8_sata_enable(hpriv);
703 usleep_range(1000, 2000);
708 clk_disable_unprepare(imxpriv->sata_ref_clk);
710 ahci_platform_disable_regulators(hpriv);
715 static void imx_sata_disable(struct ahci_host_priv *hpriv)
717 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
719 if (imxpriv->no_device)
722 switch (imxpriv->type) {
724 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
725 IMX6Q_GPR5_SATA_SW_PD,
726 IMX6Q_GPR5_SATA_SW_PD);
727 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
728 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
729 !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
733 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
734 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
735 !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
739 clk_disable_unprepare(imxpriv->epcs_rx_clk);
740 clk_disable_unprepare(imxpriv->epcs_tx_clk);
747 clk_disable_unprepare(imxpriv->sata_ref_clk);
749 ahci_platform_disable_regulators(hpriv);
752 static void ahci_imx_error_handler(struct ata_port *ap)
755 struct ata_device *dev;
756 struct ata_host *host = dev_get_drvdata(ap->dev);
757 struct ahci_host_priv *hpriv = host->private_data;
758 void __iomem *mmio = hpriv->mmio;
759 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
761 ahci_error_handler(ap);
763 if (!(imxpriv->first_time) || ahci_imx_hotplug)
766 imxpriv->first_time = false;
768 ata_for_each_dev(dev, &ap->link, ENABLED)
771 * Disable link to save power. An imx ahci port can't be recovered
772 * without full reset once the pddq mode is enabled making it
773 * impossible to use as part of libata LPM.
775 reg_val = readl(mmio + IMX_P0PHYCR);
776 writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
777 imx_sata_disable(hpriv);
778 imxpriv->no_device = true;
780 dev_info(ap->dev, "no device found, disabling link.\n");
781 dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n");
784 static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
785 unsigned long deadline)
787 struct ata_port *ap = link->ap;
788 struct ata_host *host = dev_get_drvdata(ap->dev);
789 struct ahci_host_priv *hpriv = host->private_data;
790 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
793 if (imxpriv->type == AHCI_IMX53)
794 ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
796 ret = ahci_ops.softreset(link, class, deadline);
801 static struct ata_port_operations ahci_imx_ops = {
802 .inherits = &ahci_ops,
803 .host_stop = ahci_imx_host_stop,
804 .error_handler = ahci_imx_error_handler,
805 .softreset = ahci_imx_softreset,
808 static const struct ata_port_info ahci_imx_port_info = {
809 .flags = AHCI_FLAG_COMMON,
810 .pio_mask = ATA_PIO4,
811 .udma_mask = ATA_UDMA6,
812 .port_ops = &ahci_imx_ops,
815 static const struct of_device_id imx_ahci_of_match[] = {
816 { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
817 { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
818 { .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP },
819 { .compatible = "fsl,imx8qm-ahci", .data = (void *)AHCI_IMX8QM },
822 MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
829 struct reg_property {
831 const struct reg_value *values;
837 static const struct reg_value gpr13_tx_level[] = {
838 { 937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
839 { 947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
840 { 957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
841 { 966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
842 { 976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
843 { 986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
844 { 996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
845 { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
846 { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
847 { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
848 { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
849 { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
850 { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
851 { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
852 { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
853 { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
854 { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
855 { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
856 { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
857 { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
858 { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
859 { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
860 { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
861 { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
862 { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
863 { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
864 { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
865 { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
866 { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
867 { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
868 { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
869 { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
872 static const struct reg_value gpr13_tx_boost[] = {
873 { 0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
874 { 370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
875 { 740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
876 { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
877 { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
878 { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
879 { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
880 { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
881 { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
882 { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
883 { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
884 { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
885 { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
886 { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
887 { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
888 { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
891 static const struct reg_value gpr13_tx_atten[] = {
892 { 8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
893 { 9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
894 { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
895 { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
896 { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
897 { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
900 static const struct reg_value gpr13_rx_eq[] = {
901 { 500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
902 { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
903 { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
904 { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
905 { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
906 { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
907 { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
908 { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
911 static const struct reg_property gpr13_props[] = {
913 .name = "fsl,transmit-level-mV",
914 .values = gpr13_tx_level,
915 .num_values = ARRAY_SIZE(gpr13_tx_level),
916 .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
918 .name = "fsl,transmit-boost-mdB",
919 .values = gpr13_tx_boost,
920 .num_values = ARRAY_SIZE(gpr13_tx_boost),
921 .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
923 .name = "fsl,transmit-atten-16ths",
924 .values = gpr13_tx_atten,
925 .num_values = ARRAY_SIZE(gpr13_tx_atten),
926 .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
928 .name = "fsl,receive-eq-mdB",
929 .values = gpr13_rx_eq,
930 .num_values = ARRAY_SIZE(gpr13_rx_eq),
931 .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
933 .name = "fsl,no-spread-spectrum",
934 .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
939 static u32 imx_ahci_parse_props(struct device *dev,
940 const struct reg_property *prop, size_t num)
942 struct device_node *np = dev->of_node;
946 for (i = 0; i < num; i++, prop++) {
949 if (prop->num_values == 0) {
950 if (of_property_read_bool(np, prop->name))
951 reg_value |= prop->set_value;
953 reg_value |= prop->def_value;
957 if (of_property_read_u32(np, prop->name, &of_val)) {
958 dev_info(dev, "%s not specified, using %08x\n",
959 prop->name, prop->def_value);
960 reg_value |= prop->def_value;
964 for (j = 0; j < prop->num_values; j++) {
965 if (prop->values[j].of_value == of_val) {
966 dev_info(dev, "%s value %u, using %08x\n",
967 prop->name, of_val, prop->values[j].reg_value);
968 reg_value |= prop->values[j].reg_value;
973 if (j == prop->num_values) {
974 dev_err(dev, "DT property %s is not a valid value\n",
976 reg_value |= prop->def_value;
983 static const struct scsi_host_template ahci_platform_sht = {
987 static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv)
989 struct resource *phy_res;
990 struct platform_device *pdev = imxpriv->ahci_pdev;
991 struct device_node *np = dev->of_node;
993 if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio))
994 imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM;
995 phy_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
997 imxpriv->phy_base = devm_ioremap(dev, phy_res->start,
998 resource_size(phy_res));
999 if (!imxpriv->phy_base) {
1000 dev_err(dev, "error with ioremap\n");
1004 dev_err(dev, "missing *phy* reg region.\n");
1008 syscon_regmap_lookup_by_phandle(np, "hsio");
1009 if (IS_ERR(imxpriv->gpr)) {
1010 dev_err(dev, "unable to find gpr registers\n");
1011 return PTR_ERR(imxpriv->gpr);
1014 imxpriv->epcs_tx_clk = devm_clk_get(dev, "epcs_tx");
1015 if (IS_ERR(imxpriv->epcs_tx_clk)) {
1016 dev_err(dev, "can't get epcs_tx_clk clock.\n");
1017 return PTR_ERR(imxpriv->epcs_tx_clk);
1019 imxpriv->epcs_rx_clk = devm_clk_get(dev, "epcs_rx");
1020 if (IS_ERR(imxpriv->epcs_rx_clk)) {
1021 dev_err(dev, "can't get epcs_rx_clk clock.\n");
1022 return PTR_ERR(imxpriv->epcs_rx_clk);
1024 imxpriv->phy_pclk0 = devm_clk_get(dev, "phy_pclk0");
1025 if (IS_ERR(imxpriv->phy_pclk0)) {
1026 dev_err(dev, "can't get phy_pclk0 clock.\n");
1027 return PTR_ERR(imxpriv->phy_pclk0);
1029 imxpriv->phy_pclk1 = devm_clk_get(dev, "phy_pclk1");
1030 if (IS_ERR(imxpriv->phy_pclk1)) {
1031 dev_err(dev, "can't get phy_pclk1 clock.\n");
1032 return PTR_ERR(imxpriv->phy_pclk1);
1034 imxpriv->phy_apbclk = devm_clk_get(dev, "phy_apbclk");
1035 if (IS_ERR(imxpriv->phy_apbclk)) {
1036 dev_err(dev, "can't get phy_apbclk clock.\n");
1037 return PTR_ERR(imxpriv->phy_apbclk);
1040 /* Fetch GPIO, then enable the external OSC */
1041 imxpriv->clkreq_gpiod = devm_gpiod_get_optional(dev, "clkreq",
1042 GPIOD_OUT_LOW | GPIOD_FLAGS_BIT_NONEXCLUSIVE);
1043 if (IS_ERR(imxpriv->clkreq_gpiod))
1044 return PTR_ERR(imxpriv->clkreq_gpiod);
1045 if (imxpriv->clkreq_gpiod)
1046 gpiod_set_consumer_name(imxpriv->clkreq_gpiod, "SATA CLKREQ");
1051 static int imx_ahci_probe(struct platform_device *pdev)
1053 struct device *dev = &pdev->dev;
1054 struct ahci_host_priv *hpriv;
1055 struct imx_ahci_priv *imxpriv;
1056 unsigned int reg_val;
1059 imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
1063 imxpriv->ahci_pdev = pdev;
1064 imxpriv->no_device = false;
1065 imxpriv->first_time = true;
1066 imxpriv->type = (enum ahci_imx_type)device_get_match_data(dev);
1068 imxpriv->sata_clk = devm_clk_get(dev, "sata");
1069 if (IS_ERR(imxpriv->sata_clk)) {
1070 dev_err(dev, "can't get sata clock.\n");
1071 return PTR_ERR(imxpriv->sata_clk);
1074 imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
1075 if (IS_ERR(imxpriv->sata_ref_clk)) {
1076 dev_err(dev, "can't get sata_ref clock.\n");
1077 return PTR_ERR(imxpriv->sata_ref_clk);
1080 imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
1081 if (IS_ERR(imxpriv->ahb_clk)) {
1082 dev_err(dev, "can't get ahb clock.\n");
1083 return PTR_ERR(imxpriv->ahb_clk);
1086 if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
1089 imxpriv->gpr = syscon_regmap_lookup_by_compatible(
1090 "fsl,imx6q-iomuxc-gpr");
1091 if (IS_ERR(imxpriv->gpr)) {
1093 "failed to find fsl,imx6q-iomux-gpr regmap\n");
1094 return PTR_ERR(imxpriv->gpr);
1097 reg_value = imx_ahci_parse_props(dev, gpr13_props,
1098 ARRAY_SIZE(gpr13_props));
1100 imxpriv->phy_params =
1101 IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
1102 IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
1103 IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
1105 } else if (imxpriv->type == AHCI_IMX8QM) {
1106 ret = imx8_sata_probe(dev, imxpriv);
1111 hpriv = ahci_platform_get_resources(pdev, 0);
1113 return PTR_ERR(hpriv);
1115 hpriv->plat_data = imxpriv;
1117 ret = clk_prepare_enable(imxpriv->sata_clk);
1121 if (imxpriv->type == AHCI_IMX53 &&
1122 IS_ENABLED(CONFIG_HWMON)) {
1123 /* Add the temperature monitor */
1124 struct device *hwmon_dev;
1127 devm_hwmon_device_register_with_groups(dev,
1130 fsl_sata_ahci_groups);
1131 if (IS_ERR(hwmon_dev)) {
1132 ret = PTR_ERR(hwmon_dev);
1135 devm_thermal_of_zone_register(hwmon_dev, 0, hwmon_dev,
1136 &fsl_sata_ahci_of_thermal_ops);
1137 dev_info(dev, "%s: sensor 'sata_ahci'\n", dev_name(hwmon_dev));
1140 ret = imx_sata_enable(hpriv);
1145 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
1146 * and IP vendor specific register IMX_TIMER1MS.
1147 * Configure CAP_SSS (support stagered spin up).
1148 * Implement the port0.
1149 * Get the ahb clock rate, and configure the TIMER1MS register.
1151 reg_val = readl(hpriv->mmio + HOST_CAP);
1152 if (!(reg_val & HOST_CAP_SSS)) {
1153 reg_val |= HOST_CAP_SSS;
1154 writel(reg_val, hpriv->mmio + HOST_CAP);
1156 reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
1157 if (!(reg_val & 0x1)) {
1159 writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
1162 reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
1163 writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
1165 ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
1166 &ahci_platform_sht);
1173 imx_sata_disable(hpriv);
1175 clk_disable_unprepare(imxpriv->sata_clk);
1179 static void ahci_imx_host_stop(struct ata_host *host)
1181 struct ahci_host_priv *hpriv = host->private_data;
1182 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
1184 imx_sata_disable(hpriv);
1185 clk_disable_unprepare(imxpriv->sata_clk);
1188 #ifdef CONFIG_PM_SLEEP
1189 static int imx_ahci_suspend(struct device *dev)
1191 struct ata_host *host = dev_get_drvdata(dev);
1192 struct ahci_host_priv *hpriv = host->private_data;
1195 ret = ahci_platform_suspend_host(dev);
1199 imx_sata_disable(hpriv);
1204 static int imx_ahci_resume(struct device *dev)
1206 struct ata_host *host = dev_get_drvdata(dev);
1207 struct ahci_host_priv *hpriv = host->private_data;
1210 ret = imx_sata_enable(hpriv);
1214 return ahci_platform_resume_host(dev);
1218 static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
1220 static struct platform_driver imx_ahci_driver = {
1221 .probe = imx_ahci_probe,
1222 .remove_new = ata_platform_remove_one,
1225 .of_match_table = imx_ahci_of_match,
1226 .pm = &ahci_imx_pm_ops,
1229 module_platform_driver(imx_ahci_driver);
1231 MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
1232 MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
1233 MODULE_LICENSE("GPL");
1234 MODULE_ALIAS("platform:" DRV_NAME);