2 * fw/board_atusb.c - ATUSB Board-specific functions (for boot loader and application)
4 * Written 2016 by Stefan Schmidt
5 * Copyright 2016 Stefan Schmidt
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
18 #include <avr/interrupt.h>
21 #define F_CPU 8000000UL
22 #include <util/delay.h>
25 #include "at86rf230.h"
30 static bool spi_initialized = 0;
34 /* set up all the outputs; default port value is 0 */
44 OUT(nRST_RF); /* this also resets the transceiver */
49 /* AT86RF231 data sheet, 12.4.13, reset pulse width: 625 ns (min) */
55 /* 12.4.14: SPI access latency after reset: 625 ns (min) */
59 /* we must restore TRX_CTRL_0 after each reset (9.6.4) */
74 /* switch CLKM to 8 MHz */
77 * @@@ Note: Atmel advise against changing the external clock in
78 * mid-flight. We should therefore switch to the RC clock first, then
79 * crank up the external clock, and finally switch back to the external
80 * clock. The clock switching procedure is described in the ATmega32U2
81 * data sheet in secton 8.2.2.
84 spi_send(AT86RF230_REG_WRITE | REG_TRX_CTRL_0);
85 spi_send(CLKM_CTRL_8MHz);
91 /* Disable the watchdog timer */
93 MCUSR = 0; /* Remove override */
94 WDTCSR |= 1 << WDCE; /* Enable change */
95 WDTCSR = 1 << WDCE; /* Disable watchdog while still enabling
99 /* We start with a 1 MHz/8 clock. Disable the prescaler. */
107 if (!spi_initialized)
126 UBRR1 = 0; /* set bit rate to zero to begin */
127 UCSR1C = 1 << UMSEL11 | 1 << UMSEL10;
128 /* set MSPI, MSB first, SPI data mode 0 */
129 UCSR1B = 1 << RXEN1 | 1 << TXEN1;
130 /* enable receiver and transmitter */
131 UBRR1 = 0; /* reconfirm the bit rate */
138 USBCON |= 1 << FRZCLK; /* freeze the clock */
140 /* enable the PLL and wait for it to lock */
141 PLLCSR &= ~(1 << PLLP2 | 1 << PLLP1 | 1 << PLLP0);
143 while (!(PLLCSR & (1 << PLOCK)));
145 USBCON &= ~(1 << USBE); /* reset the controller */
148 USBCON &= ~(1 << FRZCLK); /* thaw the clock */
150 UDCON &= ~(1 << DETACH); /* attach the pull-up */
151 UDIEN = 1 << EORSTE; /* enable device interrupts */
152 // UDCON |= 1 << RSTCPU; /* reset CPU on bus reset */
157 void board_app_init(void)
159 /* enable INT0, trigger on rising edge */
160 EICRA = 1 << ISC01 | 1 << ISC00;