2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #ifndef _DEV_ATH_ATHVAR_H
37 #define _DEV_ATH_ATHVAR_H
40 #include <adf_os_types.h>
41 #include <adf_os_dma.h>
42 #include <adf_os_timer.h>
43 #include <adf_os_lock.h>
44 #include <adf_os_io.h>
45 #include <adf_os_mem.h>
46 #include <adf_os_util.h>
47 #include <adf_os_stdtypes.h>
48 #include <adf_os_defer.h>
49 #include <adf_os_atomic.h>
52 #include <adf_net_types.h>
53 #include <adf_net_wcmd.h>
54 #include <asf_queue.h>
57 #include "ieee80211_var.h"
58 #include "ieee80211_node.h"
59 #include "if_athrate.h"
61 #include <Magpie_api.h>
62 #include <htc_services.h>
67 #define tq_struct adf_os_bh_t
68 #define ATH_INIT_TQUEUE(a,b,c,d) adf_os_init_bh((a),(b),(c),(void *)(d))
69 #define ATH_SCHEDULE_TQUEUE(a,b) adf_os_sched_bh((a),(b))
70 typedef void * TQUEUE_ARG;
72 #define ATH_MIN(a,b) ((a) < (b) ? (a) : (b))
73 #define ATH_AC_2_TXQ(_sc, _ac) (_sc)->sc_ac2q[(_ac)]
74 #define TID_TO_ACTXQ(tidno) sc->sc_ac2q[ TID_TO_WME_AC(tidno)]
76 #define RATE_TABLE_SIZE 32
78 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
80 #define IEEE80211_SEQ_MAX 4096
81 #define SEQNO_FROM_BF_SEQNO(_x) (_x >> IEEE80211_SEQ_SEQ_SHIFT)
82 #define BAW_WITHIN(_start, _bawsz, _seqno) \
83 ((((_seqno) - (_start)) & 4095) < (_bawsz))
85 #define __stats(sc, _x) sc->sc_tx_stats._x ++
86 #define __statsn(sc, _x, _n) sc->sc_tx_stats._x += _n
88 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
92 ATH_TGT_AGGR_BAW_CLOSED,
98 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
99 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
101 #define ATH_DS_BA_SEQ(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_seqnum
102 #define ATH_DS_BA_BITMAP(_ds) (&((struct ath_tx_desc *)_ds)->ds_us.tx.ba_low)
103 #define ATH_DS_TX_BA(_ds) (((struct ath_tx_desc *)_ds)->ds_us.tx.ts_flags & HAL_TX_BA)
104 #define ATH_DS_TX_STATUS(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_status
105 #define ATH_DS_TX_FLAGS(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_flags
106 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
108 #define ATH_AGGR_DELIM_SZ 4
109 #define ATH_AGGR_MINPLEN 256
110 #define ATH_AGGR_ENCRYPTDELIM 10
112 #define ATH_AGGR_GET_NDELIM(_len) \
113 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
114 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
116 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
117 #define OWLMAX_RETRIES 10
118 #define OWLMAX_BAR_RETRIES 10
120 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
123 #define ATH_TXMAXTRY 11
124 #define TARGET_NODE_MAX ATH_NODE_MAX
125 #define TARGET_VAP_MAX ATH_VAP_MAX
127 #define MAX_RATE_POWER 63
128 #define ATH_COMP_PROC_NO_COMP_NO_CCS 3
130 #define ATH_BUFSTATUS_DONE 0x00000001 /* hw processing complete, desc processed by hal */
132 #define ATH_AGGR_MIN_QDEPTH 1
134 struct ath_softc_tgt;
138 #define ATH_TXQ(_sc, _qi) (&(_sc)->sc_txq[(_qi)])
139 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
141 #define ATH_NODE_TARGET(_n) ((struct ath_node_target *)(_n))
144 * Built-in implementation for skb free.
146 #define ath_free_rx_skb(_sc,_skb) BUF_Pool_free_buf(_sc->pool_handle, POOL_ID_WLAN_RX_BUF, _skb)
147 #define ath_free_tx_skb(_htc_handle, endpt, _skb) HTC_ReturnBuffers(_htc_handle, endpt, _skb);
151 typedef void (*ath_txq_add_fn_t)(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
152 typedef void (*ath_tx_comp_fn_t)(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
154 struct ath_buf_state {
155 ath_tx_comp_fn_t bfs_comp; /* completion function */
156 ath_txq_add_fn_t bfs_txq_add; /* txq buffer add function */
157 a_uint16_t bfs_pktlen; /* pktlen including crc */
158 a_uint16_t bfs_seqno; /* sequence nuber */
159 a_uint8_t bfs_hdrlen; /* header length */
160 a_uint8_t bfs_keyix; /* key index */
161 a_uint8_t bfs_atype; /* packet type */
162 a_uint8_t bfs_ndelim; /* # delims for padding */
163 a_uint8_t bfs_nframes; /* # frames in aggregate */
164 a_uint8_t bfs_tidno; /* tid of the buffer */
165 a_uint16_t bfs_al; /* length of aggregate */
166 struct ath_rc_series bfs_rcs[4]; /* rate series */
167 struct ath_txq *bfs_txq; /* transmit h/w queue */
168 a_uint8_t bfs_protmode; /* protection mode */
169 a_uint8_t bfs_keytype; /* encr key type */
170 a_uint8_t bfs_retries; /* current retries */
171 a_uint32_t bfs_ismcast : 1; /* is multicast */
172 a_uint32_t bfs_shpream : 1; /* use short preamble */
173 a_uint32_t bfs_isaggr : 1; /* is an aggregate */
174 a_uint32_t bfs_isretried: 1; /* is retried */
177 #define bf_comp bf_state.bfs_comp
178 #define bf_txq_add bf_state.bfs_txq_add
179 #define bf_pktlen bf_state.bfs_pktlen
180 #define bf_hdrlen bf_state.bfs_hdrlen
181 #define bf_keyix bf_state.bfs_keyix
182 #define bf_atype bf_state.bfs_atype
183 #define bf_seqno bf_state.bfs_seqno
184 #define bf_ndelim bf_state.bfs_ndelim
185 #define bf_nframes bf_state.bfs_nframes
186 #define bf_al bf_state.bfs_al
187 #define bf_tidno bf_state.bfs_tidno
188 #define bf_rcs bf_state.bfs_rcs
189 #define bf_txq bf_state.bfs_txq
190 #define bf_protmode bf_state.bfs_protmode
191 #define bf_keytype bf_state.bfs_keytype
192 #define bf_ismcast bf_state.bfs_ismcast
193 #define bf_shpream bf_state.bfs_shpream
194 #define bf_isaggr bf_state.bfs_isaggr
195 #define bf_isretried bf_state.bfs_isretried
196 #define bf_retries bf_state.bfs_retries
198 #define ATH_GENERIC_BUF \
199 adf_os_dma_map_t bf_dmamap; \
200 adf_os_dmamap_info_t bf_dmamap_info; \
201 struct ieee80211_node_target *bf_node; \
202 adf_nbuf_queue_t bf_skbhead; \
208 asf_tailq_entry(ath_buf) bf_list;
209 struct ath_buf *bf_next;
210 struct ath_desc *bf_lastds;
211 struct ath_desc *bf_desc;
212 struct ath_desc *bf_descarr;
218 asf_tailq_entry(ath_tx_buf) bf_list;
219 struct ath_tx_buf *bf_next;
220 struct ath_tx_desc *bf_desc;
221 struct ath_tx_desc *bf_descarr;
222 struct ath_tx_desc *bf_lastds;
223 struct ath_buf_state bf_state;
225 HTC_ENDPOINT_ID bf_endpt;
234 asf_tailq_entry(ath_rx_buf) bf_list;
235 struct ath_rx_buf *bf_next;
236 struct ath_rx_desc *bf_desc;
237 struct ath_rx_desc *bf_descarr;
238 struct ath_rx_desc *bf_lastds;
239 a_uint32_t bf_status;
240 struct ath_rx_status bf_rx_status;
243 #define ATH_BUF_GET_DESC_PHY_ADDR(bf) (a_uint32_t)bf->bf_desc
244 #define ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, idx) (adf_os_dma_addr_t)(&bf->bf_descarr[idx])
245 #define ATH_BUF_SET_DESC_PHY_ADDR(bf, addr)
246 #define ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, idx, addr)
248 typedef asf_tailq_head(ath_deschead_s, ath_rx_desc) ath_deschead;
249 typedef asf_tailq_head(ath_bufhead_s, ath_buf) ath_bufhead;
250 typedef asf_tailq_head(ath_rx_bufhead_s, ath_rx_buf) ath_rx_bufhead;
251 typedef asf_tailq_head(ath_tx_bufhead_s, ath_tx_buf) ath_tx_bufhead;
253 #define WME_NUM_TID 8
254 #define WME_BA_BMP_SIZE 64
255 #define WME_MAX_BA WME_BA_BMP_SIZE
256 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
257 #define TID_CLEANUP_INPROGRES 0x1
258 #define TID_AGGR_ENABLED 0x2
259 #define TID_REINITIALIZE 0x4
261 #define TAILQ_DEQ(_q, _elm, _field) do { \
262 (_elm) = asf_tailq_first((_q)); \
264 asf_tailq_remove((_q), (_elm), _field); \
268 #define TX_BUF_BITMAP_SIZE 32
269 #define TX_BUF_BITMAP_SET(bitmap, i) bitmap[i>>5] |= ((a_uint32_t)1 << (i&0x1f))
270 #define TX_BUF_BITMAP_CLR(bitmap, i) bitmap[i>>5] &= (~((a_uint32_t)1 << (i&0x1f)))
271 #define TX_BUF_BITMAP_IS_SET(bitmap, i) ((bitmap[i>>5] & ((a_uint32_t)1 << (i&0x1f))) != 0)
273 typedef struct ath_atx_tid {
275 a_uint16_t seq_start;
280 a_uint32_t tx_buf_bitmap[ATH_TID_MAX_BUFS/TX_BUF_BITMAP_SIZE];
281 asf_tailq_entry(ath_atx_tid) tid_qelem;
282 asf_tailq_head(ath_tid_rbq,ath_tx_buf) buf_q;
287 struct ath_node_target *an;
290 struct ath_node_target {
291 struct ieee80211_node_target ni;
292 struct ath_atx_tid tid[WME_NUM_TID];
298 const a_int8_t *dd_name;
299 struct ath_desc *dd_desc;
300 adf_os_dma_map_t dd_desc_dmamap;
301 adf_os_dma_addr_t dd_desc_paddr;
302 adf_os_size_t dd_desc_len;
303 struct ath_buf *dd_bufptr;
308 a_uint32_t *axq_link;
309 asf_tailq_head(,ath_tx_buf) axq_q;
310 a_uint32_t axq_depth;
311 struct ath_tx_buf *axq_linkbuf;
312 asf_tailq_head(,ath_atx_tid) axq_tidq;
315 struct wmi_rc_rate_mask_cmd {
322 struct ath_vap_target {
323 struct ieee80211vap_target av_vap;
324 struct ath_txq av_mcastq;
325 struct ath_tx_buf *av_bcbuf;
326 a_uint32_t av_rate_mask[2]; /* 0 - 2G, 1 - 5G */
327 a_uint8_t av_minrateidx[2]; /* 0 - 2G, 1 - 5G */
331 #define ATH_RXBUF_RESET(bf) \
336 /* Target-side HTC/HIF/WMI related data structure */
337 pool_handle_t pool_handle;
338 hif_handle_t tgt_hif_handle;
339 htc_handle_t tgt_htc_handle;
340 wmi_handle_t tgt_wmi_handle;
342 /* Target HTC Service IDs */
343 HTC_SERVICE htc_beacon_service;
344 HTC_SERVICE htc_cab_service;
345 HTC_SERVICE htc_uapsd_service;
346 HTC_SERVICE htc_mgmt_service;
347 HTC_SERVICE htc_data_VO_service;
348 HTC_SERVICE htc_data_VI_service;
349 HTC_SERVICE htc_data_BE_service;
350 HTC_SERVICE htc_data_BK_service;
353 /* Target HTC Endpoint IDs */
354 HTC_ENDPOINT_ID wmi_command_ep;
355 HTC_ENDPOINT_ID beacon_ep;
356 HTC_ENDPOINT_ID cab_ep;
357 HTC_ENDPOINT_ID uapsd_ep;
358 HTC_ENDPOINT_ID mgmt_ep;
359 HTC_ENDPOINT_ID data_VO_ep;
360 HTC_ENDPOINT_ID data_VI_ep;
361 HTC_ENDPOINT_ID data_BE_ep;
362 HTC_ENDPOINT_ID data_BK_ep;
364 adf_os_handle_t sc_hdl;
365 adf_os_device_t sc_dev;
367 struct ath_ratectrl *sc_rc;
369 a_uint32_t sc_invalid : 1,
373 a_int32_t sc_rxbufsize;
374 a_uint16_t sc_cachelsz;
376 struct ath_interrupt_stats sc_int_stats;
377 struct ath_tx_stats sc_tx_stats;
378 struct ath_rx_stats sc_rx_stats;
380 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
381 const HAL_RATE_TABLE *sc_currates;
383 a_uint8_t sc_rixmap[256];
385 enum ieee80211_phymode sc_curmode;
387 a_uint8_t sc_protrix;
391 tq_struct sc_bmisstq;
393 tq_struct sc_fataltq;
395 ath_rx_bufhead sc_rxbuf;
397 ath_deschead sc_rxdesc_idle;
398 ath_deschead sc_rxdesc;
399 struct ath_rx_desc *sc_rxdesc_held;
401 struct ath_tx_buf *sc_txbuf_held;
403 struct ath_descdma sc_rxdma;
404 struct ath_descdma sc_txdma;
405 struct ath_descdma sc_bdma;
407 a_uint32_t *sc_rxlink;
408 ath_tx_bufhead sc_txbuf;
409 a_uint8_t sc_txqsetup;
411 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
412 struct ath_txq *sc_ac2q[WME_NUM_AC];
415 struct ath_hal *sc_ah;
416 struct ath_txq *sc_cabq;
417 struct ath_txq *sc_uapsdq;
418 struct ath_node_target sc_sta[TARGET_NODE_MAX];
419 struct ath_vap_target sc_vap[TARGET_VAP_MAX];
420 struct ieee80211com_target sc_ic;
422 ath_tx_bufhead sc_bbuf;
423 a_uint64_t sc_swba_tsf;
425 WMI_TXSTATUS_EVENT tx_status[2];
428 #define SM(_v, _f) (((_v) << _f##_S) & _f)
429 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
431 #define ATH9K_HTC_TXSTAT_ACK 1<<0
432 #define ATH9K_HTC_TXSTAT_FILT 1<<1
433 #define ATH9K_HTC_TXSTAT_RTC_CTS 1<<2
434 #define ATH9K_HTC_TXSTAT_MCS 1<<3
435 #define ATH9K_HTC_TXSTAT_CW40 1<<4
436 #define ATH9K_HTC_TXSTAT_SGI 1<<5
438 #define ATH9K_HTC_TXSTAT_RATE 0x0f
439 #define ATH9K_HTC_TXSTAT_RATE_S 0
440 #define ATH9K_HTC_TXSTAT_EPID 0xf0
441 #define ATH9K_HTC_TXSTAT_EPID_S 4
443 #define TAILQ_INSERTQ_HEAD(head, tq, field) do { \
444 if ((head)->tqh_first) { \
445 *(tq)->tqh_last = (head)->tqh_first; \
446 (head)->tqh_first->field.tqe_prev = (tq)->tqh_last; \
448 (head)->tqh_last = (tq)->tqh_last; \
450 (head)->tqh_first = (tq)->tqh_first; \
451 (tq)->tqh_first->field.tqe_prev = &(head)->tqh_first; \
454 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
455 asf_tailq_insert_tail( &(_tq)->axq_q, (_elm), _field); \
456 (_tq)->axq_depth++; \
457 (_tq)->axq_linkbuf = (_elm); \
459 #define ATH_TXQ_REMOVE_HEAD(_tq, _elm, _field) do { \
460 asf_tailq_remove(&(_tq)->axq_q, (_elm), _field); \
461 (_tq)->axq_depth--; \
464 struct ieee80211_rate {
465 struct ieee80211_rateset rates;
466 struct ieee80211_rateset htrates;
467 } __attribute__((packed));
469 struct wmi_rc_state_change_cmd {
474 struct ieee80211_rate rs;
475 } __attribute__((packed));
477 struct wmi_rc_rate_update_cmd {
478 a_uint8_t node_index;
482 struct ieee80211_rate rs;
483 } __attribute__((packed));
491 a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp);
492 void ath_tgt_tx_cleanup(struct ath_softc_tgt *sc, struct ath_node_target *an,
493 ath_atx_tid_t *tid, a_uint8_t discard_all);
494 void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
495 void ath_tgt_handle_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
496 void ath_tgt_tid_drain(struct ath_softc_tgt *sc, struct ath_atx_tid *tid);
497 void ath_tx_status_clear(struct ath_softc_tgt *sc);
499 void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id,
500 void *buffer, a_int32_t Length);
502 #endif /* _DEV_ATH_ATHVAR_H */