2 * Copyright (C) 2006-2007 Michael Buesch <mb@bu3sch.de>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2
6 * as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
26 extern int yyparse(void);
30 const char *infile_name;
31 const char *outfile_name;
41 unsigned int operand; /* For NORMAL */
42 struct label *label; /* For LABELREF */
52 /* Set to true, if this is a jump instruction.
53 * This is only used when assembling RET to check
54 * whether the previous instruction was a jump or not. */
58 struct out_operand operands[3];
60 /* The absolute address of this instruction.
61 * Only used in resolve_labels(). */
64 const char *labelname; /* only for OUT_LABEL */
65 /* Set to 1, if this is the %start instruction. */
68 struct list_head list;
71 struct assembler_context {
72 /* The architecture version (802.11 core revision) */
75 struct label *start_label;
78 struct statement *cur_stmt;
80 struct list_head output;
84 #define for_each_statement(ctx, s) \
85 list_for_each_entry(s, &infile.sl, list) { \
88 #define for_each_statement_end(ctx, s) \
89 } do { ctx->cur_stmt = NULL; } while (0)
91 #define _msg_helper(type, stmt, msg, x...) do { \
92 fprintf(stderr, "Assembler " type); \
94 fprintf(stderr, " (file \"%s\", line %u)", \
98 fprintf(stderr, ":\n " msg "\n" ,##x); \
101 #define asm_error(ctx, msg, x...) do { \
102 _msg_helper("ERROR", (ctx)->cur_stmt, msg ,##x); \
106 #define asm_warn(ctx, msg, x...) \
107 _msg_helper("warning", (ctx)->cur_stmt, msg ,##x)
109 #define asm_info(ctx, msg, x...) \
110 _msg_helper("info", (ctx)->cur_stmt, msg ,##x)
113 static void eval_directives(struct assembler_context *ctx)
118 int have_start_label = 0;
121 for_each_statement(ctx, s) {
122 if (s->type == STMT_ASMDIR) {
127 asm_error(ctx, "Multiple %%arch definitions");
128 ctx->arch = ad->u.arch;
129 if (ctx->arch != 5 && ctx->arch != 15) {
130 asm_error(ctx, "Architecture version %u unsupported",
136 if (have_start_label)
137 asm_error(ctx, "Multiple %%start definitions");
138 ctx->start_label = ad->u.start;
139 have_start_label = 1;
142 asm_error(ctx, "Unknown ASM directive");
145 } for_each_statement_end(ctx, s);
148 asm_error(ctx, "No %%arch defined");
149 if (!have_start_label)
150 asm_info(ctx, "Using start address 0");
153 static bool is_possible_imm(unsigned int imm)
157 /* Immediates are only possible up to 16bit (wordsize). */
160 if (imm & (1 << 15)) {
161 if ((imm & mask) != mask &&
165 if ((imm & mask) != 0)
172 static bool is_valid_imm(struct assembler_context *ctx,
176 unsigned int immediate_size;
178 /* This function checks if the immediate value is representable
179 * as a native immediate operand.
181 * For v5 architecture the immediate can be 10bit long.
182 * For v15 architecture the immediate can be 11bit long.
184 * The value is sign-extended, so we allow values
185 * of 0xFFFA, for example.
188 if (!is_possible_imm(imm))
192 if (ctx->arch == 5) {
193 immediate_size = 10; /* 10bit */
194 } else if (ctx->arch == 15) {
195 immediate_size = 11; /* 11bit */
197 asm_error(ctx, "Unknown immediate size for arch %u",
201 /* First create a mask with all possible bits for
202 * an immediate value unset. */
203 mask = (~0 << immediate_size) & 0xFFFF;
204 /* Is the sign bit of the immediate set? */
205 if (imm & (1 << (immediate_size - 1))) {
206 /* Yes, so all bits above that must also
207 * be set, otherwise we can't represent this
208 * value in an operand. */
209 if ((imm & mask) != mask)
212 /* All bits above the immediate's size must
221 /* This checks if the value is nonzero and a power of two. */
222 static bool is_power_of_two(unsigned int value)
224 return (value && ((value & (value - 1)) == 0));
227 /* This checks if all bits set in the mask are contiguous.
228 * Zero is also considered a contiguous mask. */
229 static bool is_contiguous_bitmask(unsigned int mask)
231 unsigned int low_zeros_mask;
236 /* Turn the lowest zeros of the mask into a bitmask.
237 * Example: 0b00011000 -> 0b00000111 */
238 low_zeros_mask = (mask - 1) & ~mask;
239 /* Adding the low_zeros_mask to the original mask
240 * basically is a bitwise OR operation.
241 * If the original mask was contiguous, we end up with a
242 * contiguous bitmask from bit 0 to the highest bit
243 * set in the original mask. Adding 1 will result in a single
244 * bit set, which is a power of two. */
245 is_contiguous = is_power_of_two(mask + low_zeros_mask + 1);
247 return is_contiguous;
250 static unsigned int generate_imm_operand(struct assembler_context *ctx,
251 const struct immediate *imm)
253 unsigned int val, tmp;
256 /* format: 0b11ii iiii iiii */
263 if (!is_valid_imm(ctx, tmp)) {
264 asm_warn(ctx, "IMMEDIATE 0x%X (%d) too long "
265 "(> 9 bits + sign). Did you intend to "
266 "use implicit sign extension?",
279 static unsigned int generate_reg_operand(struct assembler_context *ctx,
280 const struct registr *reg)
282 unsigned int val = 0;
286 /* format: 0b1011 11rr rrrr */
290 if (reg->nr & ~0x3F) //FIXME 128 regs for v15 arch possible?
291 asm_error(ctx, "GPR-nr too big");
295 /* format: 0b100. .... .... */
299 if (reg->nr & ~0x1FF)
300 asm_error(ctx, "SPR-nr too big");
304 /* format: 0b1000 0110 0rrr */
309 asm_error(ctx, "OFFR-nr too big");
313 asm_error(ctx, "generate_reg_operand() regtype");
319 static unsigned int generate_mem_operand(struct assembler_context *ctx,
320 const struct memory *mem)
322 unsigned int val = 0, off, reg;
326 /* format: 0b0mmm mmmm mmmm */
328 if (off & ~0x7FF) { //FIXME 4096 words for v15 arch possible?
329 asm_warn(ctx, "DIRECT memoffset 0x%X too long (> 11 bits)", off);
335 /* format: 0b101r rroo oooo */
339 //FIXME what about v15 arch?
341 asm_warn(ctx, "INDIRECT memoffset 0x%X too long (> 6 bits)", off);
345 /* Assembler bug. The parser shouldn't pass this value. */
346 asm_error(ctx, "OFFR-nr too big");
349 asm_warn(ctx, "Using offset register 6. This register is broken "
350 "on certain devices. Use off0 to off5 only.");
356 asm_error(ctx, "generate_mem_operand() memtype");
362 static void generate_operand(struct assembler_context *ctx,
363 const struct operand *oper,
364 struct out_operand *out)
366 out->type = OUTOPER_NORMAL;
368 switch (oper->type) {
370 out->u.operand = generate_imm_operand(ctx, oper->u.imm);
373 out->u.operand = generate_reg_operand(ctx, oper->u.reg);
376 out->u.operand = generate_mem_operand(ctx, oper->u.mem);
379 out->type = OUTOPER_LABELREF;
380 out->u.label = oper->u.label;
383 out->u.operand = oper->u.addr->addr;
386 out->u.operand = oper->u.raw;
389 asm_error(ctx, "generate_operand() operstate");
393 static struct code_output * do_assemble_insn(struct assembler_context *ctx,
394 struct instruction *insn,
401 struct code_output *out;
402 struct label *labelref = NULL;
403 struct operand *oper;
404 int have_spr_operand = 0;
405 int have_mem_operand = 0;
407 out = xmalloc(sizeof(*out));
408 INIT_LIST_HEAD(&out->list);
409 out->opcode = opcode;
412 if (ARRAY_SIZE(out->operands) > ARRAY_SIZE(ol->oper))
413 asm_error(ctx, "Internal operand array confusion");
415 for (i = 0; i < ARRAY_SIZE(out->operands); i++) {
420 /* If this is an INPUT operand (first or second), we must
421 * make sure that not both are accessing SPR or MEMORY.
422 * The device only supports one SPR or MEMORY operand in
423 * the input operands. */
424 if ((i == 0) || (i == 1)) {
425 if ((oper->type == OPER_REG) &&
426 (oper->u.reg->type == SPR)) {
427 if (have_spr_operand)
428 asm_error(ctx, "Multiple SPR input operands in one instruction");
429 have_spr_operand = 1;
431 if (oper->type == OPER_MEM) {
432 if (have_mem_operand)
433 asm_error(ctx, "Multiple MEMORY input operands in on instruction");
434 have_mem_operand = 1;
438 generate_operand(ctx, oper, &out->operands[i]);
442 asm_error(ctx, "Internal error: nr_oper at "
443 "lowlevel do_assemble_insn");
445 list_add_tail(&out->list, &ctx->output);
450 static unsigned int merge_ext_into_opcode(struct assembler_context *ctx,
452 struct instruction *insn)
456 unsigned int mask, shift;
460 mask = ol->oper[0]->u.raw;
462 asm_error(ctx, "opcode MASK extension too big (> 0xF)");
463 shift = ol->oper[1]->u.raw;
465 asm_error(ctx, "opcode SHIFT extension too big (> 0xF)");
466 opcode |= (mask << 4);
468 ol->oper[0] = ol->oper[2];
469 ol->oper[1] = ol->oper[3];
470 ol->oper[2] = ol->oper[4];
475 static unsigned int merge_external_jmp_into_opcode(struct assembler_context *ctx,
477 struct instruction *insn)
479 struct operand *fake;
480 struct registr *fake_reg;
481 struct operand *target;
488 cond = ol->oper[0]->u.imm->imm;
490 asm_error(ctx, "External jump condition value too big (> 0xFF)");
492 target = ol->oper[1];
493 memset(ol->oper, 0, sizeof(ol->oper));
495 /* This instruction has two fake r0 operands
496 * at position 0 and 1. */
497 fake = xmalloc(sizeof(*fake));
498 fake_reg = xmalloc(sizeof(*fake_reg));
499 fake->type = OPER_REG;
500 fake->u.reg = fake_reg;
501 fake_reg->type = GPR;
506 ol->oper[2] = target;
511 static void assemble_instruction(struct assembler_context *ctx,
512 struct instruction *insn);
514 static void emulate_mov_insn(struct assembler_context *ctx,
515 struct instruction *insn)
517 struct instruction em_insn;
518 struct operlist em_ol;
519 struct operand em_op_shift;
520 struct operand em_op_mask;
521 struct operand em_op_x;
522 struct operand em_op_y;
523 struct immediate em_imm_x;
524 struct immediate em_imm_y;
526 struct operand *in, *out;
529 /* This is a pseudo-OP. We emulate it by OR or ORX */
531 in = insn->operands->oper[0];
532 out = insn->operands->oper[1];
537 em_op_x.type = OPER_IMM;
538 em_op_x.u.imm = &em_imm_x;
539 em_ol.oper[1] = &em_op_x;
542 if (in->type == OPER_IMM) {
543 tmp = in->u.imm->imm;
544 if (!is_possible_imm(tmp))
545 asm_error(ctx, "MOV operand 0x%X > 16bit", tmp);
546 if (!is_valid_imm(ctx, tmp)) {
547 /* Immediate too big for plain OR */
550 em_op_mask.type = OPER_RAW;
551 em_op_mask.u.raw = 0x7;
552 em_op_shift.type = OPER_RAW;
553 em_op_shift.u.raw = 0x8;
555 em_imm_x.imm = (tmp & 0xFF00) >> 8;
556 em_op_x.type = OPER_IMM;
557 em_op_x.u.imm = &em_imm_x;
559 em_imm_y.imm = (tmp & 0x00FF);
560 em_op_y.type = OPER_IMM;
561 em_op_y.u.imm = &em_imm_y;
563 em_ol.oper[0] = &em_op_mask;
564 em_ol.oper[1] = &em_op_shift;
565 em_ol.oper[2] = &em_op_x;
566 em_ol.oper[3] = &em_op_y;
571 em_insn.operands = &em_ol;
572 assemble_instruction(ctx, &em_insn); /* recurse */
575 static void emulate_jmp_insn(struct assembler_context *ctx,
576 struct instruction *insn)
578 struct instruction em_insn;
579 struct operlist em_ol;
580 struct immediate em_condition;
581 struct operand em_cond_op;
583 /* This is a pseudo-OP. We emulate it with
584 * JEXT 0x7F, target */
586 em_insn.op = OP_JEXT;
587 em_condition.imm = 0x7F; /* Ext cond: Always true */
588 em_cond_op.type = OPER_IMM;
589 em_cond_op.u.imm = &em_condition;
590 em_ol.oper[0] = &em_cond_op;
591 em_ol.oper[1] = insn->operands->oper[0]; /* Target */
592 em_insn.operands = &em_ol;
594 assemble_instruction(ctx, &em_insn); /* recurse */
597 static void emulate_jand_insn(struct assembler_context *ctx,
598 struct instruction *insn,
601 struct code_output *out;
602 struct instruction em_insn;
603 struct operlist em_ol;
604 struct operand em_op_shift;
605 struct operand em_op_mask;
606 struct operand em_op_y;
607 struct immediate em_imm;
609 struct operand *oper0, *oper1, *oper2;
610 struct operand *imm_oper = NULL;
612 int first_bit, last_bit;
614 oper0 = insn->operands->oper[0];
615 oper1 = insn->operands->oper[1];
616 oper2 = insn->operands->oper[2];
618 if (oper0->type == OPER_IMM)
620 if (oper1->type == OPER_IMM)
622 if (oper0->type == OPER_IMM && oper1->type == OPER_IMM)
626 /* We have a single immediate operand.
627 * Check if it's representable by a normal JAND insn.
629 tmp = imm_oper->u.imm->imm;
630 if (!is_valid_imm(ctx, tmp)) {
631 /* Nope, this must be emulated by JZX/JNZX */
632 if (!is_contiguous_bitmask(tmp)) {
633 asm_error(ctx, "Long bitmask 0x%X is not contiguous",
637 first_bit = ffs(tmp);
638 last_bit = ffs(~(tmp >> (first_bit - 1))) - 1 + first_bit - 1;
643 em_insn.op = OP_JNZX;
644 em_op_shift.type = OPER_RAW;
645 em_op_shift.u.raw = first_bit - 1;
646 em_op_mask.type = OPER_RAW;
647 em_op_mask.u.raw = last_bit - first_bit;
650 em_op_y.type = OPER_IMM;
651 em_op_y.u.imm = &em_imm;
653 em_ol.oper[0] = &em_op_mask;
654 em_ol.oper[1] = &em_op_shift;
655 if (oper0->type != OPER_IMM)
656 em_ol.oper[2] = oper0;
658 em_ol.oper[2] = oper1;
659 em_ol.oper[3] = &em_op_y;
660 em_ol.oper[4] = oper2;
662 em_insn.operands = &em_ol;
664 assemble_instruction(ctx, &em_insn); /* recurse */
669 /* Do a normal JAND/JNAND instruction */
671 out = do_assemble_insn(ctx, insn, 0x040 | 0x1);
673 out = do_assemble_insn(ctx, insn, 0x040);
674 out->is_jump_insn = 1;
677 static void assemble_instruction(struct assembler_context *ctx,
678 struct instruction *insn)
680 struct code_output *out;
685 do_assemble_insn(ctx, insn, 0x1C0);
688 do_assemble_insn(ctx, insn, 0x1C2);
691 do_assemble_insn(ctx, insn, 0x1C1);
694 do_assemble_insn(ctx, insn, 0x1C3);
697 do_assemble_insn(ctx, insn, 0x1D0);
700 do_assemble_insn(ctx, insn, 0x1D2);
703 do_assemble_insn(ctx, insn, 0x1D1);
706 do_assemble_insn(ctx, insn, 0x1D3);
709 do_assemble_insn(ctx, insn, 0x130);
712 do_assemble_insn(ctx, insn, 0x160);
715 do_assemble_insn(ctx, insn, 0x140);
718 do_assemble_insn(ctx, insn, 0x170);
721 do_assemble_insn(ctx, insn, 0x120);
724 opcode = merge_ext_into_opcode(ctx, 0x200, insn);
725 do_assemble_insn(ctx, insn, opcode);
728 do_assemble_insn(ctx, insn, 0x110);
731 do_assemble_insn(ctx, insn, 0x1A0);
734 do_assemble_insn(ctx, insn, 0x1B0);
737 do_assemble_insn(ctx, insn, 0x150);
740 opcode = merge_ext_into_opcode(ctx, 0x300, insn);
741 do_assemble_insn(ctx, insn, opcode);
744 emulate_mov_insn(ctx, insn);
747 emulate_jmp_insn(ctx, insn);
750 emulate_jand_insn(ctx, insn, 0);
753 emulate_jand_insn(ctx, insn, 1);
756 out = do_assemble_insn(ctx, insn, 0x050);
757 out->is_jump_insn = 1;
760 out = do_assemble_insn(ctx, insn, 0x050 | 0x1);
761 out->is_jump_insn = 1;
764 out = do_assemble_insn(ctx, insn, 0x0D0);
765 out->is_jump_insn = 1;
768 out = do_assemble_insn(ctx, insn, 0x0D0 | 0x1);
769 out->is_jump_insn = 1;
772 out = do_assemble_insn(ctx, insn, 0x0D2);
773 out->is_jump_insn = 1;
776 out = do_assemble_insn(ctx, insn, 0x0D2 | 0x1);
777 out->is_jump_insn = 1;
780 out = do_assemble_insn(ctx, insn, 0x0D4);
781 out->is_jump_insn = 1;
784 out = do_assemble_insn(ctx, insn, 0x0D4 | 0x1);
785 out->is_jump_insn = 1;
788 out = do_assemble_insn(ctx, insn, 0x0DA);
789 out->is_jump_insn = 1;
792 out = do_assemble_insn(ctx, insn, 0x0DA | 0x1);
793 out->is_jump_insn = 1;
796 out = do_assemble_insn(ctx, insn, 0x0DC);
799 out = do_assemble_insn(ctx, insn, 0x0DC | 0x1);
800 out->is_jump_insn = 1;
803 opcode = merge_ext_into_opcode(ctx, 0x400, insn);
804 out = do_assemble_insn(ctx, insn, opcode);
805 out->is_jump_insn = 1;
808 opcode = merge_ext_into_opcode(ctx, 0x500, insn);
809 out = do_assemble_insn(ctx, insn, opcode);
810 out->is_jump_insn = 1;
813 opcode = merge_external_jmp_into_opcode(ctx, 0x700, insn);
814 out = do_assemble_insn(ctx, insn, opcode);
815 out->is_jump_insn = 1;
818 opcode = merge_external_jmp_into_opcode(ctx, 0x600, insn);
819 out = do_assemble_insn(ctx, insn, opcode);
820 out->is_jump_insn = 1;
823 do_assemble_insn(ctx, insn, 0x002);
826 /* Get the previous instruction and check whether it
827 * is a jump instruction. */
828 list_for_each_entry_reverse(out, &ctx->output, list) {
829 /* Search the last insn. */
830 if (out->type == OUT_INSN) {
831 if (out->is_jump_insn) {
832 asm_warn(ctx, "RET instruction directly after "
833 "jump instruction. The hardware won't like this.");
838 do_assemble_insn(ctx, insn, 0x003);
844 do_assemble_insn(ctx, insn, 0x1E0);
847 do_assemble_insn(ctx, insn, 0x001);
850 do_assemble_insn(ctx, insn, insn->opcode);
853 asm_error(ctx, "Unknown op");
857 static void assemble_instructions(struct assembler_context *ctx)
860 struct instruction *insn;
861 struct code_output *out;
863 if (ctx->start_label) {
864 /* Generate a jump instruction at offset 0 to
865 * jump to the code start.
867 struct instruction sjmp;
871 oper.type = OPER_LABEL;
872 oper.u.label = ctx->start_label;
877 assemble_instruction(ctx, &sjmp);
878 out = list_entry(ctx->output.next, struct code_output, list);
879 out->is_start_insn = 1;
882 for_each_statement(ctx, s) {
887 assemble_instruction(ctx, insn);
890 out = xmalloc(sizeof(*out));
891 INIT_LIST_HEAD(&out->list);
892 out->type = OUT_LABEL;
893 out->labelname = s->u.label->name;
895 list_add_tail(&out->list, &ctx->output);
900 } for_each_statement_end(ctx, s);
903 /* Resolve a label reference to the address it points to. */
904 static int get_labeladdress(struct assembler_context *ctx,
905 struct code_output *this_insn,
906 struct label *labelref)
908 struct code_output *c;
912 switch (labelref->direction) {
913 case LABELREF_ABSOLUTE:
914 list_for_each_entry(c, &ctx->output, list) {
915 if (c->type != OUT_LABEL)
917 if (strcmp(c->labelname, labelref->name) != 0)
920 asm_error(ctx, "Ambiguous label reference \"%s\"",
924 address = c->address;
927 case LABELREF_RELATIVE_BACK:
928 for (c = list_entry(this_insn->list.prev, typeof(*c), list);
929 &c->list != &ctx->output;
930 c = list_entry(c->list.prev, typeof(*c), list)) {
931 if (c->type != OUT_LABEL)
933 if (strcmp(c->labelname, labelref->name) == 0) {
935 address = c->address;
940 case LABELREF_RELATIVE_FORWARD:
941 for (c = list_entry(this_insn->list.next, typeof(*c), list);
942 &c->list != &ctx->output;
943 c = list_entry(c->list.next, typeof(*c), list)) {
944 if (c->type != OUT_LABEL)
946 if (strcmp(c->labelname, labelref->name) == 0) {
948 address = c->address;
958 static void resolve_labels(struct assembler_context *ctx)
960 struct code_output *c;
963 unsigned int current_address;
965 /* Calculate the absolute addresses for each instruction. */
966 recalculate_addresses:
968 list_for_each_entry(c, &ctx->output, list) {
971 c->address = current_address;
975 c->address = current_address;
980 /* Resolve the symbolic label references. */
981 list_for_each_entry(c, &ctx->output, list) {
984 if (c->is_start_insn) {
985 /* If the first %start-jump jumps to 001, we can
986 * optimize it away, as it's unneeded.
989 if (c->operands[i].type != OUTOPER_LABELREF)
990 asm_error(ctx, "Internal error, %%start insn oper 2 not labelref");
991 if (c->operands[i].u.label->direction != LABELREF_ABSOLUTE)
992 asm_error(ctx, "%%start label reference not absolute");
993 addr = get_labeladdress(ctx, c, c->operands[i].u.label);
997 list_del(&c->list); /* Kill it */
998 goto recalculate_addresses;
1002 for (i = 0; i < ARRAY_SIZE(c->operands); i++) {
1003 if (c->operands[i].type != OUTOPER_LABELREF)
1005 addr = get_labeladdress(ctx, c, c->operands[i].u.label);
1007 goto does_not_exist;
1008 c->operands[i].u.operand = addr;
1010 /* Is not a jump target.
1011 * Make it be an immediate */
1013 c->operands[i].u.operand |= 0xC00;
1014 else if (ctx->arch == 15)
1015 c->operands[i].u.operand |= 0xC00 << 1;
1017 asm_error(ctx, "Internal error: label res imm");
1028 asm_error(ctx, "Label \"%s\" does not exist",
1029 c->operands[i].u.label->name);
1032 static void emit_code(struct assembler_context *ctx)
1036 struct code_output *c;
1038 unsigned char outbuf[8];
1039 unsigned int insn_count = 0;
1040 struct fw_header hdr;
1043 fd = fopen(fn, "w+");
1045 fprintf(stderr, "Could not open microcode output file \"%s\"\n", fn);
1048 if (IS_VERBOSE_DEBUG)
1049 fprintf(stderr, "\nCode:\n");
1051 list_for_each_entry(c, &ctx->output, list) {
1061 memset(&hdr, 0, sizeof(hdr));
1062 hdr.type = FW_TYPE_UCODE;
1063 hdr.ver = FW_HDR_VER;
1064 hdr.size = cpu_to_be32(8 * insn_count);
1065 if (fwrite(&hdr, sizeof(hdr), 1, fd) != 1) {
1066 fprintf(stderr, "Could not write microcode outfile\n");
1070 if (insn_count > NUM_INSN_LIMIT)
1071 asm_warn(ctx, "Generating more than %d instructions. This "
1072 "will overflow the device microcode memory.",
1075 list_for_each_entry(c, &ctx->output, list) {
1078 if (IS_VERBOSE_DEBUG) {
1079 fprintf(stderr, "%03X %03X,%03X,%03X\n",
1081 c->operands[0].u.operand,
1082 c->operands[1].u.operand,
1083 c->operands[2].u.operand);
1087 if (ctx->arch == 5) {
1088 /* Instruction binary format is: xxyyyzzz0000oooX
1091 * Xxx is the first operand
1092 * yyy is the second operand
1093 * zzz is the third operand
1095 code |= ((uint64_t)c->operands[2].u.operand);
1096 code |= ((uint64_t)c->operands[1].u.operand) << 12;
1097 code |= ((uint64_t)c->operands[0].u.operand) << 24;
1098 code |= ((uint64_t)c->opcode) << 36;
1099 code = ((code & (uint64_t)0xFFFFFFFF00000000ULL) >> 32) |
1100 ((code & (uint64_t)0x00000000FFFFFFFFULL) << 32);
1101 } else if (ctx->arch == 15) {
1102 code |= ((uint64_t)c->operands[2].u.operand);
1103 code |= ((uint64_t)c->operands[1].u.operand) << 13;
1104 code |= ((uint64_t)c->operands[0].u.operand) << 26;
1105 code |= ((uint64_t)c->opcode) << 39;
1106 code = ((code & (uint64_t)0xFFFFFFFF00000000ULL) >> 32) |
1107 ((code & (uint64_t)0x00000000FFFFFFFFULL) << 32);
1109 asm_error(ctx, "No emit format for arch %u",
1112 outbuf[0] = (code & (uint64_t)0xFF00000000000000ULL) >> 56;
1113 outbuf[1] = (code & (uint64_t)0x00FF000000000000ULL) >> 48;
1114 outbuf[2] = (code & (uint64_t)0x0000FF0000000000ULL) >> 40;
1115 outbuf[3] = (code & (uint64_t)0x000000FF00000000ULL) >> 32;
1116 outbuf[4] = (code & (uint64_t)0x00000000FF000000ULL) >> 24;
1117 outbuf[5] = (code & (uint64_t)0x0000000000FF0000ULL) >> 16;
1118 outbuf[6] = (code & (uint64_t)0x000000000000FF00ULL) >> 8;
1119 outbuf[7] = (code & (uint64_t)0x00000000000000FFULL) >> 0;
1121 if (fwrite(&outbuf, ARRAY_SIZE(outbuf), 1, fd) != 1) {
1122 fprintf(stderr, "Could not write microcode outfile\n");
1131 if (arg_print_sizes) {
1132 printf("%s: text = %u instructions (%u bytes)\n",
1134 (unsigned int)(insn_count * sizeof(uint64_t)));
1140 static void assemble(void)
1142 struct assembler_context ctx;
1144 memset(&ctx, 0, sizeof(ctx));
1145 INIT_LIST_HEAD(&ctx.output);
1147 eval_directives(&ctx);
1148 assemble_instructions(&ctx);
1149 resolve_labels(&ctx);
1153 static void initialize(void)
1155 INIT_LIST_HEAD(&infile.sl);
1156 INIT_LIST_HEAD(&infile.ivals);
1158 if (IS_INSANE_DEBUG)
1162 #endif /* YYDEBUG */
1165 int main(int argc, char **argv)
1169 err = parse_args(argc, argv);
1176 err = open_input_file();
1182 assemble_initvals();
1186 /* Lazyman simply leaks all allocated memory. */