GNU Linux-libre 4.4.295-gnu1
[releases.git] / arch / arm / mach-omap1 / dma.c
1 /*
2  * OMAP1/OMAP7xx - specific DMA driver
3  *
4  * Copyright (C) 2003 - 2008 Nokia Corporation
5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7  * Graphics DMA and LCD DMA graphics tranformations
8  * by Imre Deak <imre.deak@nokia.com>
9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
11  *
12  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
13  * Converted DMA library into platform driver
14  *                   - G, Manjunath Kondaiah <manjugk@ti.com>
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
20
21 #include <linux/err.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/device.h>
26 #include <linux/io.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/omap-dma.h>
29 #include <mach/tc.h>
30
31 #include "soc.h"
32
33 #define OMAP1_DMA_BASE                  (0xfffed800)
34
35 static u32 enable_1510_mode;
36
37 static const struct omap_dma_reg reg_map[] = {
38         [GCR]           = { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
39         [GSCR]          = { 0x0404, 0x00, OMAP_DMA_REG_16BIT },
40         [GRST1]         = { 0x0408, 0x00, OMAP_DMA_REG_16BIT },
41         [HW_ID]         = { 0x0442, 0x00, OMAP_DMA_REG_16BIT },
42         [PCH2_ID]       = { 0x0444, 0x00, OMAP_DMA_REG_16BIT },
43         [PCH0_ID]       = { 0x0446, 0x00, OMAP_DMA_REG_16BIT },
44         [PCH1_ID]       = { 0x0448, 0x00, OMAP_DMA_REG_16BIT },
45         [PCHG_ID]       = { 0x044a, 0x00, OMAP_DMA_REG_16BIT },
46         [PCHD_ID]       = { 0x044c, 0x00, OMAP_DMA_REG_16BIT },
47         [CAPS_0]        = { 0x044e, 0x00, OMAP_DMA_REG_2X16BIT },
48         [CAPS_1]        = { 0x0452, 0x00, OMAP_DMA_REG_2X16BIT },
49         [CAPS_2]        = { 0x0456, 0x00, OMAP_DMA_REG_16BIT },
50         [CAPS_3]        = { 0x0458, 0x00, OMAP_DMA_REG_16BIT },
51         [CAPS_4]        = { 0x045a, 0x00, OMAP_DMA_REG_16BIT },
52         [PCH2_SR]       = { 0x0460, 0x00, OMAP_DMA_REG_16BIT },
53         [PCH0_SR]       = { 0x0480, 0x00, OMAP_DMA_REG_16BIT },
54         [PCH1_SR]       = { 0x0482, 0x00, OMAP_DMA_REG_16BIT },
55         [PCHD_SR]       = { 0x04c0, 0x00, OMAP_DMA_REG_16BIT },
56
57         /* Common Registers */
58         [CSDP]          = { 0x0000, 0x40, OMAP_DMA_REG_16BIT },
59         [CCR]           = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
60         [CICR]          = { 0x0004, 0x40, OMAP_DMA_REG_16BIT },
61         [CSR]           = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
62         [CEN]           = { 0x0010, 0x40, OMAP_DMA_REG_16BIT },
63         [CFN]           = { 0x0012, 0x40, OMAP_DMA_REG_16BIT },
64         [CSFI]          = { 0x0014, 0x40, OMAP_DMA_REG_16BIT },
65         [CSEI]          = { 0x0016, 0x40, OMAP_DMA_REG_16BIT },
66         [CPC]           = { 0x0018, 0x40, OMAP_DMA_REG_16BIT }, /* 15xx only */
67         [CSAC]          = { 0x0018, 0x40, OMAP_DMA_REG_16BIT },
68         [CDAC]          = { 0x001a, 0x40, OMAP_DMA_REG_16BIT },
69         [CDEI]          = { 0x001c, 0x40, OMAP_DMA_REG_16BIT },
70         [CDFI]          = { 0x001e, 0x40, OMAP_DMA_REG_16BIT },
71         [CLNK_CTRL]     = { 0x0028, 0x40, OMAP_DMA_REG_16BIT },
72
73         /* Channel specific register offsets */
74         [CSSA]          = { 0x0008, 0x40, OMAP_DMA_REG_2X16BIT },
75         [CDSA]          = { 0x000c, 0x40, OMAP_DMA_REG_2X16BIT },
76         [COLOR]         = { 0x0020, 0x40, OMAP_DMA_REG_2X16BIT },
77         [CCR2]          = { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
78         [LCH_CTRL]      = { 0x002a, 0x40, OMAP_DMA_REG_16BIT },
79 };
80
81 static struct resource res[] __initdata = {
82         [0] = {
83                 .start  = OMAP1_DMA_BASE,
84                 .end    = OMAP1_DMA_BASE + SZ_2K - 1,
85                 .flags  = IORESOURCE_MEM,
86         },
87         [1] = {
88                 .name   = "0",
89                 .start  = INT_DMA_CH0_6,
90                 .flags  = IORESOURCE_IRQ,
91         },
92         [2] = {
93                 .name   = "1",
94                 .start  = INT_DMA_CH1_7,
95                 .flags  = IORESOURCE_IRQ,
96         },
97         [3] = {
98                 .name   = "2",
99                 .start  = INT_DMA_CH2_8,
100                 .flags  = IORESOURCE_IRQ,
101         },
102         [4] = {
103                 .name   = "3",
104                 .start  = INT_DMA_CH3,
105                 .flags  = IORESOURCE_IRQ,
106         },
107         [5] = {
108                 .name   = "4",
109                 .start  = INT_DMA_CH4,
110                 .flags  = IORESOURCE_IRQ,
111         },
112         [6] = {
113                 .name   = "5",
114                 .start  = INT_DMA_CH5,
115                 .flags  = IORESOURCE_IRQ,
116         },
117         /* Handled in lcd_dma.c */
118         [7] = {
119                 .name   = "6",
120                 .start  = INT_1610_DMA_CH6,
121                 .flags  = IORESOURCE_IRQ,
122         },
123         /* irq's for omap16xx and omap7xx */
124         [8] = {
125                 .name   = "7",
126                 .start  = INT_1610_DMA_CH7,
127                 .flags  = IORESOURCE_IRQ,
128         },
129         [9] = {
130                 .name   = "8",
131                 .start  = INT_1610_DMA_CH8,
132                 .flags  = IORESOURCE_IRQ,
133         },
134         [10] = {
135                 .name  = "9",
136                 .start = INT_1610_DMA_CH9,
137                 .flags = IORESOURCE_IRQ,
138         },
139         [11] = {
140                 .name  = "10",
141                 .start = INT_1610_DMA_CH10,
142                 .flags = IORESOURCE_IRQ,
143         },
144         [12] = {
145                 .name  = "11",
146                 .start = INT_1610_DMA_CH11,
147                 .flags = IORESOURCE_IRQ,
148         },
149         [13] = {
150                 .name  = "12",
151                 .start = INT_1610_DMA_CH12,
152                 .flags = IORESOURCE_IRQ,
153         },
154         [14] = {
155                 .name  = "13",
156                 .start = INT_1610_DMA_CH13,
157                 .flags = IORESOURCE_IRQ,
158         },
159         [15] = {
160                 .name  = "14",
161                 .start = INT_1610_DMA_CH14,
162                 .flags = IORESOURCE_IRQ,
163         },
164         [16] = {
165                 .name  = "15",
166                 .start = INT_1610_DMA_CH15,
167                 .flags = IORESOURCE_IRQ,
168         },
169         [17] = {
170                 .name  = "16",
171                 .start = INT_DMA_LCD,
172                 .flags = IORESOURCE_IRQ,
173         },
174 };
175
176 static void __iomem *dma_base;
177 static inline void dma_write(u32 val, int reg, int lch)
178 {
179         void __iomem *addr = dma_base;
180
181         addr += reg_map[reg].offset;
182         addr += reg_map[reg].stride * lch;
183
184         __raw_writew(val, addr);
185         if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
186                 __raw_writew(val >> 16, addr + 2);
187 }
188
189 static inline u32 dma_read(int reg, int lch)
190 {
191         void __iomem *addr = dma_base;
192         uint32_t val;
193
194         addr += reg_map[reg].offset;
195         addr += reg_map[reg].stride * lch;
196
197         val = __raw_readw(addr);
198         if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
199                 val |= __raw_readw(addr + 2) << 16;
200
201         return val;
202 }
203
204 static void omap1_clear_lch_regs(int lch)
205 {
206         int i;
207
208         for (i = CPC; i <= COLOR; i += 1)
209                 dma_write(0, i, lch);
210 }
211
212 static void omap1_clear_dma(int lch)
213 {
214         u32 l;
215
216         l = dma_read(CCR, lch);
217         l &= ~OMAP_DMA_CCR_EN;
218         dma_write(l, CCR, lch);
219
220         /* Clear pending interrupts */
221         l = dma_read(CSR, lch);
222 }
223
224 static void omap1_show_dma_caps(void)
225 {
226         if (enable_1510_mode) {
227                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
228         } else {
229                 u16 w;
230                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
231                                                         dma_read(HW_ID, 0));
232                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
233                         dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
234                         dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
235                         dma_read(CAPS_4, 0));
236
237                 /* Disable OMAP 3.0/3.1 compatibility mode. */
238                 w = dma_read(GSCR, 0);
239                 w |= 1 << 3;
240                 dma_write(w, GSCR, 0);
241         }
242         return;
243 }
244
245 static unsigned configure_dma_errata(void)
246 {
247         unsigned errata = 0;
248
249         /*
250          * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
251          * read before the DMA controller finished disabling the channel.
252          */
253         if (!cpu_is_omap15xx())
254                 SET_DMA_ERRATA(DMA_ERRATA_3_3);
255
256         return errata;
257 }
258
259 static const struct platform_device_info omap_dma_dev_info = {
260         .name = "omap-dma-engine",
261         .id = -1,
262         .dma_mask = DMA_BIT_MASK(32),
263         .res = res,
264         .num_res = 1,
265 };
266
267 static struct omap_system_dma_plat_info dma_plat_info __initdata = {
268         .reg_map        = reg_map,
269         .channel_stride = 0x40,
270         .show_dma_caps  = omap1_show_dma_caps,
271         .clear_lch_regs = omap1_clear_lch_regs,
272         .clear_dma      = omap1_clear_dma,
273         .dma_write      = dma_write,
274         .dma_read       = dma_read,
275 };
276
277 static int __init omap1_system_dma_init(void)
278 {
279         struct omap_system_dma_plat_info        p;
280         struct omap_dma_dev_attr                *d;
281         struct platform_device                  *pdev, *dma_pdev;
282         int ret;
283
284         pdev = platform_device_alloc("omap_dma_system", 0);
285         if (!pdev) {
286                 pr_err("%s: Unable to device alloc for dma\n",
287                         __func__);
288                 return -ENOMEM;
289         }
290
291         dma_base = ioremap(res[0].start, resource_size(&res[0]));
292         if (!dma_base) {
293                 pr_err("%s: Unable to ioremap\n", __func__);
294                 ret = -ENODEV;
295                 goto exit_device_put;
296         }
297
298         ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
299         if (ret) {
300                 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
301                         __func__, pdev->name, pdev->id);
302                 goto exit_iounmap;
303         }
304
305         d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
306         if (!d) {
307                 dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
308                         __func__, pdev->name);
309                 ret = -ENOMEM;
310                 goto exit_iounmap;
311         }
312
313         /* Valid attributes for omap1 plus processors */
314         if (cpu_is_omap15xx())
315                 d->dev_caps = ENABLE_1510_MODE;
316         enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
317
318         if (cpu_is_omap16xx())
319                 d->dev_caps = ENABLE_16XX_MODE;
320
321         d->dev_caps             |= SRC_PORT;
322         d->dev_caps             |= DST_PORT;
323         d->dev_caps             |= SRC_INDEX;
324         d->dev_caps             |= DST_INDEX;
325         d->dev_caps             |= IS_BURST_ONLY4;
326         d->dev_caps             |= CLEAR_CSR_ON_READ;
327         d->dev_caps             |= IS_WORD_16;
328
329         /* available logical channels */
330         if (cpu_is_omap15xx()) {
331                 d->lch_count = 9;
332         } else {
333                 if (d->dev_caps & ENABLE_1510_MODE)
334                         d->lch_count = 9;
335                 else
336                         d->lch_count = 16;
337         }
338
339         p = dma_plat_info;
340         p.dma_attr = d;
341         p.errata = configure_dma_errata();
342
343         ret = platform_device_add_data(pdev, &p, sizeof(p));
344         if (ret) {
345                 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
346                         __func__, pdev->name, pdev->id);
347                 goto exit_release_d;
348         }
349
350         ret = platform_device_add(pdev);
351         if (ret) {
352                 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
353                         __func__, pdev->name, pdev->id);
354                 goto exit_release_d;
355         }
356
357         dma_pdev = platform_device_register_full(&omap_dma_dev_info);
358         if (IS_ERR(dma_pdev)) {
359                 ret = PTR_ERR(dma_pdev);
360                 goto exit_release_pdev;
361         }
362
363         return ret;
364
365 exit_release_pdev:
366         platform_device_del(pdev);
367 exit_release_d:
368         kfree(d);
369 exit_iounmap:
370         iounmap(dma_base);
371 exit_device_put:
372         platform_device_put(pdev);
373
374         return ret;
375 }
376 arch_initcall(omap1_system_dma_init);